entity dan architecture LIBRARY ieee; USE ieee.std_logic_1164.

ALL; ENTITY decoder IS PORT( d : IN STD_LOGIC_VECTOR (3 downto 0); y : OUT STD_LOGIC); END decoder; ARCHITECTURE decoder2 OF decoder IS BEGIN WITH d SELECT y <= '1' WHEN "0000", '1' WHEN "0100", '1' WHEN "1001", '0' WHEN others; END decoder2; test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY tb IS end ENTITY tb; ARCHITECTURE tb_ARCH OF tb IS Signal d : STD_LOGIC_VECTOR (3 downto 0); Signal y : STD_LOGIC; Begin M : ENTITY work.decoder (decoder2) Port Map ( d => d, y => y ); Stimulus : Process IS begin d <= "0000", "0100" after 10 ns, "1001" after 20 ns, "0010" after 30 ns, "0011" after 40 ns; wait; end process Stimulus; end ARCHITECTURE tb_ARCH;