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    This document outlines the contents and organization of a thesis on designing a cryptographic processor using the BLAKE hash function and RSA algorithm. Chapter 1 introduces cryptographic concepts like symmetric and asymmetric encryption, hash functions, and Network-on-Chip. It describes the need for cryptographic processors, states the objectives of designing a more secure reconfigurable processor, and outlines the organization of the thesis. Chapter 2 covers related work and literature survey. Chapter 3 details the design of the proposed cryptographic processor architecture, operation of the RSA and BLAKE algorithms, VHDL implementation, and use of the Modelsim software tool for simulation.

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    This document outlines the contents and organization of a thesis on designing a cryptographic processor using the BLAKE hash function and RSA algorithm. Chapter 1 introduces cryptographic concepts like symmetric and asymmetric encryption, hash functions, and Network-on-Chip. It describes the need for cryptographic processors, states the objectives of designing a more secure reconfigurable processor, and outlines the organization of the thesis. Chapter 2 covers related work and literature survey. Chapter 3 details the design of the proposed cryptographic processor architecture, operation of the RSA and BLAKE algorithms, VHDL implementation, and use of the Modelsim software tool for simulation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    Download as doc, pdf, or txt
    16 views4 pages

    Chapter No

    Uploaded by

    art101988
    This document outlines the contents and organization of a thesis on designing a cryptographic processor using the BLAKE hash function and RSA algorithm. Chapter 1 introduces cryptographic concepts like symmetric and asymmetric encryption, hash functions, and Network-on-Chip. It describes the need for cryptographic processors, states the objectives of designing a more secure reconfigurable processor, and outlines the organization of the thesis. Chapter 2 covers related work and literature survey. Chapter 3 details the design of the proposed cryptographic processor architecture, operation of the RSA and BLAKE algorithms, VHDL implementation, and use of the Modelsim software tool for simulation.

    Copyright:

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    of 4

    TABLE OF CONTENTS

    CHAPTER NO

    TITLE ABSTRACT LIST OF TABLES LIST OF FIGURES INTRODUTION 1.1 Overview of the project 1.1.1 Symmetric key encryption technique 1.1.2 Asymmetric key encryption technique 1.1.3 Cryptographic hash function 1.1.4 Applications of cryptographic hash functions 1.2 Network- On- Chip 1.2.1 Benefits of Network-On-Chip 1.3 Introduction to VLSI systems 1.4 Cryptographic Processor 1.4.1 Need for the cryptographic processors 1.5 Statement of work 1.5.1 Existing system 1.5.2 Drawbacks of the existing system 1.5.3 Proposed system 1.5.4 Advantages of proposed system v

    PAGE NO iii vii viii 1 1 2 3 4 4 5 5 6 6 7 7 7 8 9 9

    1.6 Objective of the project 1.7 Organization of the thesis

    9 10

    LITERATURE SURVEY 2.1 Introduction 2.2 Survey DESIGNING 3.1 Overall architecture 3.2 RSA algorithm 3.3 Current hash functions background 3.4 BLAKE hash functions 3.4.1 Message padding 3.4.2 Counter 3.4.3 State initialization 3.4.4 State update 3.4.5 G-function 3.4.6 Finalization 3.5 VHDL implementation 3.5.1 VHDL language 3.5.2 Design units 3.6 Software tool 3.6.1 Modelsim RESULTS CONCLUSION REFERENCES vi

    11 11 11 18 18 20 25 26 29 30 31 32 33 36 38 38 38 39 39 42 48 49

    4 5

    LIST OF TABLES

    TABLE NO 3.1 3.2 3.3 3.4 3.5

    TITLE RSA algorithm method public and private key pairs Permutation table (rc) Blake constants Finalization Blakes Initialization Vector

    PAGE NO 23 35 36 37 37

    vii

    LIST OF FIGURES FIGURE NO 1.1 1.2 1.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.1 4.2 4.3 4.4 TITLE Symmetric Key Encryption Technique Asymmetric Key Encryption Technique Functional flow diagram of existing system Block diagram of the cryptographic processor Proposed architecture for more secured reconfigurable cryptographic processor Example for RSA Algorithm
    Top level diagram of Blake State initialization

    PAGE NO 2 3 8 18 19 25 27 32 33 34 40 41 42 43 44 46

    State update: columns and diagonals


    G-function

    Basic steps for simulating a design in ModelSim Modelsim software Prime no generation in RSA Encryption and Decryption process in RSA Blake encryption Blake decryption

    viii

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