Step7 Jeld1 Farsi

STEP7
( )
:
:
STEP7
( )
:
:
. ....
.
( Step7 )

. Step7

.
PLC
.
PLC
. S7 PLC
ST SFC
FBD STL LAD
PID
Step7 .

.

.

.

reza.maher@gmail.com
PLC
IEC1131
PLC
S7
-
-
-
-
Step7
Step5 Step7
Step7
Step7
Step7 -
Step7
Step7
Simatic Manager
Hwconfig -
S7-300
S7-400
PLC
S7
S7
S7
CPU S7
Simatic Manager
LAD/STL/FBD
Reference Data
Rewiring
Word
SFB3
n -
Address Register
PLC On-Line
Upload PLC Download
-
-
Simatic Manager On-Line
Hwconfig On-Line
LAD/STL/FBD On-Line
IEC1131
STL
S7-400

S5 S7

:
PLC -
IEC1131
PLC -
S7
Step7 -
Step5 Step7
Step7
Step7
Step7 -
PLC
PLC -
Programmable Controller Programmable Logic Controller PLC
.
.
. CPU PLC
CPU ( 1 0 ) Field

CPU .
.
. (Actuators) Field
(Hard-wired)
PLC
.
(Troubleshooting)
PLC
. PLC
.

. PLC ...
. PLC PLC
. (Communication)
. IEC1131 PLC
IEC1131
IEC1131 -
PLC (International Elctro-technical Commission) IEC

.
. PLC
IEC1131
.
PLC .
.
: IEC1131
(General Information) -
( ... HMI ) PLC

... CPU
(Equipment Requirements and Tests)
PLC
PLC .
.
IEC1131
(Programming Languages) -
Integer,Real, Word , Date , Time Byte Bool
(FB) (FC) (Program Organization Units ) POU .
. FB FC FB .

IEC
: . PLC
. PLC Instruction List IL x
.
FBD . Function Block Diagram FBD x
.
.
Ladder Diagram LD x
. FBD LD
C ST . IEC Structured Text ST
.
. Sequential Function Control SFC
Transition Step
. . Step Step
.
.
Sequentioal Function Contrl
(SFC)
Step 1
FILL
InstructionList (IL)
LD
ANDN B
ST
StructuredText (ST)
A
C:= A AND NOTB
Transition 1
Step 2
Empty
FunctionBlock Diagram (FBD)

AND
Transition 2
Step 3
Ladder Diagram(LD)
A B
-| |--|/|----------------( )
(User Guidelines) -
(End User)
. IEC1131
IEC1131
(Communications)
.
.
.
(Fuzzy Control Programming) -

.
(Guidelines for the application of programming languages)
PLC
.
. IEC1131
PLC
PLC -
Compact . SIMATIC PLC
CPU
Compact (Modular) .
.
: PLC
Simatic S5
PLC

Compact
S5-115U S5-100U
S5-95U
S5-90U
.
S5-
PLC
.
S5-155U 135U
. STEP 5 PLC
Simatic S7
S5 PLC
Compact S7-200
S7-300 .
S7-400
.
STEP7 PLC
.
LOGO! Logic Modules
LOGO
( )
Compact PLC .
.
. LOGO! Soft Comfort
PLC
Simatic C7
. Operator Control S7-300 C7

.
C7
.
STEP7 PLC
. Protool
Simatic 505
505

Compact
. TISOFT
. Texas Instruments
. S7
S7
S7 -
S7-200
. micro PLC x
. x
. x
On-Board
I/O Compact x
.
x
. CPU
. Step7-Micro/Win x
S7-300
mini PLc x
. x
x
. x
x
. STEP7 x
S7-300F
x
Fail-Safe
. S7-300 x
F CPU x
CPU 315F
S7-300C
CPU S7-300 x
Compact /
.
C CPU x
CPU 314C
S7
S7-400
. x
x
. x
x
S7-300 x
.
STEP7 x
S7-400H
High Availability S7-400
:
x
.
. x
x
.
CPU Redundant
. (Hot-Standby)
CPU
. CPU
.
.
Step7
. H-System
S7-400FH
S7-400 x
. S7-400H x
F-system x
.
Step7 S7
. S7-200 .
Step7
Step7 -
: Step7
. S7-200 PLC Step7-MicroWin .
. C7 S7-300 , S7-400 Step7
2004 Step7 V5.3 Step7

5.2
Step7 (V5.2)
. Step7V5.1 2002 Step7 V5.2

:

()
RUN V5.2
. ( Configuration in Run) CiR

.
RUN
.
. FirmWare 3.1 S7-400 CPU CiR
Step7 Mini , Step7 lite
(V5.2 V5.1 ) Step7 Step7

: Lite .
. C7 S7-300
. FBD STL LAD
Step7 Proffesional
: Optional
Step7 V5.2
S7-PLCSIM
S7-PDIAG
SFC S7-Graph V5.2
ST S7-SCL
V5.2
:
Step 7
. Proffesional
Step7
Step5 Step7 -
: Step5 Step7
: IEC1131 -
Step7
. Step5 .
: -
STEP 7 PLC STEP 5

.
Step7 Proffesional -
:
-
:
Windows
Windows
Windows
Windows
Windows
Windows
95
98
Me
NT4 workstation (SP6a)
2000 Proffesional (SP2)
XP Proffesional
. RAM CPU
. Step7
Win95
Processor
Win98
Win NT
P133
Win 2000
Win XP
P166
P300
P III
RAM
Win Me
16
24
32
64
64
64
32
32
64
64
128
128
450 MB
Hard Disk
(Autoroziation) -
STEP7
.
Single License
Authorization .
Authorization
Authorization
.
Step7
Start AuthorzW Authorization

: Desktop
Move Authorization Tab

Product
--> . Step7 V5.2 Counter
.
. <-- Authorization
: PLC -
PC Adaptor
. MPI
. USB . RS232 USB
Step7
PCI ISA
) PLC
( CP5611
PCMCIA
CP5511 Notebook
:
PG . PG
. PLC
Step7
PLC
. PLC .
Step7 Set PG/PC Interface
. Control Panel
.
. PLC MPI MPI

. PLC DP Profibus
. Auto
. ( Com2 Com1 ) Properties
38400 19200 .
)
Dip ( 6ES7 972-0CA20-0XA0
.
Windows 2000 , XP , 95,98 , Me
. Plug and Play NT Windows NT
Step7
Step7 -
Step7 Simatic
. HMI Runtime Engineering
Engineering Tools
S7 SCL
ST
CPU314) S7-300 PLC IEC1131-3
. C7 S7-400 (
. Step7 Professional
. C7 s7-400 S7-300 PLC : S7 HiGraph
S7 GRAPH

PLC
IEC1131-3 SFC
C7 S7-400 ( CPU315) S7-300

Step7 Professional
Step7
. PLC : S7 PLCSIM
. Professional
CFC

.
F/H
S7-400 S7-300
Systems
. S7-400 ( CPU314) S7-300 PLC ( Diagnostic ) : S7 PDIAG

. Step7 Professional
. (TS) PLC . PLC : TeleService
Remote
Wiring : DOCPRO
.
Step7
Runtime Software
Standard PID Control

PLC PID
. C7 S7-400 ( CPU31C) S7-300
. : Fuzzy Control
. PID
Modular PID Control
. : Neurosystem
. C7 M7 S7 MPI : PRODAVE MPI
HMI Software
SIMATIC ProTool
. C7
SIMATIC WinCC
Step7
Step7 -
: S7 PLC

. Step7
. PG PC PLC

PLC .
. PLC Offline Step7 .
On-Line
. PLC PG PC PLC
. PLC
Commisioning

. (Cold Test)
.
Step7 .
. PLC Online PG PC
Operation
PC PG . PLC
. . Step7
Troubleshooting
PC PG .
. . Step7
Step 7 -
:
-
Step7
Simatic Manager -
-
Desktop Start Step7
.
Simatic Manager
. .
( ) Simatic Manager
( Optional ) Step7 Professional
:
x
x
x
x
S7 SCL
S7-PDIAG
S7-PLCSIM
S7 Graph
Step7
.
Standard Package
NETPROCommunication
Configuration
SIMATIC Manager
Symbol Editor
Hardware Diagnostics
Programming
Languages
LAD / FBD / STL
Hardware
Configuration
Simatic Manager
Symbol Editor
. PLC
Diagnostics
. PLC
Programming Language
. LAD , FBD , STL

Hardware Configuration
.
Network Configuration
. Node
:
. PDF Documentation
. Step7 Help
Simatic Manager -
. Simatic Manager
Desktop Step7
.
. Wizard
Simatic Manager
. Wizard CPU
. ( ) Wizard
Simatic Manager
. . Simatic Manager Wizard Cancel

( Project ) :
. PLC
. File > Open
. Sample Project File > Open
) File>New>New Project> .
: ( Test
.
.
.
Simatic Manager
Simatic Manager
Insert > Program Insert > Station
.

.
.
.
.
Program Station :
: Insert > Station .
. H 400 300 Station

. H-System Step7 H Station
: Station
. () : Simatic PC Station
. :Other Station
Step7 S5 . (S7) S5 PLC :Simatic S5
. S5
. PLC PG :PG/PC
. Station
400 300 PLC . Station
. Station .
Insert>Station Station
Simatic Manager
Inser>Program>s7
. . Program
:
Insert>Subnet
.
.
Simatic Manager -
Simatic Manager
:
.
File
Properties Rename Cut Paste Copy
Edit
.
. PLC PLC
. Object
Insert
PLC
View
Options
. Simatic Manager
Window
. Simatic Manager
Help
.
.
.
Simatic Manager
File

:
: New
Wizard :New Project Wizard
: Open
: Open Version 1 Project

: Close
:Save As
:Delete
: Reorganize
Object Gap
.

. : Manage

Hide . User Project
. .
Simatic Manager
Display . Display
. Start Search
.
.
. : Archive
Backup
ZIP . File > Archive .
. Option>Customize
Retrieve : Retrieve
. Simatic Manager .
Object List : Print
Object Simatic Manager
Contenet
.
: Page Setup
(... ) : Labeling fields
.
. :Print Setup
Simatic Manager
View

PLC : Offline
PLC :Online
LargeIcons
Small Icons
List
Details
..
Expand all

Collapse all
.
Object : Filter
. S7 CPU .
Simatic Manager
Option
Simatic Manager
Language . Tab Customize
General
Simatic Manager
Online View
: Object Column
: Archiving
Toolbar Simatic Manager

. View > Toolbar
-
:
Hwconfig -
-
S7-300
S7-400
Hwconfig
Hwconfig -
Hardware Simatic Manager Station
Station 300 Station .
.
. Hwconfig Hardware
H-Station 400 300 Station .
PG S5 Station Pc Station Hardware
. Others

Step7 Station
.
: .
Station
Hwconfig
( Rack )
Station 300 Hwconfig

300 Station 400
.
Hwconfig
. Hardware Hwconfig
. Catalog .
. View >catalog
.
. Station
. 400 Station 300
. Not The same System Family
. Station
.
Rack
Rack
Power Supply
PS
Central Processing Unit
CPU
Interface Module
IM
Signal Module
SM
Communication Processor
CP
Function Module
FM

( I/O )

CPU
( Folder )
.
Simatic Step7
(Free download) Service Pack
. Update (www4.ad.siemens.de)
-
.
. I/O
PLC CD .
I/O x
. CPU
I/O
CPU
...
x

I/O
x
I/O
....
FM
CP
.....
x
x
I/O x

IM x
.
....
S7-300 PLC
S7-300 PLC -
simatic Manager Station 300 -

SIMATIC 300 . Hwconfig Hardware
. .
.
: 300
.
. () CPU PS x
. x
. x
CPU (
CPU (
S7-300 PLC
300
Hwconfig .
.

PS
CPU
IM
FM CP SM
4-11

(Drag)
. .
.
( Consistency Check)
. Station
.
. ( ) IM
. CPU
S7-300 PLC
(Expansion)
I/O . Expansion Central

. .
(Field) .
. PLC
.
: S7-300
. o
. IM o
. IM
: IM
( ) IM 361R IM 360S
( ) IM 365 IM 365
/ . IM o
. .
. o
. IM Daisy Chain IM
.
S7-300 PLC
. . CPU

PS
IM
FM CP
SM
4-11
Drag Rail Hwconfig

(0) UR
.
. ( ) IM
. .
. ( CPU 312 ) 300 CPU :
.
S7-300 PLC
S7-300
Hwconfig
. .
... 400 300 Step7
Service Pack
.
.
.
View > Address Overview .
CPU . (Gap) (output) (input)
.

. . Object Properties
S7-300 PLC
DI
Digital Input SM-300

: .
Digital Input
24 VDC
48 VDC
120 VAC
230 VAC
: General
.
End Start . : Address
1 0 DI .
. (1 0 ) Bit
2 Byte= 16 Bit
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
. DI
S7-300 PLC
CPU315 ) 300 CPU . S7-300
System Selection . (
CPU Address Area .
.
.
( Interrupt ) . DI
Properties .
: Inputs
(
) : Diagnostic Interrupt
No Sensor Supply . CPU
. . 15 8 7 0
.
: Hardware Interrupt
. .
. ( )
. :
. Organization Block
. Stop CPU
. : Input Delay
:
. . .
. . .
S7-300 PLC
DO
: Digital Output
Digital Output
24 VDC
0.5 , 1 , 1.5 , 2 A
5 , 8 A
48 VDC
120 VAC
230 VAC
CPU
. F-System :
Address General DO
. Output . DI
: Wire Break

:No Load Voltage
: Short Circuit to M
:Short Circuit to L+
.
DO CPU : Reaction To CPU Stop
Substitute Value . 1 .
. 0 .
. CPU Keep Last Value
S7-300 PLC
DI/DO
.
.
DI/DO
24 VDC
0.5 A
/
+
. DO DI Address General
.
. S7-400 S7-300 DI/DO
S7-300 PLC

. Analoge Input
.
.

.
x
x
x
x
x
x
x
x
x
x
+/-25 mV
+/-50 mV
+/-80 mV
+/-250 mV
+/-500 mV
+/-1 V
+/-2.5 V
+/-5 V
1.. 5 V
+/-10 V

. ()
. ( )
4 Wire
Transducer
AI
2 Wire
Transducer
AI
Power
Supply
Power
Supply
: 4-20mA
-5 mA
-10 mA
-20 mA
0 mA
4 mA
to
to
to
to
to
+5 mA x
+10 mA x
+20 mA x
20 mA x
20 mA x
S7-300 PLC

(Resistor)
48
150
300
600
6000
. (RTD)

.

.( )

.

.

. Pt100 .
.
Pt100
Pt200
Pt500
Pt1000
Ni100
Ni1000
x
x
x
x
x
x
. x
AI
S7-300 PLC
.
. mV

. .
)
. (Compensator) .
(Reference Junction)
. (External Compensating) .
.
. (Internal Compensating)
( ).
Thermocouple
Conductor
Type
Positive
Temperature
Voltage Range
Negative
Range (qC)
(mV)
E
J
Chromel
Constantan
-270q to 1,000q
-9.835 to 76.358
Iron
Constantan
-210q to 1,200q
-8.096 to 69.536
Chromel
Alumel
-270q to 1,372q
-6.548 to 54.874
Copper
Constantan
-270q to 400q
-6.258 to 20.869
Platinum-10%
Platinum
-50q to 1,768q
-0.236 to 18.698
Platinum
-50q to 1,768q
-0.226 to 21.108
Rhodium
R
Platinum-13%
Rhodium
S7-300 PLC
AI
Hwconfig AI
Measuring Range Module .
D , C , B , A
.
. Hwconfig
(6ES7 331-7KF01-0AB0 ) AI 8x12 Bit

Measuring Range Module
.

mV
S7-300 PLC
PLC

CPU AI
1 0 PLC .
. Hex
. Cycle Time
. n
. Cycle Time
.
.
1 0 .
.
Resolution
Number of bits
Bit weighting
Analog Value
15 14 13 12 11 10 9
8
7
6
VZ 214 213 212 211 210 29 28 27 26
22.810
32511
: Resolution
20.0005
27649
20.000
27648
16.000
20736
:
Resolution
0
4.000
1
3.9995
: :
1.1852
4864
< 1.1852
32768
Range
Overflow
7EFF
Overrange
6C01
H
6C00
H
5100
H
:
0
H
FFFF
H
:
ED00
H
8000
H
4
24
3
23
2
22
1
21
0
20
Hex
Measuring
Units
Resolution
Range
20

4 to
mA Decimal Hexadecimal
7FFF
>
22.810 32767
H
5
25
. Decimal
.
Overflow
. Underflow
PLC . 4-20 mA
.
Nominal
Hex .
range
Underrange
Underflow

. PLC .
Hex

.
Resolution Resolution
. Resolution .
S7-300 PLC
S5 S7
S5 S7 S5 PLC
.
. S7
S5 . 1 Overflow S5
.
. Overflow O 0
. Wire Break 1
. Error Bit E 1
. Invalid Valid Activity Bit A 2
Resolution
Bit Number
Bit Value ( S7 )
15
VZ
14
214
13
213
12
212
11
211
10
210
Analog Value
9 8 7
6
29 28 27 26
5
25
4
24
3
23
2
22
1
21
0
20
Bit Value ( S5 )
PS
211
210
29
28
27
26
22
21
20
25
24
23
S7 . ( ) Resolution S5
. ( ) Resolution
S5 S7
Dip S5 . S7
. S5 .
S7-300 PLC
AI
. Analog Input

x
x
x
TC
RTD
x
x
. AI
. Address General
. Word
. 623 608
. AI Input
.
Measuring Range Input . Input
. . D C B A
S7-300 PLC
. Measuring Type
.
.
. Measurement type
. Deactivated
. Deactivate

Measuring range Measuring type
. .
AI
Measuring range .
RTD
. TC
. RTD
S7-300 PLC
AI
: AI
. DI Wire Break : Diagnostics Interrupt
. : Hardware
Interrupt
. Input Low Limit High Limit

.
. Reaction to Open Thermocouple AI 8xTC

7FFF . Overflow
.( ) .
Underflow
.
8000
.( ) .
Resolution . Integration time AI

.
Resolution
9+ Sign bit
12+ Sign bit
12+ Sign bit
14+ Sign bit
Interference
Frequency
(HZ)
400
60
50
10
Integration
Time (ms)
2.5
16.6
20
100
S7-300 PLC
AO
. Analog Output

CPU
AI Address General
. Output
.
. Output Range
. Deactivated I E
CPU .
. . ( )
. Deactivated
Group Diagnostics Diagnostic Interrupt

( ) ( )
.
KLV OCV . CPU
. SV
.
S7-300 PLC
AI/AO
. .
Output Input
.
Special 300
S7-300 SM I/O
. Special 300
Dummy
.
.
I/O

.
I/O
.
. SM 338
S7-300 PLC
CPU
CPU 300 CPU

CPU .
Over Design CPU .
.
CPU 318-2DP
256 KB
512
512
8192 byte
65536 byte Input
65536 byte Output
CPU 315-2DP
128 KB
256
256
2048 byte
128 byte
CPU 314
48 KB
256
256
256 byte
128 byte
CPU 312
16 KB
128
128
128 byte
128 byte
4096 byte Input

4096 byte Output
16384 byte
1024 byte
256 byte
max. 4
Yes
max. 4
Yes
max. 4
No
max. 1
No
RAM
Counter
Timer
Bit Memory
Digital
Channel
Analog
Channel
Rack
Profibus DP
: Hwconfig CPU
. 2DP CPU
. New
. DP CPU
CPU C CPU
. CPU .
I/O
.
S7-300 PLC
: CPU
. CPU .
. CPU
CPU
(Startup) PLC
(STOP) RUN . Run
. RUN .
( ) RUN CPU
. . ( )
. (Operating System )
.

S7-300 PLC
CPU . PII Process Image Input CPU

PLC . .
Organization Block 1 OB1
. Process Image Output PIQ CPU
CPU PIQ PII
.
1998 . 1998 CPU
. .
RUN
RUN CPU
RUN
.
:
PII Update
PIQ
S7-300 PLC
PLC
: PLC
Write Read CPU . I/O :Stop
. .
Read Only CPU . I/O CPU . :Run
. Download
CPU . I/O CPU . :Run-P
. Write Read
. ( ) CPU :
. Run-P CPU
CPU : MRES
. CPU .
. STOP MRES CPU
. Stop LED Stop :
. Stop MRES STOP -
. LED . MRES Stop ( ) .
LED . CPU
.
Step7 PLC > Clear / Reset : Step7

. Hwconfig
S7-300 PLC
S7-300 CPU
. (400 300 ) S7 CPU
S7 CPU
. (Download) CPU : Load Memory

. :Work Memory
. .... PII , PIQ :System Memory
Load . System Memory Work Memory CPU
. Memory
Load Memory 318-2DP CPU . CPU
MMC Load Memory 300 CPU . EPROM RAM
. Load Memory CPU (Micro Memory Card)

. CPU
S7-300 PLC

Memory Load Memory CPU
Master Memory MMC . Flash EPROM RAM Card
MMC . Load Memory FEPROM Card

. 8 MB CPU 315-2DP .
CPU : Non-Volatile Memory
. NV Memory
. Retentive NVRAM .
. CPU .
NVRAM
.
S7-300 PLC

: S7 CPU
Cold Restart
Warm Restart
( S7-400 ) Hot restart
.
.
.
Cold Restart
. (Retentive)
. OB1 x
Warm Restart
. Retentive x
. OB1 x
Hot Restart
. Retentive x
. x
. S7-400 x
. Backup CPU x
. RUN Stop CPU
.
HOLD
. PC PG

Debug . (breakpoint) Debug .
.
CPU
RUN CPU .
. STOP CPU STOP PG

.

STOP
HOLD
STARTUP
RUN
S7-300 PLC
S7-300 PLC
CPU
. CPU
. STOP CPU
: STARTUP STOP CPU
. RUN-P RUN
(PLC Step7 ) STOP
. STOP OB STOP
HOLD
Breakpoint
:
.
STARTUP CPU
.
.
5
STOP
STARTUP CPU
STARTUP
HOLD CPU
EXIT HOLD Breakpoint
STOP
(PLC Step7 ) STOP
. STOP
RUN
STARTUP CPU
STOP
RUN
CPU
. OB RUN
(PLC Step7 ) STOP
. STOP
:
.
10
HOLD CPU
.
8
Breakpoint
:
.
HOLD
RUN CPU

RUN
HOLD CPU
EXIT HOLD Breakpoint
S7-300 PLC
. CPU
S7-300 CPU
CPU
. CPU
:
. CPU : General
. CPU MPI . Interface

Simatic Multi Point Interface MPI
PC PG CPU MPI .
.
. MPI
: Cycle/ Clock Memory
Scan Cycle Monitoring Time
.
Stop PLC 150ms
.
.
Minimum Scan Cycle Time
318 300 CPU S7-400 CPU

. .
.
S7-300 PLC
: Retentive Memory
. NVRAM
.
. S7 S5 Retentive Step5
: Retentive 115U CPU
Retentive
. Retentive
( ) . Retentive
. Retentive S7
:Startup
RUN CPU
.
:
. Cold , Warm , Hot S7-400
. Cold , Warm CPU 318 S7-300
. Warm CPU S7-300
x
:
PLC > Operating Mode . Step7 PLC
. LAD/STL/FBD Hwconfig
S7-300 PLC
Retentive Memory Warm

.

.
. ( Field )
. OB102, OB101, OB100 ,
Protection
S7-400 CPU
: CPU
(Write Read )
x
.
Upload (Read)
x
. Download
. Read , Write
x
. (Know-How)
Simatic Manager Password . CPU
. Online
Simatic Manager PLC>Access Right>Setup
PLC>Access Right>Cancel . Simatic Manager
.

MRES PLC
.
S7-300 PLC

. CPU
:
. (OB)
. OB CPU
. ( OB1) CPU
. : Interrupts
. Time-of-Day Interrupts x
. Cyclic Interrupts x
OB CPU . CPU315-2DP Interrupt
.
S7-300 PLC
CPU
CPU . CPU CPU
. 318
. PLC CPU
LED
SF
BATF
DC5V
. CPU 5VDC
FRCE
( ) Force
RUN
STOP
SF DP
DP
BUSF
DP
S7-300 PLC
FM
CPU Function Modules

FM . CPU
CPU . CPU
Step7 FM . FM
FM FM .
FM Simatic Manager Hwconfig FM .
. FM .
300 FM
. Address Generel
FM
. SM Address
. CPU FM Parameters Basic

Hardware Interrupt . Diagnostic
CPU . Actual
. FM .
S7-300 PLC
: S7-300
(Counter Module )
FM350-1
(Incremental) .
FM350-1 . 500KHZ
.
.
(Counter Module )
FM350-2
(Incremental) .
. 10 KHZ
. 20KHZ
(Position Module )
FM351

.
.
.
.
(Position Module )
FM353
.
(Position Module )
FM354
.
(Electronic Cam Controller ) FM352 x
. Cam Control
.

.

.
(Closed Loop Controller )
FM355

Continues Control .

Step Control
.
S7-300 PLC
FM350-1
CPU
. .
CPU CPU
.
Step7 FM350-1
. Download FM .
FM350-1 HWconfig Step7
.
S7-300 PLC
. Encoders
.
Operating Mode
Continuous
.
Single Counting .
Peridic Counting .
. Load Value Continuous
S7-300 PLC
(Gate Control)
.
.
) Inputs (Hardware
Gate Control)
: . (
Level Control -
: DI Start
Edge Control -
: DI Stop DI Start
(Software Gate Control )
.
FM
Step7
FC0 . Library
. CNT_CTRL
S7-300 PLC
: FM350-1
Hardware Interrupt Enables

. Underflow Overflow .
HWConfig
. Basic Parameters Properies FM
Outputs
FM Output
.
FM
. FM350-1 FM
FM .
.
AI Submodule FM
. D A FM350-1 .
A
D
5 V Differential Signals
24V Signals
S7-300 PLC
CP
( Communication Processor )
. CP
.
PS
. 10A 5A 2A
120/230 300
. Hwconfig

. 300
) . File > Consistency Check .
. ( CPU
File > Save . No Error
File> Save and Compile .

Simatic Manager System Data .
.
PLC
S7-400 PLC
S7-400 -
S7-400 S7-300
. .
Simatic Manager Station400
Hwconfig Station
400
: S7-400 S7-300
. 300 400
.300
. 400
. S7-400 AI/AO DI/DO
. 300 400
. 400 CPU
. CPU 400 CPU Multicomputing
. 400 CPU Hot Startup Warm Cold
.300 400 CPU
:
PS
. S7-400
Redundant
Standard
10 A
4A
10 A
20 A
24 V
120/230 V
Redundant
. .

.
S7-400 PLC
S7-400
: S7-400

Backplane Bus
I/O BUS
. Communication Bus
. 400
. S7-400 .
.
Universal
UR1
Redundant
"
"
"
UR2
"
18
Expansion
ER1
"
"
"
ER2
10 + 8
Segmented
CR2
Universal
CR2-H

.
.
18
UR2
PLC
2*9
Redundant
S7-400 PLC
S7-400
: S7-400
. S7-400
. IM
. IM
. IM
. IM (Chain) IM x
460-3
461-3
4
460-1
461-1
1
460-0
461-0
4
102.25
m
No
1.5 m
5m
Yes
No
Send IM
Recieve IM
Max. ER
/chain
Max.Distance
Power
Transfer
Number of IM
in Rack0
IM 9
. (Send/Receive) .
.
IM 9
.
IM 9

. IM467
S7-400 PLC

IM s7-300 . S7-300
IM S7-400
IM .
.
IM . Connect
. C2 C1
S7-400 PLC
400
: 400
. CPU x
. Receive IM
. Redundant
CPU ( ) multicomputing CPU
.
. CPU x
Redundant
Multicomputing CPU
. S7-300 S7-400
. CPU PS
S7- 400 CPU
. S7-300 S7-400 CPU

:
Load Memory . 400 CPU
FEPROM RAM
. CPU .
. 300 400 CPU
S7-400 PLC
. Startup Hot Warm ,Cold
. Cycle/Clock Memory
.400 CPU Protection x

. 300 OB x
. 300 CPU Multicomputing 400 CPU
S7-400 PLC
Multicomputing CPU
CPU S7-400 CPU CPU
(Tasks) ( )
CPU STOP CPU .
.
: Multicomputing
CPU 9
. CPU
CPU 9
.
: Multicomputing
. Hwconfig . Multicomputing CPU
. CPU414-2DP CPU412-2DP
CPU .
CR . UR .
. CPU
S7-400 PLC
Multicomputing CPU .
Analog Input . CPU .

. CPU Address Properties
View>Filter Hwconfig
. CPU . CPU
Station 400 Simatic Manager Hwconfig
CPU . CPU
. CPU
: . CR CPU Multicomputing :
UR Multicomp. C bus i/o CR
.
Multicomp CR CPU

Multicomp SM CPU CR
. CPU Hwconfig
CPU H H-system Multicomputing :
. CPU .
-
:
PLC
-
S7
S7
CPU S7
-
-
Simatic Manager
LAD/STL/FBD
-
-
Reference Data
Rewiring
Compare Blocks
PLC
PLC -
. Decimal

PLC .
. .
(Binary) (Decimal)
. .
Decimal
4
9
24
Binary
100
1001
11000
. Bit (
)
. Double Word Word . Word Byte
Decimal
.
PLC
BCD Hexadecimal PLC
. Hexadecimal
. Hex .
.

16 digits
0 , 1, 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , A , B , C , D , E, F
:
A=10
B=11
C=12
D=13
E=14
F=15
: .
Decimal
Binary
Hexadecimal
BCD
43
1011
0010
0100
0011
PLC . Binary Coded Decimal BCD

. .. Decimal BCD .
BCD
.
: BCD .

BCD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
PLC
.
Decimal
Binary
BCD
Hexadecimal
0000
0001
0010
11
0011
100
0100
101
0101
110
0110
111
0111
1000
1000
1001
1001
10
1010
0001 0000
11
1011
0001 0001
12
1100
0001 0010
13
1101
0001 0011
14
1110
0001 0100
15
1111
0001 0101
16
1 0000
0001 0110
10
17
1 0001
0001 0111
11
18
1 0010
0001 1000
12
19
1 0011
0001 1001
13
20
1 0100
0010 0000
14
126
111 1110
0001 0010 0110
7E
127
111 1111
0001 0010 0111
7F
128
1000 0000
0001 0010 1000
80
510
1 1111 1110
0101 0001 000
1FE
511
1 1111 1111
0101 0001 0001
1FF
512
10 0000 0000
0101 0001 0010
200
S7
S7 -

DI . Dword Word Byte Bit PLC
Bit
. Dword Word Byte
. Word AI
0.0
4.7

. 0.8
. . I S7
I 0.1
IB 1
IW 2
ID 8
I
Bit
IB
Byte
IW
Word
ID
Dword
. IW IW
. IW1 IW0 ..... IW4,IW2,IW0

IW 0
BYTE0
BYTE1
IW 1
=
BYTE1
+
BYTE2
ID4 ID0
. . Double Word
PI (peripheral) :
PIB 1
PIW 2
PID 8
PIB
PIW
PID
Byte
Word
Dword
. Bit
S7

. Q I .
Q 0.1
QB 1
QW 2
QD 8
Q
QB
QW
QD
Bit
Byte
Word
Dword
.. (peripheral)
PQB 1
PQW 2
PQD 8
PQB
PQW
PQD
Byte
Word
Dword
.. PLC

. Bit Memory CPU
. Flag F S5 .
M 0.1
MIB 1
MW 2
MD 8
M
MB
MW
MD
Bit
Byte
Word
Dword

C T
C2 T1
. cpu :
S7
S7 -
S5 . Parameter Complex Elementary S7
.
Elementary
S5
A I 0.0
=Q 0.1
A F1.1
KB
KH
DH
A I 0.0
=Q 0.1
A M1.1
L B#16#01
L IB0
T QB1
T MB3
L W#16#6AC0
L IW0
T QW2
L MW4
L ID4
T QD8
(bit)
1
Bool
B#16#
Byte
FF 00
16
W#16#
Word
FFFF 0000
32
DW#16#
DWord
0000_0000
FFFF_FFFF
KF
L +35
L -415
16
L -3200947891
32

+ -
L#
-2147483648
Integer
(INT)
Double
Integer
(DINT)
2147483647
KG
L 1.23e+1
32
(Floating Point)
Real
KT
L S5T#1M40S
L S5Time#20MS
16
S5T#

S5Time

2H46M30S0MS

L T#10M20S
L Time#1MS
32
T#
Time
24D20H31M23S647MS
16
L D#2004-3-15
L Date#20043-15
Time
L TOD#1:10:3.3
32
ASCII
Character
L a
T IB0
D#
yyy-mm-dd
TOD#h:m:s.ms
0:0:0.0
23:59:59.999

Date
Time_Of_Day
CHAR
S7
Complex
64
Bit
DT#yy-mm-dd-h:m:s.ms
DATE_AND_TIME
S5
DT#1993-12-258:01:1.23

BCD
.
STRING[4]
n+2
Byte
STRING[n]
STRING
. n
Test
String
String[4]
Test[1..3]
:
Test[1], Test[2],
Test[3]
ARRAY
ARRAY[x1..x2]
x2 x1
+ -
.
Test[1..3,1..2]
:
Test[1,1]
Test[1,2]
Test[2,1]
Test[2,2]
Test[3,1]
Test[3,2]

:
Test[1,1,2,1,5,4]

ARRAY[x1..x2 y1..y2]
y2 y1 x2 x1
+ -

.
.
.
:
Bool

. INT
.
Test
Struct
a
bool
b
int
c
word
End Struct
Struct

End Struct
STRUCT
CPU S7
Parameter Types
S5
T1
Timer
C1
Counter
P#M50.0
P#
Pointer
2
bytes
2
bytes
6
bytes
10
bytes
Any
CPU S7 -
S7 CPU . ACCU2 ACCU1 . S5 S7 CPU

. ACCU4 ACCU3
ACCU1
ACCU2 ACCU1 ( )
. . ACCU1
:
31
24
23
16
15
..
ACCU1
ACCU1-H
ACCU1-H-H
High Word - High Byte
ACCU1-H-L
High Word - Low Byte
ACCU1-L
ACCU1-L-H
ACCU1-L-L
Low Word - High Byte
Low Word - Low Byte
:
( ) . ACCU1-L-L
( ) . ACCU1-L Word
( ) . ACCU1 Dword
CPU Stack
: Stack S7 CPU
Status Word x
.
. TAR LAR Address Registers x
Nesting Nesting Stack x
. RLO RLO .
Master Control Relay MCR Stack x
.
CPU S7
CPU S7
Status Word

. .
( X ) 1 0
. Show FC . BR S5
CC1 , CC0
:
CC1
CC0
OV
. 1 (Overflow)
. Update
OS
OV . OverFlow Stored
.
OR
. OR AND (bit Logic) 1

STA
.0 1
RLO
1 0 (Result of Logic Operation )

. 0 AND
FC
Network RLO First Check

. Update RLO .
BR
First Check RLO SAVE

BR .
-
. Step7
(logic Blocks) -
: Code Blocks
x OB
Organization Block
x FB
Function Block
x FC
Function
x SFB
System Function Block
x SFC
System Function
-
.
:
x DB
Data Block
x SDB
System Data Block

User Defined Type UDT -
: CPU CPU
CPU 416-2
CPU 412-1
CPU 314
CPU 312
44
23
13
OB
2048
256
128
32
FB
2048
256
128
32
FC
4095
511
127
63
DB
Step5 Step7
:
. Step7 Step5 OB
. Step7 Step5 DB
. Step7 FC Step5 FB
. Step7 FC Step5 Program Block PB
. Step7 FC Step5 Sequence Block SB
. IEC1131
:
. Step5 FB Step7 FB
Organization Blocks
. (user Program) (Operating System) PLC OB

OB1 OB . L
. Step7 Step5 .
. OB1 OB
: . OB

OB
Main program scan
Time-of-day interrupts
OB10 to OB17
Time-delay interrupts OB20
OB20 to OB23
Cyclic interrupts
OB30 to OB38
Hardware interrupts
OB40 to OB47
3 to 6
7 to 15
16 to 23
25
Multicomputing interrupt
25
28
26
Redundancy errors
29
Background cycle
27
Startup
Asynchronous errors
OB1
OB60
OB70, OB72
OB80, OB82 to OB87
OB90
OB100 to OB102
Synchronous errors
OB121, OB122
. (priority) OB
OB1 . OB OB .
. OB CPU . OB
S7- S7-300 OB
Time of Day Interrupt CPU . 400

. Interrupt Cyclic Interrupt
. CPU 416-2DP
:
OB47 OB10 x
OB72 OB70 x
OB87 OB81 x
. OB
. Deselect OB
. OB OB1
S7 S5 OB
. S5 OB1 S7 OB1 (
Cold . S5 OB S7 OB (
. . OB21 Step7 OB100

: SFC S7 S5 OB (
S7
S5
SFC41 SFC40
OB120
: S7 S5 OB (
S7
S5
LOOP
OB160
PUSH
OB111

S7 S5 OB
S5
S7
Free cycle
OB1
OB1
Time-delay (delayed)
interrupt
OB6
OB20 to OB23
Time-of-day
(clock-controlled) interrupt
OB9
OB10 to OB17
Hardware interrupts
OB2 to OB5
OB40 to OB47
Process interrupts
OB2 to OB9
Cyclic (timed)
interrupts
OB10 to OB18
Replaced by
hardware
interrupts
OB30 to OB38
Multicomputing interrupt
OB60
Manual complete (cold) restart

OB100
OB21 (S5-115U)
OB20 (S5-135U)
OB100
Manual (warm) restart
OB21 (S5-135U)
OB101
Automatic (warm) restart
OB22
OB101
Errors
Error
OB19 to OB35
Other
Processing in STOP
mode
OB39
OB121, OB122,
OB80 to OB87
Omitted
Background processing
OB90
Function
Main
program
Interrupts
Startup
(Function)
FC
FC . FC
FC .
. FC FC
OB1
FC1
-----------CALL FC1
-----------------------
-------------------------------------------------
FC
.
FC
. FC
(Function Block)
FB
FC FC FB
FB . .
:
CALL FB1 , DB1
. FB FB
(Data Block)
DB
. Step7 OB ,FC,FB
DB PLC Write Protect
. Properties
:
Shared DB -
.
. CPU DB .
Instance DB -
DB FB FB
. FB
.
System Blocks
:
System Function
SFC x
System Function Block SFB
FC SFC FB SFB
. . .
stop cpu
SFC 46
SFB 41

:
. Linear Programming OB1 -
Structured Programming -
.
Linear Programming
Structured Programming
Main Program = OB1
Main Program
OB1
FB1
FC1
. FC FB FC FB FB FC OB
FC1 FB1 . Step7
. OB1
CPU 315 . CPU Nesting Depth
. CPU 414-3
. Nesting Depth
PLC structured Programming :

. SF PLC
Simatic Manager
Simatic Manager -
. Simatic Manager DB FC FB OB
. SFC SFB
.
. CPU S7 Program Station
Sources Blocks
. Source Source
Blocks OB1 . Blocks
Hwconfig .
Blocks System data Save and Compile
System Data Blocks SDB
:
. PLC PLC
S7 Program .
. Blocks
Simatic Manager
:
: Block Insert > S7 Blocks Blocks -
Insert New Object Blocks -

.

:
. . x
. STL OB , FB , FC x
( ) Instance . Shared x
. Blocks FB . FB
Open New Object General Option > Customize Simatic Manager x
.
LAD/STL/FBD
LAD/STL/FBD -
Simatic Manager Blocks FC FB OB

: . LAD/STL/FBD
Menu / Toolbar
Declaration Section
Program
Element
Code Section
:Program Element
.
View FBD STL LAD . LAD
.
. Insert > Program Element Program Element
LAD/STL/FBD
:Declaration Section
Temp OB .
. Temp FC FB
.
Declaration
in
FC
X
FB
X
OB
-
Out
In/out
temp
static
:
. Temp x
.
. Temp x
Temp OB x
.
. OB x
. out in x
) in/out x
(
. DB Temp FB . FB Static x
Static DB
.
: . # x
L #test
. test . FB Declaration
LAD/STL/FBD
:Code Section
OB1 .
STL View . LAD
Code Section FBD STL . LAD FBD
. T
:
Block Title
.
Block Comment
.. Comment
Network Comment
Network
. Network . Segment

Insert > Network Network .
. 64 Title Network . Toolbars

. Network Comment
. STL . Statement Network
LAD/STL/FBD
. Network
. Network 2 Network 1
. OB1 Network
STL . Statement
Toolbar FBD LAD
. Network Drag Program Element
. LAD
. FBD
.
.
. FBD
-
FC
OB1
.
:
Simatic Manager
. Declaration . LAD/STL/FBD
b a Declaration C a, b
FC Network . Int C
Program Element OB1 FC

CALL FC Blocks
. .
.
. .
FB
: FC FB
Simatic Manager FB -
LAD/STL/FBD FB -
Declaration -
Network -
FB -
Simatic Manager -
FB Instance -
FB Blocks Program Element FB
: DB CALL OB1
CALL FB1,DB2
. Declaration
. CALL DB
Temp PLC
DB .
FB DB Simatic Manager
. ( Temp )
SFB SFC
. ( )
: Program Element
System Function Blocks +

.
. Network Drag
. Call DB SFB . Call
: Call
Simatic Manager Blocks

.
Simatic Manager
.
.
.
LAD/STL/FBD . Protect
. The Block Is Protected
. . Protect
Protect . Source EXE
.
STP SFC 46
. CPU .
DB
Shared DB . FB FB Instance
.
.
:
Simatic Manager -
LAD/STL/FBD -
-
: SF PLC
. Simatic Manager (
. PLC Simatic Manager (
. (
LAD/STL/FBD
.
Insert > Declaration Line
.
2 2 1 0 Word 0
cell 6 Real
. Type
DB PLC Read Only

Part2 DB is write Protected Peroperties Simatic Manager
. SF DB PLC
UDT
Simatic Blocks User-defined Data Type
UDT
UDT . Manager
.
( Run, Stop,Error, Min,Max )
.
. UDT . UDT
UDT . UDT
.

LAD\STL\FBD View> Data View
.
UDT UDT
. File> Check and Update Access
. Varriable Table VAT

.
-
.... STEP 7
. T5 C1 I 1.1 , Q 4.0 .
Q4.0

. Motor_ON
.

. Declaration
.
Simatic Manager Symbol Editor
. S7 Program
. Symbol Editor
.
.
Reference Data
. LAD
. Enter
View > Display With LAD/STL/FBD
. Symbolic Representation
:
. . x
Import ( Step 5 ) S7
. Symbol Editor Symbol > Import .

. PLC PLC x
v (Upload) PLC
Reference Data -
Reference Data
Option > Reference Blocks Simatic Manager .
: Ref . Data>Display
(I , Q , M ,T ,C ) -
Go to location .
.
Reference Data
-
(byte, word) X O
. -
. Call -
:
Example
CALL FB10
Meaning
UC FB10
Block called unconditionally
CC FB10
Block called conditionally
Data block
Block not called
Symbole
Block called normally
. -
. -
Rewiring
Rewiring -

Simatic Manager Rewiring . .
. Option
OK Rewiring
. Rewiring
.
Compare Blocks -
PLC
. PG PC
:
Off Line On Line
Offline
: Option > Compare Blocks
Simatic Manager
Path2 Blocks
. Blocks Simatic Manager
OK .
. Detail
LAD/STL/FBD Go To
.
S7 Z] cYf{ -5
: ] f
Bit Logic Instructions
Comparison Instructions
Conversion Instructions
Counter Instructions
Data Block Instructions
-
-
-
-
-
Logic Control Instructions
Integer Math Instructions
Floating-Point Math Instructions

Load and Transfer Instructions
-
-
Program Control Instructions
Shift and Rotate Instructions
Timer Instructions
Word Logic Instructions
Accumulator Instructions
-
Word -
-
S7
: .
. STL FBD LAD STL .
. FBD LAD
FBD LAD .
.
. .
Status Word .
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
. CPU Writes
:
1 0
( )
Bit Logic
Bit Logic -
: .
x A
And
x AN
And Not
x O
Or
x ON
Or Not
x X
Exclusive Or
x XN
Exclusive Or Not
x O
And before Or
x A(
And with Nesting Open
x AN(
And Not with Nesting Open
x O(
Or with Nesting Open
x ON(
Or Not with Nesting Open
x X(
Exclusive Or with Nesting Open
x XN(
Exclusive Or Not with Nesting Open
x )
Nesting Closed
x =
Assign
x R
Reset
x S
Set
x NOT Negate RLO

x SET
Set RLO (=1)
x CLR
Clear RLO (=0)
x SAVE Save RLO in BR Register

x FN
Edge Negative
x FP
Edge Positive
:
Address
<Bit>
Data Type
Bool
Memory Area
I,Q,M,L,D
Bit Logic
And
: STL
A <Bit>
. AND RLO 1 A :
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
A
A
=
AN
I 0.0
I 0.1
Q 4.0
4.0 And I0.1 I0.0 :
. 1 . 1 .
LAD
FBD
And Not
: STL
AN <Bit>
. AND RLO 0 AN
And :Status Word
A
AN
=
I 0.0
I 0.1
Q 4.0
Q4.0 And Not I0.1 I0.0 :
. 0 1 . 1 .
LAD
Normal Open
Normal Closed
FBD
Bit Logic
Or
: STL
O <Bit>
. Or RLO 1 O :
:Status Word
Writes:
BR
-
CC1
-
CC0
-
OV
-
OS
-
OR
0
STA
x
RLO
x
/FC
1
:
O
O
=
ON
I 0.0
I 0.1
Q 4.0
Q4.0 OR I0.1 I0.0

. 1 1 .
LAD
FBD
Or Not
: STL
ON <Bit>
. Or RLO 0 ON
or :Status Word
O
ON
=
I 0.0
I 0.1
Q 4.0
Q4.0 OR Not I0.1 I0.0

. 1 0 1 .
FBD
LAD
Bit Logic
Exclusive Or
: STL
X <Bit>
. XOR RLO 1 x :
1 1 ( RLO )
or :Status Word
:
X
I 0.0
I 0.0
I 0.1
Q 4.0
0
0
1
1
I 0.1 Q 4.0
0
1
0
1
0
1
1
0

1
. 1

.
LAD
FBD
XN
Exclusive Or Not
: STL
XN <Bit>
. XOR RLO 0 XN
. 1 0 1 ( RLO )
or :Status Word
X
I 0.0
XN
I 0.1
Q 4.0
I 0.0
0
0
1
1
I 0.1 Q 4.0
0
1
0
1
FBD
1
0
0
1

1 1
. 0
LAD
Bit Logic
A(
: STL
:
A( <Bit>
:
. Nesting Stack ( Status Word ) OR RLO A(
. Nesting Stack
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A(
O
O
)
A(
O
O
)
=
I 0.1
M1.0
I0.0
. Nesting Stack RLO . OR M1.0
Nesting Stack AND
I 0.2
M1.1
. Q4.0 RLO RLO
Q 4.0
() LAD

() FBD

Bit Logic
AN(
: STL
:
A( <Bit>
:
. And Not A(
O(
: STL
:
O( <Bit>
:
. Or A(
ON(
: STL
:
ON( <Bit>
:
. Or Not O(
X(
: STL
:
X( <Bit>
:
. XOR O(
XN(
: STL
:
X( <Bit>
:
. XOR Not X(
Bit Logic
Nesting Close
: STL
:
)
:
( Status Word ) OR RLO Nesting Stack )
And Nesting Stack RLO
Stack . Stack Or
. . (
A(
AN(
O(
ON(
X(
XN(
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A(
O
O
)
A(
O
O
)
=
I 0.1
M1.0
I0.0
. Nesting Stack RLO . OR M1.0
Nesting Stack AND
I 0.2
M1.1
. Q4.0 RLO RLO
Q 4.0
LAD
A(
FBD
A(
Bit Logic
Assign
: STL
= <Bit>
Master Control Relay RLO = :
0 = MCR=0
. RLO
:Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
0
And I0.1 I0.0 :
. Q4.0
. 1 . 1
A
A
=
() FBD
I 0.0
I 0.1
Q 4.0
() LAD
Set
: STL
S <Bit>
Master
. 1 RLO=1 S
S MCR=0
Control Relay
RLO = 1 S = S .
. S . 1 0
Assign :Status Word
Q4.0 I0.0
I0.0 . I0.0 1 0
.. Q4.0
A
S
FBD
I 0.0
Q 4.0
LAD
Bit Logic
Reset
: STL
R <Bit>
. 0 RLO=1 R
R MCR=0 Master Control Relay
.
Assign :Status Word
Q4.0 I0.0 :
I0.0 1 0
Q4.0 I0.0 .
..
A
R
I 0.0
Q 4.0
FBD
NOT
LAD
Negate RLO
: STL
NOT
:
0 1 1 0 RLO NOT
:Status Word
BR
CC1
CC0
OV
OS
Writes:
A
NOT
=
OR
STA
RLO
/FC
I 0.0
Q4.0 I0.0
Q 4.0
I0.0 . NOT
.
FBD
LAD
Bit Logic
132
SET
Set RLO (=1)
: STL
SET
:
. 1 RLO SET
NOT :Status Word
SET
=
=
. RLO SET
M10.0
M15.1
FBD
LAD
CLR
Clear RLO (=0)
: STL
CLR
:
. 0 RLO CLR
:Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
CLR
=
=
M10.1
M10.2
. RLO CLR
.
FBD
LAD
Bit Logic
133
SAVE
Save RLO in BR Register
: STL
:
SAVE
:
First Check . (Status Word ) BR RLO SAVE
. AND Network BR . /FC
. SAVE
BR RLO BR RLO SAVE
. .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I 0.0
I0.1
SAVE
LAD
FBD
Bit Logic
FN
Edge Negative
: STL
:
FN <Bit>
Address
<Bit>
Data Type
Bool
Memory Area
I,Q,M,L,D
:
0 1 RLO RLO FN
. RLO=1
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I 1.0
FN
M1.0
FN 0 1 I1.0
Q 4.0
. Q4.0
. M1.0
LAD
FBD
Bit Logic
135
FP
Edge Positive
: STL
:
FN <Bit>
Address
<Bit>
Data Type
Bool
Memory Area
I,Q,M,L,D
:
1 0 RLO RLO FP
. RLO=1
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I 1.0
FN
M1.0
FP 1 0 I1.0
Q 4.0
. Q4.0
. M1.0
.
LAD
FBD
Bit Logic
STL FBD LAD

. STL
Midline Output
FBD
Address
<Bit>
Data Type
Bool
Memory Area
I,Q,M,L,D
:
. RLO
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
M2.2 M1.1 I1.1 I1.0 And M0.0
. M3.3
() LAD
Bit Logic
137
RS
Reset_Set Flip Flop
FBD
Parameter
<address>
Data Type
BOOL
Memory Area
I, Q, M, D, L
Description
S
R
Q
BOOL
BOOL
BOOL
I, Q, M, D, L, T, C
I, Q, M, D, L, T, C
I, Q, M, D, L
:
. RLO=0 RLO =1 RS
. S=0 R=1
1 . S=1 R=0
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. Q4.0 M0.0 I0.1 I0.0
.
.
() STL
A
R
A
S
=
I0.0
M0.0
I0.1
M0.0
Q4.0
() LAD
Bit Logic
SR
Set_Reset Flip Flop
FBD
Parameter
<address>
Data Type
BOOL
Memory Area
I, Q, M, D, L
Description
S
R
Q
BOOL
BOOL
BOOL
I, Q, M, D, L, T, C
I, Q, M, D, L, T, C
I, Q, M, D, L
:
. RLO=0 RLO =1 RS
. S=1 R=0
1 . S=0 R=1
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. Q4.0 M0.0 I0.1 I0.0
.
.
() STL
A
S
A
R
A
=
I
M
I
M
M
Q
0.0
0.0
0.1
0.0
0.0
4.0
() LAD
(Comparison Instruction)
(Comparison Instruction) -
.
:
==
<>
>
<
>=
<=
ACCU1 is equal to ACCU2

ACCU1 is not equal to ACCU2
ACCU1 is greater than ACCU2
ACCU1 is less than ACCU2
ACCU1 is greater than or equal to ACCU2
ACCU1 is less than or equal to ACCU2
:
x ? I
Compare Integer (16-bit)
x ? D
Compare Double Integer (32-bit)
x ? R
Compare Floating-point Number (32-bit)

. ?
. FBD FBD LAD :
?I
Compare Integer (16-bit)
: STL
:
==I , <>I , >I , <I , >=I , <=I

:
. ACCU1-L ACCU2-L
Status Word CC0 CC1 . RLO=0 RLO=1
:
CC1
CC0
0
0
1
0
1
0
ACCU2-L = ACCU1-L
ACCU2-L < ACCU1-L
ACCU2-L > ACCU1-L
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MW0
ACCU1-L MW0
MW2
MW2 ACCU2-L
ACCU2-L . ACCU1-L
>I
=
Q4.0
ACCU1-L
. Q4.0 RLO=1
FBD
141
?D
Compare Double Integer (32-bit)
: STL
:
==D , <>D , >D , <D , >=D , <=D

:
ACCU1 ACCU2
Status CC0 CC1 . RLO=0 RLO=1 .
: Word
CC1
CC0
0
0
1
0
1
0
ACCU2 = ACCU1
ACCU2 < ACCU1
ACCU2 > ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD0
ACCU1 MW0
MD4
ACCU1 MW2 ACCU2
ACCU2 .
<>D
=
Q4.0
ACCU1
. Q4.0 RLO=1
FBD
?R
Compare Floating-Point (32-bit)
: STL
:
==R , <>R , >R , <R , >=R , <=R

:
. ACCU1 ACCU2
Status Word CC0 CC1 . RLO=0 RLO=1
:
CC1
CC0
0
0
1
0
1
0
ACCU2 = ACCU1
ACCU2 < ACCU1
ACCU2 > ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD0
ACCU1 MD0
1.359E+02
ACCU1 135.9 ACCU2
ACCU2 .
<R
=
Q4.0
RLO=1 ACCU1
. Q4.0
FBD
(Conversion Instruction)
(Conversion Instruction) -
:
: Integer BCD :
x
BTI BCD to Integer (16-bit)
ITB Integer (16-bit) to BCD
BTD BCD to Integer (32-bit)
ITD Integer (16-bit) to Double Integer (32-bit)
DTB Double Integer (32-bit) to BCD
DTR Double Integer (32-bit) to Floating-point (32-bit IEEE-FP)

: :
INVI Ones Complement Integer (16-bit)
INVD Ones Complement Double Integer (32-bit)
NEGI Twos Complement Integer (16-bit)
NEGD Twos Complement Double Integer (32-bit)
NEGR Negate Floating-point Number (32-bit, IEEE-FP)

: :
CAW Change Byte Sequence in ACCU 1-L (16-bit)
CAD Change Byte Sequence in ACCU 1 (32-bit)

: :
RND Round
TRUNC Truncate
RND+ Round to Upper Double Integer
RND- Round to Lower Double Integer
. FBD FBD LAD :

. LAD
BTI
BCD to Integer (16-bit)
: STL
:
BTI
:
. (Integer) ACCU1-L BCD BTI
. ACCU2 ACCU1-H ACCU1-L
11 0 +999 -999 ACCU1-L BCD
BCD . 14 12 .(0=Positive , 1= Negative) 15
STOP CPU BCDF 15 10

OB121 . CPU Id:2521
. CPU Stop
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MW10
Integer ACCU1-L
BTI
T
MW10 BCD
MW12
. MW12 ACCU1-L
Integer BCD
+915
. ACCU1-L
. I0.0=1
(overflow) Q4.0=1
. Q4.0
FBD
ITB
Integer (16-bit) to BCD
: STL
:
ITB
:
. BCD ACCU1-L ITB
. ACCU2 ACCU1-H ACCU1-L
: 15 12 BCD 11 0 ACCU1-L
0000= Positive
,
1111=Negative
Status Word OS OV +999 -999 BCD
. RLO .
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MW10
BCD ACCU1-L
ITB
T
MW10
MW12
. MW12 ACCU1-L
BCD Integer -413
. ACCU1-L
Q4.0=1
FBD
BTD
BCD to Integer (32-bit)
: STL
:
BTD
:
. (Integer) ACCU1 BCD BTD
. ACCU2 ACCU1
27 0 +9,999,999 -9,999,999 ACCU1 BCD
. 30 28 .(0=Positive , 1= Negative) 31
CPU BCDF 15 10 BCD
OB121 . CPU Id:2521 STOP
. CPU Stop
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD10
Integer ACCU1
BTI
T
MD10 BCD
MD20
. MD20 ACCU1
Integer BCD
+157821
. ACCU1
BTI Q4.0=1
FBD
ITD
Integer (16-bit) to
Double Integer (32-bit)
: STL
:
ITD
:
ACCU1 . ACCU1-L ITD
. ACCU2
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
MW10
L
ACCU1-L
MW10
. MD12 ACCU1
IT
B
T
-10
MD12
. ACCU1
Example: MW10 = "-10" (Integer, 16-bit)
Contents
ACCU1-H
..
..
ACCU1-L
Bit
31 . . .
before execution of ITD
XXXX
XXXX XXXX XXXX
1111
1111 1111
0110
after execution of ITD
1111
1111
1111
1111 1111
0110
1111
. . . 16 15 . . .
1111
..
..
...0
(X = 0 or 1, bits are not used for conversion)
BTI Q4.0=1
FBD
DTB
Double Integer (32-bit) to BCD
: STL
:
DTB
:
. BCD ACCU1 DTB
. ACCU2 ACCU1
: 31 28 BCD 27 0 ACCU1
0000= Positive
1111=Negative
OS OV +9,999,999 -9,999,999 BCD

. RLO . Status Word
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD10
BCD ACCU1-L
ITB
T
MW10
MD20
. MW12 ACCU1-L
BCD Integer -701
. ACCU1-L
BTI Q4.0=1
FBD
DTR
Double Integer (32-bit) to

Floating Point (32-bit)
: STL
:
DTR
:
. (Real) ACCU1 DTR
. ACCU2 ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD10
ACCU1
ITB
T
MD10
MD20
. MD20 ACCU1
ACCU1 Real Integer +500
BTI Q4.0=1
FBD
INVI
Ones Complement Integer

(16-bit)
: STL
:
INVI
:
1 . ACCU1-L 16 INVI
. ACCU1-L . 1 0 0
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MW8
MW8
ACCU1-L
INVI
T
. MW10 ACCU1-L
MW10
Contents
ACCU1-L
Bit
15 . . .
..
before execution of INVI
0110
0011
1010
1110
after execution of INVI
1001
1100
0101
0001
. I0.0=1
. Q4.0 Q4.0=1
..
...0
FBD
INVD
Ones Complement Double

Integer (32-bit)
: STL
:
INVD
:
0 1 . ACCU1 32 INVD
. ACCU1 . 1 0
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD8
MD 32
ACCU1
INVI
T
. MD12 ACCU1
MD12
Contents
ACCU1-H
Bit
31 . . .
..
before execution of INVD
0110
1111 1000 1100
0110 0011 1010 1110
after execution of INVD
1001
0000 0111 0011
1001 1100 0101 0001
Q4.0=1
..
ACCU1-L
. . . 16 15 . . . . .
..
...0
FBD
NEGI
Twos Complement Integer

(16-bit)
: STL
:
NEGI
:
0 0 1 . ACCU1-L 16 NEGI
. ACCU1-L . 1 1
. ( ) .
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
Status word generation
CC 1
CC 0
OV
OS
Result = 0
-32768 <= Result <= -1
32767 >= Result >= 1
Result = 32768
:
L
MW8
MW8
( ) ACCU1-L
NEGI
T
. MW10 ACCU1-L
MW10
.
Contents
ACCU1-L
Bit
15 . . .
..
..
...0
before execution of NEGI
0101
1101
0011
1000
after execution of NEGI
1010
0010
1100
1000
Q4.0=1
FBD
NEGD
Twos Complement Double

Integer (32-bit)
: STL
:
NEGD
:
0 0 1 . ACCU1 32 NEGI
. ACCU1 . 1 1
. ( ) .
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
Status word generation
CC 1
CC 0
OV
OS
Result = 0
-2,147,483,648 <= Result <= -1
2,147,483,647 >= Result >= 1
Result = 2,147,483,648
:
L
MD8
MD8
( ) ACCU1
NEGI
T
. MD12 ACCU1
MD12
.
Contents
Bit
before execution of NEGD
after execution of NEGD
31 . . .
0101
1010
ACCU1-H
..
..
1111 0110
0000 1001
Q4.0=1
. . . 16 15 . . .
0100 0101
1011 1010
ACCU1-L
..
..
...0
1101 0011 1000
0010 1100 1000
FBD
NEGR
Twos Complement FloatingPoint (32-bit)
: STL
:
NEGR
:
ACCU1 31 . ACCU1 32 NEGR
. ACCU1 ( 1 0 )
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD8
MD8
ACCU1
NEGR
T
. MD12 ACCU1
MD12
.
MD8 = + 6.234
Q4.0=1
MD12 = - 6.234
FBD
CAW
Change Byte Sequence

in ACCU1-L (16-bit)
: STL
:
CAW
ACCU1-L . ACCU1-L CAW :
FBD , LAD . ACCU2 ACCU1-H
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MW10
MW10
ACCU1-L
CAW
T
MW20
MW20
Contents
ACCU1-H-H
ACCU1-H-L
ACCU1-L-H
ACCU1-L-L
before execution of CAW
value A
value B
value C
value D
after execution of CAW
value A
Value B
value D
value C
CAD
Change Byte Sequence

in ACCU1 (32-bit)
: STL
:
CAD
ACCU2 ACCU1 . ACCU1 CAD :
. CAW Status Word FBD LAD .
:
L
MD10
MD10
ACCU1
CAD
T
MD20
MD20
Contents
ACCU1-H-H
ACCU1-H-L
ACCU1-L-H
ACCU1-L-L
before execution of CAD
value A
value B
value C
value D
after execution of CAD
value D
value C
value B
value A
RND
Round
: STL
:
RND
:
(Double Integer) 32 32 RND
19 18 18.5 ) .
. OS OV . (
. ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD8
MD8
MD12 ACCU1
RND
T
MD12
Value before conversion
Value after conversion
MD8 = "100.5"
=>
RND =>
MD12 = "+100"
MD8 = "-100.5"
=>
RND =>
MD12 = "-100"
FBD
. I0.0=1

Q4.0=1
. Q4.0
TRUNC
Truncate
: STL
:
TRUNC
:
(Double Integer) 32 32 TRUNC
OS OV . .
. ACCU1 .
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
MD8
MD8
ACCU1
TRUNC
T
MD12
MD12
Value before conversion
Value after conversion
MD8 = "100.5"
=>
TRUNC =>
MD12 = "+100"
MD8 = "-100.5"
=>
TRUNC =>
MD12 = "-100"
. Q4.0=1
FBD
RND+
Round to Upper
Double Integer
: STL
:
RND+
:
(Double Integer) 32 32 RND +
+2 +1.2
. OS OV . -1 -1.5
. ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
FBD
Q4.0
RND-
Round to Lower
Double Integer
: STL
:
RND:
(Double Integer) 32 32 RND -

. +1 +1.2
. ACCU1 . OS OV
. RND+ Statud word
FBD
(Counter Instruction)
(Counter Instruction) -
. CPU STEP7
CPU . Word
.
( ) 999 0 BCD
127 . 11 0
:
:
x
FR
Enable Counter (Free)
Load Current Counter Value into ACCU 1
LC
Load Current Counter Value into ACCU 1 as BCD
Reset Counter
Set Counter Preset Value
CU
Counter Up
CD
Counter Down
. FBD FBD LAD :

. LAD
FR
Enable Counter (Free)
: STL
:
FR <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
:
FR 1 0 RLO
. 1 0 RLO .
. RLO=1 1 0 RLO
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I 1.0
FR
C3
FR 1 0 I1.0
. C3
.
.
LAD
FBD
Load Current Counter

Value into ACCU1
: STL
:
L <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
:
ACCU2 ACCU1 L
ACCU1-L Integer
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
C3
C3
. ACCU1-L
.
LAD
FBD
LC Load Current Counter

Value into ACCU1 as BCD
: STL
:
LC <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
:
ACCU2 ACCU1 LC
ACCU1-L BCD
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
LC
C3
BCD C3
.. ACCU1-L
LAD
FBD
Reset Counter
: STL
:
R <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
. RLO=1 R :
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I0.2
C10
. C10 I0.2=1
LAD
FBD
Set Counter Preset Value
: STL
:
S <Counter>
. ACCU1-L 1 0 RLO S :
. Status Word . 999 0 BCD
:
A
I0.0
100 I0.0
L
s
C#100
C5 1 0 RLO ACCU1-L BCD
C5
.
FBD
LAD
CU
Counter Up
: STL
:
CU <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
:
. 1 0 RLO CU
RLO 999 . 999
.
OV .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I0.0
RLO I0.0
CU
C10
. C10 1 0
LAD
FBD
CD
Counter Down
: STL
:
CD <Counter>
Address
< Counter >
Data Type
Counter
Memory Area
C
:
. 1 0 RLO CD
. RLO 0 . 0
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
C#14
RLO I0.1
I0.1
C10 1 0
C10
I0.0
CD
C10
AN
C1
Q0.0
. C10 1 0 I0.0
Q0.0
.
LAD
FBD
FBD
S_CU
Assign Parameter and

Counter Up
: FBD
Parameter
no.
CU
S
PV
R
CV
CV_BCD
Q
Data Type
COUNTER
BOOL
BOOL
WORD
BOOL
WORD
WORD
BOOL
Memory
C
I, Q, M, D, L
I, Q, M, D, L, T, C
I, Q, M, D, L or constant
I, Q, M, D, L, T, C
I, Q, M, D, L
I, Q, M, D, L
I, Q, M, D, L

BCD

(Hex)
(BCD)

:
CU . PV 1 0 S RLO
Q . R .
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
LAD
S_CD

Counter Down
: FBD
Parameter
no.
CD
S
PV
R
CV
CV_BCD
Q
Data Type
COUNTER
BOOL
BOOL
WORD
BOOL
WORD
WORD
BOOL
Memory
C
I, Q, M, D, L
I, Q, M, D, L, T, C
I, Q, M, D, L, T, C
I, Q, M, D, L
I, Q, M, D, L
I, Q, M, D, L

BCD

(Hex)
(BCD)

:
CD . PV 1 0 S RLO
Q . R .
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
LAD
S_CUD

Counter Up/Down
: FBD
Parameter
Data Type Memory
no.
COUNTER C
CU
BOOL
I, Q, M, D, L
CD
BOOL
I, Q, M, D, L
BOOL
I, Q, M, D, L, T, C
PV
WORD
BOOL
I, Q, M, D, L, T, C
CV
WORD
I, Q, M, D, L
(Hex)
CV_BCD
WORD
I, Q, M, D, L
(BCD)
BOOL
I, Q, M, D, L

BCD

:
CU . . PV 1 0 S RLO
R . CD
. Q .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
LAD
(DB Instructions)
(Data Block Instructions) -
.
. FC FB OB Shared DB :
. FB FB Instance DB :
: DB
x
OPN
Open a Data Block
CDB
Exchange Shared DB and Instance DB
L DBLG
Load Length of Shared DB in ACCU 1
L DBNO Load Number of Shared DB in ACCU 1
L DILG
Load Length of Instance DB in ACCU 1
L DINO
Load Number of Instance DB in ACCU 1
. LAD FBD OPN
(DB Instructions)
OPN
Open a Data Block
: STL
:
OPN <Data Block>

Address
< Data Block >
Data Block Type

DB , DI
Source Address
1 to 65535
:
: Instance Shared OPN
OPN
DBn
n Shared
OPN
DIn
n Instance
. Instance Shared
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
OPN
DB10
DBX0.0
Q4.0
DB10
Q4.0 DBX0.0
.
LAD
FBD
(DB Instructions)
CDB
Exchange Shared DB
and Instance DB
: STL
:
CDB
:
Instance Shared . Instance Shared CDB
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
OPN
DB10
OPN
DI20

Instance Shared
Instance CDB
CDB
. Shared
L DBLG
Load Length of
Shared DB in ACCU1
: STL
:
L DBLG
:
ACCU1 Shared ACCU2 ACCU1
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
OPN
DB10
DBLG
Shared

ERRO MD10
MD10
<
JC
ERRO
(DB Instructions)
L DBNO
Load Number of
Shared DB in ACCU1
: STL
:
L DBNO
Shared ACCU2 ACCU1 :
. Status Word ACCU1
:
OPN
DB10
Shared
DBNO
( )
MW0
. MW0
L DILG
Load Length of
Instance DB in ACCU1
: STL
:
L DILG
Instance ACCU2 ACCU1 :
. ACCU1
:
OPN
DI20
DILG
Instance

ERRO MW10
MW10
<
JC
ERRO
L DINO Load Number of

Instance DB in ACCU1
: STL
:
L DINO
Instance ACCU2 ACCU1 :
Status Word . ACCU1
:
OPN
DI20
Instance
DBNO
( )
MW0
. MW0
173
(Logic Control Instructions) -
(jump)
(LOOP) .
.Loop Label .
: Loop jump
. Label x
. Label x
(Test:
) : Label Loop x
. x
. Label Label x
. LOOP
. Label . Label x
. Program Code 32767 Word Label x
:
: :
x
x
JU
JL
Jump Unconditional
Jump to Labels
: RLO :
x
x
x
x
JC
JCN
JCB
JNB
Jump if RLO = 1
Jump if RLO = 0
Jump if RLO = 1 with BR
: (RLO )Status Word :

x
x
x
x
JBI
JNBI
JO
JOS
Jump if BR = 1
Jump if BR = 0
Jump if OV = 1
Jump if OS = 1
: :
x
x
x
x
x
x
x
JZ
JN
JP
JM
JPZ
JMZ
JUO
Jump if Zero
Jump if Not Zero
Jump if Plus
Jump if Minus
Jump if Plus or Zero
Jump if Minus or Zero
Jump if Unordered
JU
Jump Unconditional
: STL
:
JU <jump Label>
:
Label Status Word JU
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I1.0
JU
I1.2
JC
DELE
FORW
L
INC
DELE:
FORW:
MB10
1
.

jump Label
MB10
Label JU
JU
FORW
) (DELE )
(JC DELE
MB10
(DELE )
I2.1
( Label )
.
LAD
FBD
JL
Jump to Labels
: STL
:
JL <jump Label>
:
( ) JL . JL
JU ACCU1-L-L=0 JU . JU
254 ..... 3 2 ACCU1-L-L JU ACCU1-L-L=1
JU JL JU .
. JL
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MB0
JL
LSTX
. LSTX ACCU1-L-L>3
JU
SEG0
. SEG0 ACCU1-L-L=0
JU
SEG1
. SEG1 ACCU1-L-L=1
JU
COMM
. COMM ACCU1-L-L=2
JU
LSTX:
JU
SEG0:
SEG3
. ACCU1-L-L MB0
. SEG3 ACCU1-L-L=3
COMM
*
JU
SEG1:
COMM
. JU
*
*
JU
SEG3:
COMM
*
*
COMM:
*
LAD
FBD
JC
Jump if RLO=1
: STL
:
JC <jump Label>
Label RLO=1 JC :
. (Conditional)
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
I1.0
JC
I1.2
I1.2 I1.0 RLO=1
JC
JOVR:
JOVR
IW8
MW22
. JOVR
I2.1
LAD
JU
. I0.0
JCN
Jump if RLO=0
FBD
: STL
:
JCN <jump Label>

JC Label RLO=0 JCN :
. JC Status Word . (Conditional Not)
. JMPN LAD FBD
JCB
Jump if RLO=1 With BR
: STL
:
JCB <jump Label>

RLO=1 Status Word BR RLO JCB :
JC Status Word . Label
:
A
I1.0
RLO JCB
I1.2
RLO=1 BR
JCB
JOVR:
JOVR
IW8
MW22
. JOVR I1.2 I1.0
I2.1
FBD LAD
BR JMP
.
JNB
Jump if RLO=0 With BR
: STL
:
JNB <jump Label>

RLO=0 Status Word BR RLO JNB :
JC Status Word . Label
:
A
I1.0
JNB
I1.2
I1.2 I1.0 RLO=0
JNB
JOVR:
JOVR
IW8
MW22
. JOVR
I2.1
FBD LAD
BR JMPN
.
JBI
Jump if BR=1
: STL
:
JBI <jump Label>

Label BR=1 JBI :
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
CALL
JBI
FC1
JBI
TEST
FC1
) BR=1
*
JU
Test:
Test ( BR SAVE
COMM
I2.2
*
COMM:
( JMP BR ) LAD
( JMP BR ) FBD
JNBI
Jump if BR=0
: STL
:
JNBI <jump Label>

status Word . Label BR=0 JNBI :
. JBI
FBD LAD
JBI
JO
Jump if OV=1
: STL
:
JO <jump Label>
:
(Overflow) Status Word OV JO
. Label
. JOS JO
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
MW10
JO OV=1
*I
. OVER
JO
OVER
MW10
OVER:
NEXT:
JU
NEXT
AN
M4.0
Q4.0
NOP
( JMP OV ) LAD
( JMP OV ) FBD
JOS
Jump if OS=1
: STL
:
JOS <jump Label>

:
(Overflow)
Status Word OS JOS
. Label
. JOS JO
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
MW10
50 MW200
*I
L
MW200
50
OVER
MW10
OS
JU
OVER:
NEXT:
NEXT
AN
M4.0
Q4.0
NOP
. OVER
JO JOS
/I
JOS
JOS OS=1
( JMP OS ) LAD
( JMP OS ) FBD
JZ
Jump if Zero
: STL
:
JZ <jump Label>
:
. Label JZ
: Status Word
CC1=0
CC0=0
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
30
-I
JZ
ZERO
MW10
30 MW10
. ZERO JZ
*
JU
NEXT
ZERO:
AN
M4.0
NEXT:
NOP
Q4.0
0
( JMP ) LAD
( JMP ) FBD
JN
Jump if Not Zero
: STL
:
JN <jump Label>
:
. Label JN
: Status Word
CC1=0
CC1=1
CC0=1
CC0=0
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
30
-I
JN
30 MW10
. NOZE JN
NOZE
MW10
*
JU
NOZE:
NEXT:
NEXT
AN
M4.0
Q4.0
NOP
( JMP ) LAD
( JMP ) FBD
JP
Jump if Plus
: STL
:
JP <jump Label>
:
. Label JP
: Status Word
CC1=1
CC0=0
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
30
-I
JP
30 MW10
. POS JP
POS
MW10
*
JU
POS:
AN
NEXT:
NOP
NEXT
M4.0
Q4.0
0
( JMP ) LAD
( JMP ) FBD
JM
Jump if Minus
: STL
:
JM <jump Label>
:
. Label JM
: Status Word
CC1=0
CC0=1
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
L
MW10
30
-I
JM
30 MW10
. NEG JM
NEG
MW10
*
JU
NEG:
AN
NEXT:
NOP
NEXT
M4.0
Q4.0
0
( JMP ) LAD
( JMP ) FBD
JPZ
Jump if Plus Or Zero
: STL
:
JPZ <jump Label>

:
. Label JPZ
: Status Word
CC1=0
CC0=0
CC1=1
CC0=0
LAD
) FBD LAD
( JMP
JMZ
Jump if Plus Or Zero
: STL
:
JMZ <jump Label>

:
. Label JMZ
: Status Word
FBD
CC1=0
CC0=0
CC1=1
CC0=0
) FBD LAD
( JMP
JUO
Jump if Unordered
: STL
:
JUO <jump Label>

:
Status Word CC0 CC1 JUO
: . Label
x
x

Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
ERRO:
NEXT:
L
L
/D
JUO
T
JU
S
NOP
ID0
ID4
ID4=0
. ERRO JUO
ERRO
MD10
NEXT
Q4.1
0
( JMP Unorder ) LAD
( JMP Unorder ) FBD
187
LOOP
Loop
: STL
:
LOOP <jump Label>

:
. ACCU1-L LOOP
. ACCU1-L=0
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
*
NEXT:
MW10
MD20
MD20
MW10
LOOP
MD20
.
NEXT
FBD LAD
( JMP
(Integer Math Instructions) -
.

CPU .
: .
x
+I
Add ACCU 1 and ACCU 2 as Integer (16-bit)
-I
Subtract ACCU 1 from ACCU 2 as Integer (16-bit)
*I
Multiply ACCU 1 and ACCU 2 as Integer (16-bit)
/I
Divide ACCU 2 by ACCU 1 as Integer (16-bit)
Add Integer Constant (16, 32 Bit)
+D
Add ACCU 1 and ACCU 2 as Double Integer (32-bit)
-D
Subtract ACCU 1 from ACCU 2 as Double Integer (32-bit)
*D
Multiply ACCU 1 and ACCU 2 as Double Integer (32-bit)
/D
Divide ACCU 2 by ACCU 1 as Double Integer (32-bit)
MOD
Division Remainder Double Integer (32-bit)
: CC1,CC0 , OV , OS
CC 1
CC 0
OV
OS
0 (zero)
16 bits: -32 768 <= result< 0 (negative number)
32 bits: -2 147 483 648 <=result < 0 (negative number)

16 bits: 32 767 >= result > 0 (positive number)
32 bits: 2 147 483 647 >= result > 0 (positive number)
. os :*
189
CC 1
CC 0
OV
OS
CC 1
CC 0
OV
OS
+D: result = -4 294 967 296
/D or MOD: division by 0

Underflow (addition)
16 bits: result = -65536
32 bits: result = -4 294 967 296
Underflow (multiplication)
16 bits: result < -32 768 (negative number)
32 bits: result < -2 147 483 648 (negative number)
Overflow (addition, subtraction)
16 bits: result > 32 767 (positive number)
32 bits: result > 2 147 483 647 (positive number)
Overflow (multiplication, division)
16 bits: result > 32 767 (positive number)
32 bits: result > 2 147 483 647 (positive number)
Underflow (addition, subtraction)
16 bits: result < -32. 768 (negative number)
32 bits: result < -2 147 483 648 (negative number)
Division by 0
Operation
+I
Add ACCU1 And ACCU2

as Integer(16-Bit)
: STL
:
+I
:
. ACCU1-L ACCU2-L ACCU1-L +I
. CC1,CC0, OV,OS RLO .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
MW2 MW0
L
MW0
MW2
MW10
. MW10
LAD
Q4.0 I0.0=1
)
. Q4.0 ( 32768
FBD
191
-I
Subtract ACCU1 from

ACCU2 as Integer(16-Bit)
-I
: STL
:
. ACCU1-L ACCU2-L ACCU1-L -I :

LAD
I0.0=1
Q4.0
. Q4.0
*I
Multiply ACCU1 And

*I
: STL
:
. ACCU1-L ACCU2-L ACCU1-L *I :

. Status Word .
FBD
/I
Divide ACCU2 by
: STL
:
/I
ACCU1- ACCU1-L ACCU1-L ACCU2-L / I :
.. Status Word . H
LAD
Add Integer Constant

(16 , 32Bit)
: STL
:
+
:
ACCU2-L . ACCU1-L ACCU1-L +
: .
+32767
-32768
+2,147,483,647
-2,147,483,648
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
MW0
L
MW0
2589
MW10
. MW10
LAD
Q4.0 I0.0=1
Q4.0
FBD
193
+D
Add ACCU1 And ACCU2

as Double Integer(32-Bit)
: STL
:
+D
:
. ACCU1 ACCU2 ACCU1 +D
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
MD4 MD0
L
MD0
MD4
MD10
. MD10
LAD
Q4.0 I0.0=1
Q4.0
FBD
-D
Subtruct ACCU1 from ACCU2

-D
: STL
:
. ACCU1 ACCU2 ACCU1 -D :

CC1,CC0, OV,OS RLO .
LAD
*D
Multiply ACCU1 And ACCU2

: STL
:
*D
. ACCU1 ACCU2 ACCU1 *D :
FBD
/D
Divide ACCU2 by ACCU1

: STL
:
/D
:
. ACCU2 ACCU1 ACCU1 ACCU2 /D
. CC1,CC0, OV,OS RLO
LAD
195
MOD
Division Remainder
Double Integer(32-Bit)
: STL
:
MOD
:
ACCU1 ACCU2 . MOD
RLO . . ACCU1
. CC1,CC0, OV,OS
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
MD4 MD0
L
MD0
MD4
MD10
MD4=4 MD0=13 . MD10

. MD10=1
LAD
I0.0=1
Q4.0
. Q4.0
FBD
(Floating-Point Math Instructions) -

.

CPU .
.
:
x
+R
Add ACCU 1 and ACCU
-R
Subtract ACCU 1 from ACCU 2
*R
Multiply ACCU 1 and ACCU 2
/R
Divide ACCU 2 by ACCU 1
:
x
ABS
Absolute Value
SQR
Generate the Square
SQRT
Generate the Square Root
EXP
Generate the Exponential Value
LN
Generate the Natural Logarithm
SIN
Generate the Sine of Angles
COS
Generate the Cosine of Angles
TAN
Generate the Tangent of Angles
ASIN
Generate the Arc Sine
ACOS
Generate the Arc Cosine
ATAN
Generate the Arc Tangent
197
: CC1,CC0 , OV , OS
CC 1 CC 0 OV
OS
+0, -0 (Null)
-3.402823E+38 < result < -1.175494E-38 (negative number)
+1.175494E-38 < result < 3.402824E+38 (positive number)
. os :*

Underflow
CC 1 CC 0 OV
OS
-1.175494E-38 < result < - 1.401298E-45 (negative number)

Underflow
+1.401298E-45 < result < +1.175494E-38 (positive number)
Overflow
Result < -3.402823E+38 (negative number)
Overflow
Result > 3.402823E+38 (positive number)
Not a valid floating-point number or illegal instruction
(input value outside the valid range)
+R
Add ACCU1 And ACCU2

as Floating-Point (32-Bit)
: STL
:
+R
:
. ACCU1 ACCU2 ACCU1 +R
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
MD4 MD0
L
MD0
MD4
MD10
. MD10
LAD
Q4.0 I0.0=1
Q4.0
FBD
199
-R
Subtruct ACCU1 from ACCU2

: STL
-R
:
:
. ACCU1 ACCU2 ACCU1 -R

LAD
*R
Multiply ACCU1 And ACCU2

: STL
*R
:
:
. ACCU1 ACCU2 ACCU1
*R

FBD
/R
Divide ACCU2 by ACCU1

/R
: STL
:
:
. ACCU2 ACCU1 ACCU1 ACCU2 /R

. CC1,CC0, OV,OS RLO
LAD
ABS
Absolute Value of
Floating-Point (32-Bit)
: STL
:
ABS
:
. ACCU1 ACCU1 ABS
. Staut Word
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. MD10 MD8
L
MD8
ABS
T
MD10
LAD
I0.0=1
. Q4.0
FBD
201
SQR
Square of Floating-Point (32-Bit)
: STL
:
SQR
. ACCU1 ACCU1 SQR :
. CC1,CC0, OV,OS
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
. MD10 MD0
L
MD0
SQR
T
MD10
LAD
I0.0=1
. Q4.0
SQRT
Square Root of
: STL
:
SQRT
:
. ACCU1
ACCU1 SQRT
. CC1,CC0, OV,OS
I0.0=1
. Q4.0
FBD
EXP
Exponential Value of
: STL
:
EXP
:
. ACCU1 ACCU1 e EXP
. CC1,CC0, OV,OS
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. MD10 MD0 e
L
MD0
EXP
T
MD10
LAD
I0.0=1
. Q4.0
LN
Natural Logarithm of
: STL
:
LN
. ACCU1 ACCU1 LN :
CC1,CC0, OV,OS
FBD
203
SIN
Sine of Angles as
: STL
:
SIN
:
ACCU1 ACCU1 SIN
. CC1,CC0, OV,OS .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. MD10 MD0
L
MD0
SIN
T
MD10
LAD
I0.0=1
. Q4.0
FBD
COS
Cosine of Angles as
: STL
:
COS
:
ACCU1 ACCU1 COS
. CC1,CC0, OV,OS .
:
. MD10 MD0
L
MD0
COS
T
MD10
LAD
TAN
Tangent of Angles as
: STL
:
TAN
:
ACCU1 ACCU1 TAN
. CC1,CC0, OV,OS .
FBD
ASIN
Arc Sine of Floating-Point (32-Bit)
: STL
:
ASIN
:
ACCU1 ACCU1 ASIN
. CC1,CC0, OV,OS .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
. MD10 MD0
L
MD0
ASIN
T
MD10
LAD
I0.0=1
. Q4.0
FBD
ACOS Arc Cosine of Floating-Point (32-Bit)
: STL
:
ACOS
:
ACCU1 ACOS
. CC1,CC0, OV,OS . ACCU1
:
. MD10 MD0
L
MD0
ACOS
T
MD10
LAD
ATAN
Arc Tangent of Floating-Point (32-Bit)
: STL
:
ATAN
:
ACCU1 ACCU1 ATAN
. CC1,CC0, OV,OS .
FBD
207
(Load and Transfer Instructions) -
CPU / Transfer Load

. RLO CPU . CPU
:
x
Load
L STW
Load Status Word into ACCU 1
LAR1 AR2
Load Address Register 1 from Address Register 2
LAR1 <D>
Load Address Register 1 with Double Integer (32-bit Pointer)
LAR1
Load Address Register 1 from ACCU 1
LAR2 <D>
Load Address Register 2 with Double Integer (32-bit Pointer)
LAR2
Transfer
T STW
Transfer ACCU 1 into Status Word
TAR1 AR2
Transfer Address Register 1 to Address Register 2
TAR1 <D>
Transfer Address Register 1 to Destination (32-bit Pointer)
TAR2 <D>
Transfer Address Register 2 to Destination (32-bit Pointer)
TAR1
Transfer Address Register 1 to ACCU 1
TAR2
CAR
Exchange Address Register 1 with Address Register 2
. FBD LAD Transfer Load :

. Transfer Load
. LAD FBD
Load
: STL
:
L <Address>
Address
<address>
Data type
BYTE
WORD
DWORD
Memory area
Q , I , PI , M , L ,D, Pointer,
Parameter
Source address
0...65535
0...65534
0...65532
:
0 ACCU1 ACCU2 ACCU1 L
. ACCU1
Status Word
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Writes:
:
L
IB10
MB120
. ACCU1-L-L MB120
DBB12
. ACCU1-L-L DBB12
DIW15
. ACCU1-L DIW15 Word Instance
LD252
. ACCU1 LD252 Dword Local Data
P#I8.7
OTTO
. ACCU1-L-L IB10
. ACCU1 I8.7 Pointer

. ACCU1 OTTO
Load
Contents of ACCU 1
ACCU1-H-H
ACCU1-H-L
ACCU1-L-H
ACCU1-L-L
before execution of load instruction
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
after execution of L MB10 (L <Byte>)
00000000
00000000
00000000
<MB10>
after execution of L MW10 (L <word>)
00000000
00000000
<MB10>
<MB11>
after execution of L MD10
<MB10>
<MB11>
<MB12>
<MB13>
(L <double word>)
X = "1" or "0"
209
L STW
Load Status Word

into ACCU1
: STL
:
L STW
:
Status Word
. ACCU1 Status Word L STW
. L STW .
Bit
Content:
L AR1
31-9
BR
CC 1
CC 0
OV
OS
OR
STA
RLO
/FC
Load Address Register1

From ACCU1
: STL
:
LAR1
:
. ACCU2 ACCU1 . ACCU1 AR1 LAR1
. Status Word
L AR1 <D> Load Address Register1

with Double Integer (32-Bit)
: STL
:
LAR1 <D>
Address
Data type
DWORD
Pointer Constant
<D>
Memory area
D,M,L
Source address
0...65532
:
. ACCU2 ACCU1 . Dword AR1 LAR1
. Status Word
:
LAR1
DBD20
. AR1
DBD20
LAR1
DID30
. AR1
Instance DID30
LAR1
LD180
. AR1 LD180 Dword Local Data
LAR1
MD24
LAR1
P#M100.0
. AR1 MD24 Dword

. AR1 M100.0 Pointer
LAR1 AR2 Load Address Register1

from Address Register2
: STL
:
LAR1 AR2
:
. ACCU2 ACCU1 . AR1 AR2 LAR1 AR2
. Status Word
L AR2
Load Address Register2

From ACCU1
: STL
:
LAR2
:
. ACCU2 ACCU1 . ACCU1 AR2 LAR2
. Status Word
L AR2 <D> Load Address Register2

with Double Integer (32-Bit)
: STL
:
LAR2 <D>
Address
Data type
DWORD
Pointer Constant
<D>
Memory area
D,M,L
Source address
0...65532
:
. ACCU2 ACCU1 . Dword AR2 LAR2
. Status Word
:
LAR2
DBD20
. AR2
DBD20
LAR2
DID30
. AR2
Instance DID30
LAR2
LD180
. AR2 LD180 Dword Local Data
LAR2
MD24
LAR2
P#M100.0
. AR2 MD24 Dword

. AR2 M100.0 Pointer
211
Transfer
: STL
:
T <Address>
Address
<address>
Data type
BYTE
WORD
DWORD
Memory area
Q , I , PQ , , M , L , D
Source address
0...65535
0...65534
0...65532
:
ACCU1 . ACCU1 T
Master Control Relay .
. ACCU1 0 T MCR=0
. Status Word
:
T
QB10
MW120
DBD2
. QB10 ACCU1-L-L
. MW120 word ACCU1-L

DBD2 Dword ACCU1
..
T STW
Transfer ACCU1
into Status Word
: STL
:
T STW
:
. Status Word 8 0 T STW
. Status Word
. 1,4,5,6,7,8 OR,STA,/FC S7-300 CPU :
CAR
Exchange Address Register1

With Address Register2
: STL
:
CAR
:
Status
. () AR1 AR2 CAR

. Word
TAR1
Transfer Address Register1

to ACCU1
: STL
:
TAR1
:
. ACCU2 ACCU1 . ACCU1 AR1 TAR1
. Status Word
TAR1<D> Transfer Address Register1

To Destination (32-Bit Pointer)
: STL
:
TAR1 <D>
Address
<D>
Data type
DWORD
Memory area
D,M,L
Source address
0...65532
:
(D) (M) AR1 TAR1
Status Word . ACCU2 ACCU1 . (L)
.
:
TAR1
DBD20
. DBD20 AR1
TAR1
DID30
. Instance DID30 AR1
TAR1
LD180
. LD180 Dword Local Data AR1
TAR1
MD24
. MD24 Dword AR1
TAR1 AR2 Transfer Address Register1

to Address Register2
: STL
:
TAR1 AR2
:
. ACCU2 ACCU1 . AR2 AR1 TAR1 AR2
. Status Word
213
TAR2
Transfer Address Register1

to Address Register2
: STL
:
TAR2
:
.. ACCU2 ACCU1 . ACCU1 AR2 TAR2
. Status Word
TAR2<D> Transfer Address Register2

To Destination (32-Bit Pointer)
: STL
:
TAR2 <D>
Address
<D>
Data type
DWORD
Memory area
D,M,L
Source address
0...65532
:
(D) (M) AR2 TAR2
Status Word . ACCU2 ACCU1 . (L)
.
:
TAR1
DBD20
. DBD20 AR2
TAR1
DID30
. Instance DID30 AR2
TAR1
LD180
. LD180 Dword Local Data AR2
TAR1
MD24
. MD24 Dword AR2
215
(Program Control Instructions) -
:
.
215
BE
Block End
BEC
Block End Conditional
BEU
Block End Unconditional
CALL
Block Call
CC
Conditional Call
UC
Unconditional Call
Call FB
Call FC
Call SFB
Call SFC
Call Multiple Instance
Call Block from a Library
MCR
(Master Control Relay)
MCR(
Save RLO in MCR Stack, Begin MCR
)MCR
End MCR
MCRA
Activate MCR Area
MCRD
Deactivate MCR Area
215
BE
BEU
Block End
: STL
:
BE
BEU
:
( ) BEU , BE
(Local Data) . (Call)

(re-opened) Call .
.
.
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
NEXT:
A
JC
*
BE
NOP
I1.0
NEXT
I1.0=1
JC I1.0=0
. BE
FBD LAD
BEC
: STL
:
BEC
:
. 1 RLO BE BEC
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
BEC
L
T
I1.0
IW4
MW10
I1.0=1
BEC I1.0=0
.
FBD LAD
CALL
Block Call
: STL
:
CALL < logic block identifier>

:
SFC SFB FB FC CALL
.
DB SFB FB . . RLO
Step7
DB .
:
Logic Block
FC
SFC
FB
SFB
Block Type
Function
System function
Function block
System function block
Absolute Address Call Syntax

CALL FCn
CALL SFCn
CALL FBn1,DBn2
CALL SFBn1,DBn2
. Symbol Table
CALL STL
.
Formal Parameter
. Actual Parameter
CALL
FC6
Formal parameter
Actual parameter
NO OF TOOL
:= MW100
TIME OUT
:= MW110
FOUND
:= Q 0.1
ERROR
:= Q 100.0
. CALL
Actual Parameter FB
: . Call Instance
CALL
FB99 , DB2
Formal parameter
Actual parameter
MAX_RPM
:= #RPM2_MAX
MIN_RPM
:= #RPM2
MAX_POWER
:= #POWER2
MAX_TEMP
:= #TEMP2
217
CALL
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
LAD:
FBD LAD
LAD/STL/FBD FB FC
.
FB FC
FBD LAD
.
SFB SFC
. Library
FBD SFC LAD SFB
.
FBD:
: STL
:
CALL # Variable Name

:
. CPU DB FB Multiple Instance
FB2
FB FB1,DB1 DB FB
FB FB1 Declaration DB1 FB3

: Static
Decl.
Stat
Stat
Name
Type
Test2
FB2
Test3
FB3
. DB FB FB1
CALL # TEST2
CALL # TEST3
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
LAD
FBD
219
CC
Conditional Call
: STL
:
CC < logic block identifier>

:
RLO=1 SFC FC CC
CC .
. .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
CC
A
I1.0
FC6
M3.0
FC6 I1.0=1
.
LAD
FBD
UC
Unconditional Call
: STL
:
UC < logic block identifier>

:
. RLO SFC FC UC
CC
. .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
UC
I1.0
FC6
FC6 I1.0
LAD
FBD
221
MCR
Master Control Relay
: STL
MCR
.
:
: MCR . MCR
x
= <bit>
S <bit>
R <bit>
T <byte>, T <word>, T <double word>
. T = MCR =0

R S .
MCR=1 .
. .
Signal State of MCR
= <bit>
0 ("OFF")
S <bit>, R <bit>
1 ("ON")
T <byte>, T <word>
T <double word>

0
: MCR
x
MCRA
Activate MCR Area
x
MCR(
Begin MCA Area
x
)MCR
End MCR Area
x
MCRD
Deactivate MCR Area
. . MCRD MCRA MCR

)MCR MCR( . Status Word
. MCR RLO MCR( . MCR

. MCR ON MCR =1 RLO=1
MCR . OFF MCR=0 RLO = 0
. Nested )MCR MCR(
MCR . )MCR MCR(
. )MCR MCR( Status Word . MCRF
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
MCRA
A
MCR(
A
=
L
T
)MCR
MCRD
A
=
I 1.0
I 4.0
Q 8.0
MW 20
QW 10
I 1.1
Q 8.1
I 1.0=1
MCR I1.0 =0
MCR Qw20 Q8.0
.
MCR

. MCR
LAD
FBD
223
(Shift and Rotate Instructions) -
(
. .
. 2n n
2n n .
.
) 0
. 1 0
(Sign Bit
) CC1 . 0 1
. (Jump) CC1 . OV , CC0 (Status Word
RLO . Status Word
: Status Word .
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
x
SSI Shift Sign Integer (16-bit)
SSD Shift Sign Double Integer (32-bit)
SLW Shift Left Word (16-bit)
SRW Shift Right Word (16-bit)
SLD Shift Left Double Word (32-bit)
SRD Shift Right Double Word (32-bit)
(
. Rotate
Rotate 0 Shift
(Status Word ) CC1 .
. (Jump) CC1 . OV , CC0
:
x
RLD Rotate Left Double Word (32-bit)
RRD Rotate Right Double Word (32-bit)
RLDA Rotate ACCU 1 Left via CC 1 (32-bit)
RRDA Rotate ACCU 1 Right via CC 1 (32-bit)
SSI
Shift Sign Integer (16-Bit)
SSI
: STL
SSI < Number>
:
:
ACCU1-L ( ) SSI
SSI . ACCU1-H .
SSI<Number> ACCU2-L-L
0 . 15 0 . Number
. No operation NOP
:
L
SSI
T
+10
1
QW0
10
( ) 5
15
14
13
12
11
10
ACCU1-L

.
1
.
LAD
MW2 I0.0 1 MW0

. Q4.0 MW4
FBD
LAD
225
SSD
Shift Sign Double Integer (32-Bit)
: STL
:
SSD
SSD < Number>

:
ACCU1 ( ) SSD
ACCU2-L-L
SSD .
Number SSD<Number>
NOP 0 . 15 0 .
. No operation
:
. SSD7
Contents
Bit
before execution of SSD 7
after execution of SSD 7
31 . . .
1000
1111
ACCU1-H
..
..
1111 0110
1111 0001
. . . 16
0100
1110
15 . . .
0101
1100
ACCU1-L
..
..
...0
1101 0011 1011
1000 1011 1010
:
L
L
SSD
JP
+3
MD20
Next
3
SSD . MD20
. ( ) ACCU1
CC0=0 CC1=1 1
JP
. Next
LAD
MW4 I0.0 1 MD0

. Q4.0 MD10
FBD
LAD
SLW
Shift Left Word (16-Bit)
: STL
:
SLW
SLW < Number>
:
. ACCU1-L Word SLW

SLW . ACCU1-H
SLW<Number> ACCU2-L-L
0 . 15 0 . Number
. No operation NOP
:
L
SLW1
T
+3
3
MW0 ( )
MW0
15
14
13
12
11
10
:
. SLW5
Contents
ACCU1-H
Bit
31 . . .
..
before execution of SLW 5
0101
after execution of SLW 5
0101
..
ACCU1-L
. . . 16
15 . . .
..
..
...0
1111 0110
0100
0101
1101
0011
1011
1111 0110
0100
1010
0111
0110
0000
LAD
MW2 I0.0 1 MW0

. Q4.0 MW4
FBD
LAD
227
SRW
Shift Right Word (16-Bit)
: STL
:
SRW
SRW < Number>

:
ACCU1-L Word SRW

SRW . ACCU1-H .
SRW<Number> ACCU2-L-L
0 . 15 0 . Number
. No operation NOP
:
. SRW6
.
Contents
ACCU1-H
ACCU1-L
Bit
31 . . .
..
..
. . . 16
15 . . .
..
..
...0
before execution of SRW 6
0101
1111
0110
0100
0101
1101
0011
1011
after execution of SRW 6
0101
1111
0110
0100
0000
0001
0111
0100
LAD
MW2 I0.0 1 MW0

. Q4.0 MW4
FBD
LAD
SLD
Shift Left Double Word (32-Bit)
SLD
SLD < Number>
: STL
:
:
. ACCU1 DWord SLD

ACCU2-L-L
SLD
32 0 . Number SLD<Number>
. No operation NOP 0 .
. Dword :
. SHL_W SHL_DW : FBD LAD
SRD
Shift Right Double Word (32-Bit)
SRD
SRD < Number>
: STL
:
:
. ACCU1 DWord SRD

ACCU2-L-L
SRD
32 0 . Number SRD<Number>
. No operation NOP 0 .
:
L
L
SRD
JP
+3
MD20
Next
3
SRD . MD20
. ( ) ACCU1
CC0=0 CC1=1 1
JP
. Next
. SHR_W SHR_DW : FBD LAD
229
RLD
Rotate Left Double Word (32-Bit)
: STL
:
RLD
RLD < Number>

:
RLD .. ACCU1 RLD

RLD <Number> ACCU2-L-L
0 . 32 0 . Number
. No operation NOP
:
Contents
Bit
before execution of RLD 4
after execution of RLD 4
31 . . .
0101
1111
ACCU1-H
..
..
1111
0110
0110
0100
. . . 16
0100
0101
15 . . .
0101
1101
ACCU1-L
..
..
1101
0011
0011
1011
...0
1011
0101
LAD
MW4 I0.0 1 MD0

. Q4.0 MD10
FBD
LAD
RRD
Rotate Right Double Word (32-Bit)
: STL
:
RRD
RRD < Number>

:
RRD . ACCU1 RRD

RLD <Number> ACCU2-L-L
0 . 32 0 . Number
. No operation NOP
:
Contents
Bit
before execution of RRD 4
after execution of RRD 4
31 . . .
0101
1011
ACCU1-H
..
..
1111
0110
0101
1111
. . . 16
0100
0110
15 . . .
0101
0100
ACCU1-L
..
..
1101
0011
0101
1101
...0
1011
0011
LAD
MW4 I0.0 1 MD0

. Q4.0 MD10
FBD
LAD
231
RLDA
: STL
Rotate Left Double Word Via CC1 (32-Bit)
RLDA
:
:
. CC1 ACCU1 Dword

. CC1 CC1 ACCu1
. CC1 OV , CC0
. RLDA :
Contents
CC
1
Bit
ACCU1-H
before execution of RLDA
31 . .
.
0101
after execution of RLDA
1011
..
ACCU1-L
..
1111
0110
1110
1100
. . . 16
0100
15 . .
.
0101
..
..
...0
1101
0011
1011
1000
1011
1010
0111
011X
(X = 0 or 1, previous signal state of CC 1)
. : FBD LAD
RRDA
Rotate Right Double Word Via CC1 (32-Bit)
RRDA
: STL
:
:
. CC1 ACCU1 Dword

OV , . CC1 CC1
. CC1 CC0
. RRDA :
Contents
CC 1
Bit
ACCU1-H
31 . . .
..
ACCU1-L
..
before execution of RRDA
0101
1111
...
16
0110 0100
after execution of RRDA
X010
1111
1011 0010
15 . .
.
0101
..
..
...0
1101
0011
1011
0010
1110
1001
1101
(X = 0 or 1, previous signal state of CC 1)
: FBD LAD
(Timer Instructions) -
CPU . CPU CPU
. 9 0 ( ) Word CPU
.
:
: W#16#txyz .

BCD
xyz
. .
: S5T#aH_bM_cS_dMS .
MS

a , b, c
. 9990 2H_46M_30S
. Word ( Time Base )

.
233
Resolution
:
Resolution
Range
0.01 second
10MS to 9S_990MS
0.1 second
100MS to 1M_39S_900MS
1 second
1S to 16M_39S
10 seconds
10S to 2H_46M_30S
BCD .
127 . 13 12 . 11 0
. 1
.

t
.

t
.

t
.
t
t .
Extended
Pulse
Timer
On-Delay
Timer
t (
Retentive
On-Delay
Timer
1 (
Off-Delay
Timer
Pulse
Timer
:
x
x
x
x
x
x
x
x
x
FR
L
LC
R
SD
SE
SF
SP
SS
Enable Timer (Free)

Load Current Timer Value into ACCU 1 as Integer
Load Current Timer Value into ACCU 1 as BCD
Reset Timer
On-Delay Timer
Extended Pulse Timer
Off-Delay Timer
Pulse Timer
Retentive On-Delay Timer
FR
Enable Timer (free)
: STL
:
FR <timer>
:
. 1 0 RLO FR

. LAD FBD . Restart
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
FR
I2.0
T1
I2.1
S5T#10S
SP
T1
I2.2
T1
T1
Q4.0
T1
MW10
I2.0
I2.1 10 T1 I2.1
FR
I2.0
.
I2.0 RLO (
T1
I2.0 RLO .
.
I2.0 RLO I2.1 (

I2.0 RLO . T1
.
I2.0 RLO I2.1 (
. T1
235
Load Current Time Value as Integer
: STL
L < Timer >
CPU ACCU2 ACCU1 :

CPU (Time Base) . ACCU1-L
. Status Word .
L
T1
. t1 :
BI : FBD LAD
LC
Load Current Time Value as BCD
LC < Timer >
: STL
:
( ). BCD :
SP
Pulse Timer
: STL
SP < Timer>
RLO . RLO :
. One Shot .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
L
SP
A
R
A
=
I0.0
S5T#2S
T5
I0.1
T5
T5
Q4.0
. I0.0 T5
. I0.0
I0.1 . Q4.0
.
LAD
. TV . R S
Q . BCD BCD BI
FBD
237
SE
: STL
SE < Timer>
. RLO :
. RLO
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
A
L
SE
A
R
I0.0
S5T#2S
T5
I0.1
T5
A
=
I0.0 T5
I0.0
. Q4.0 .
. I0.1
T5
Q4.0
LAD
. Pulse Timer
FBD
SD
On-Delay Timer
: STL
SD < Timer>
RLO :
( ) t
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
A
L
SD
A
R
A
=
I0.0
S5T#2S
T5
I0.1
T5
T5
Q4.0
I0.0 T5
I0.0
. Q4.0 .
. I0.1
LAD
. Pulse Timer
FBD
239
SS
: STL
SS < Timer>
RLO :
. t
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
A
L
SS
A
R
A
=
I0.0
S5T#2S
T5
I0.1
T5
T5
Q4.0
I0.0 T5
I0.0
.
. I0.1 . Q4.0
LAD
. Pulse Timer
FBD
SF
Off-Delay Timer
: STL
SF < Timer>
t RLO :
( ) . t .
Status Word
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
A
L
SF
A
R
A
=
I0.0
S5T#2S
T5
I0.1
T5
T5
Q4.0
I0.0 T5
Q4.0 .
. I0.1 .
LAD
. Pulse Timer
FBD
241
. FBD LAD
. STL .
---(SP)
Pulse Timer Coil
LAD
RLO :
. Pulse Timer

LAD .
.
I0.1 I0.0
.
. Q4.0
FBD
.. .
LAD
ExtendedPulse Timer
On-Delay Timer

Off-Delay Timer
FBD
Word
(Word Logic Instructions)
Word -
(Boolean Logic) Dword Word
Word .
. Dword Low Word
.
. CC1 Status Word CC0 OV
. CC1=0 0 CC1=1 0
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
x
AW
AND Word (16-bit)
OW
OR Word (16-bit)
XOW
Exclusive OR Word (16-bit)
AD
AND Double Word (32-bit)
OD
OR Double Word (32-bit)
XOD
Exclusive OR Double Word (32-bit)
Word
243
AW
And Word (16-bit)
: STL
AW
:
AW < Constant>
ACCU1-L AND ACCU2-L ACCU1-L AW :
. ACCU2-H ACCU1-H .
AND 16 ACCU1-L AW AW <Constant>
:
L
L
AW
T
IW20
IW22
IW22 IW20
MW8
MW8
:
L
L
AW
T
MW0
W#16#000F
W#16#000F MW0
MW0 MW2
. 5555
MW2
MW0
01010101 01010101
W#16#000F
00000000 00001111
MW2
00000000 00000101
LAD
Q4.0
FBD
Word
OW
Or Word (16-bit)
: STL
OW
:
OW < Constant>
. Or . Or AW :
Bit
15 . . .
..
..
...0
ACCU 1-L before execution of OW
0101
0101
0011
1011
ACCU 2-L or 16 bit constant:
1111
0110
1011
0101
Result (ACCU 1-L) after execution of OW
1111
0111
1011
1111
FBD
XW
LAD
Exclusive Or Word (16-bit)
: STL
XW
:
XW < Constant>
. XOR .XOR :
. 1 0 1
Bit
15 . . .
..
..
...0
ACCU 1 before execution of XOW
0101
0101
0011
1011
ACCU 2-L or 16-bit constant:
1111
0110
1011
0101
Result (ACCU 1) after execution of XOW
1010
0011
1000
1110
FBD
LAD
Word
245
AD
And Double Word (32-bit)
: STL
AD
:
AD < Constant>
ACCU1 AND ACCU2 ACCU1 AD :
.
AND 32 ACCU1 AD AD <Constant>
:
L
L
AD
T
ID20
ID24
ID24 ID20
MD8
MD8
:
L
L
AD
T
MD0
DW#16#FFF
DW#16#00000FFF MD
MD0 MD4
. 55555555
MD4
MD0
0101010101010101
0101010101010101
DW#16#FFF
0000000000000000
0000111111111111
MD4
0000000000000000
0000010101010101
LAD
Q4.0
FBD
Word
OD
Or Double Word (32-bit)
: STL
OD
:
OD < Constant>
. Or . Or AD :
Bit
31 . .
..
ACCU 1 before execution of OD
0101
0000 1111
..
1100 1000 0101
..
..
..
..
ACCU 2 or 32-bit constant:
1111
0011 1000
0101 0111 0110
1011 0101
Result (ACCU 1) after execution of OD
1111
0011 1111
1101 1111 0111
1011 1111
FBD
XD
...0
0011 1011
LAD
Exclusive Or Double Word (32-bit)
: STL
XD
:
XD < Constant>
. XOR .XOR :
. 1 0 1
Bit
31 . .
..
..
..
..
..
..
...0
ACCU 1 before execution of XOD
0101
0000 1111
1100 1000 0101
0011 1011
ACCU 2 or 32-bit constant
1111
0011 1000
0101 0111 0110
1011 0101
Result (ACCU 1) after execution of XOD
1010
0011 0111
1001 1111 0011
1000 1110
FBD
LAD
247
(Accumulator Instructions) -
:
. S7 CPU x
. x
: x
.
31
24
23
16
15
..
ACCU1
ACCU1-H
ACCU1-H-H
ACCU1-L
ACCU1-L-H
ACCU1-L-L
ACCU1-H-L
High Word - High Byte
High Word - Low Byte
Low Word - High Byte
Low Word - Low Byte
. Status Word x
Writes:
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
:
x
TAK
Toggle ACCU 1 with ACCU 2
PUSH
CPU with Two ACCUs
PUSH
CPU with Four ACCUs
POP
CPU with Two ACCUs
POP
CPU with Four ACCUs
ENT
Enter ACCU Stack
LEAVE Leave ACCU Stack
INC
Increment ACCU 1-L-L
DEC
Decrement ACCU 1-L-L
+AR1
Add ACCU 1 to Address Register 1
+AR2
Add ACCU 1 to Address Register 2
BLD
Program Display Instruction (Null)
NOP 0 Null Instruction
NOP 1 Null Instruction
. FBD LAD STL :
TAK
Toggle ACCU1 with ACCU2
: STL
TAK
CPU . TAK :
.
:
L
L
TAK
MW10
MW12
Contents
ACCU 1
ACCU 2
before executing TAK instruction
<MW12>
<MW10>
after executing TAK instruction
<MW10>
<MW12>
NEXT :
L
L
>
JP
TAK
T
MW10
MW12
I
NEXT
I
MW4
. TAK
. MW12 Mw10
MW10- MW10>MW12
Mw10<MW12 MW4 MW12

MW12 TAK
.
POP
: STL
POP
CPU . CPU POP :
: CPU
Contents
before executing POP instruction
after executing POP instruction
ACCU 1
value A
value B
ACCU 2
value B
value B
: CPU
Contents
before executing POP instruction
after executing POP instruction
ACCU 1
value A
value B
ACCU 2
value B
value C
ACCU 3
value C
value D
ACCU 4
value D
value D
:
L
L
T
POP
T
+10
+20
MD0
.
POP MD0
. MD4
MD4
249
PUSH
: STL
PUSH
CPU . CPU PUSH :
: CPU
Contents
before executing PUSH instruction
after executing PUSH instruction
ACCU 1
value A
value A
ACCU 2
value B
value A
: CPU
Contents
before executing PUSH instruction
after executing PUSH instruction
ACCU 1
value A
value A
ACCU 2
value B
value A
ACCU 3
value C
value B
ACCU 4
value D
value C
:
L
PUSH
ENT
MW10
MW10
.
Enter ACCU Stack
ENT
: STL
:
. CPU ENT :
. Load
:
L
L
+
L
ENT
L
/
T
DBD0
DBD4
R
DBD8
DBD12
R
R
DBD16
DBD8 . ACCU1 DBD4 DBD0

. ACCU1 DBD8 ACCU2
. L DBD12
. ENT
DBD8 DBD12
(DBD0+DBD4) /R .
. (DBD8-DBD12)
. DBD16
LEAVE ACCU Stack

LEAVE
: STL
:
. CPU LEAVE :

. .
INC
INC
Increment ACCU-1L-L
: STL
<8 bit integer >
. ACCU-1-L-L INC :
. .
+D +I .
.
:
L
INC
T
DEC
DEC
MB22
. MB22 MB22
MB22
Decrement ACCU-1L-L
: STL
<8 bit integer >
. ACCU-1-L-L DEC :
. .
-D -I .
.
:
L
DEC
T
+AR1
MB22
. MB22 MB22
MB22
Add ACCU1 to Address Register 1
: STL
+AR1
:
+AR1 <P#byte.bit>
. AR1 ACCU-1-L +AR1 :
. +32767 -32768
. AR1 +AR1 <P#byte.bit>
:
L
+AR1
+300
AR1
:
+AR1
P#300.0
. AR1 300.0
251
+AR2
+AR2
+AR2
Add ACCU1 to Address Register2
: STL
:
<P#byte.bit>
. AR2 +AR1 :
:
L
+AR2
+300
+AR2
P#300.0
AR2
:
BLD
BLD
. AR2 300.0

<Number >
: STL
:
STL FBD LAD . PG BLD :
( BLD255 BLD0 )
.
NOP0
Null Instruction
NOP0
: STL
:
(No Operation ) NOP0 :

. Bit Pattern .
NOP1
NOP0
Null Instruction
: STL
:
. Bit Pattern . NOP0 NOP1 :
Z] Zj |q WYY -6
: ] f
( )
( )
-
-
-
-
-
SFB3
-
n -
Address Register
-
-
-
-
-
( )
. MW100 MW100
. 1 0 Q0.0 M101.0 word
L
L
+I
T
A
=
MW100
1
MW100
M101.0
Q0.0
MW100
7
MB100
4
3
MB101
4
3
MB101 MW100
. .
MB101
Scan
Cycle
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10
11
12

( ) -
. CPU
Q0.0 Extended Pulse .
) MW100 .
NOT . Mw100 BEC (
. BEC RLO RLO=0
AN
L
SE
NOT
BEC
L
L
+I
T
A
=
M0.0
S5T#250MS
T1
MW100
1
MW100
M101.0
Q0.0
. F=1/T
1/(250+250) M101.0
. . 2HZ
Bits of MB100
Frequency in Hertz
Duration
M 101.0
2.0
0.5 s
M 101.1
1.0
1s
(0.5 s on / 0.5 s off)
M 101.2
0.5
2s
(1 s on / 1 s off)
M 101.3
0.25
4s
(2 s on / 2 s off)
M 101.4
0.125
8s
(4 s on / 4 s off)
M 101.5
0.0625
16 s
(8 s on / 8 s off)
M 101.6
0.03125
32 s
(16 s on / 16 s off)
M 101.7
0.015625
64 s
(32 s on / 32 s off)
(250 ms on / 250 ms off)
. 1HZ . M101.1
-
. Stop Start
: (NC)
I 0.0
S1
I 0.1
S2
I 1.0
S3
I 1.1
S4
I 2.0
S5
Q 0.0
MOTOR
: STL
O
S1
S3
MOTOR
S2
S4
ON
S5
MOTOR
(NO) PEB2 PEB1

Q4.0 . .
. Q4.1
I 0.0
PEB2
I 0.1
PEB1
Q 4.0
RIGHT
Q 4.1
LEFT
:
NETWORK 1
A
PEB2
FP
AN
M 0.0
PEB1
LEFT
NETWORK 2
A
PEB1
FP
AN
S
M0.1
PEB2
RIGHT
NETWORK 3
AN
PEB2
AN
PEB1
RIGHT
LEFT
-
.
.
. Q0.0
M1
M2
:
O(
A
MOT1
AN
MOT2
)
O(
AN
MOT1
MOT2
)
Q0.0
MOT1
MOT2
: Exclusive OR :
X
MOT1
MOT2
Q0.0
MOT1
MOT2
: FBD
-
. Start
. (Thumbwheel)
: .
. 9 0 BCD
: IW0
I1.3
I1.0
I1.7
I1.4
I0.3
I0.0
. .
A
T1
=
Q4.0
BEC

. BEC
I 0.7
.
IW0
AW
W#16#0FFF

1
.AND
OW
W#16#2000

OR 2000 10"
A
SE
I 0.7
T1
. BCD
Extended Pulse T1

-
:
.
O
O
O
O
O
S
L
SD
R
I 0.0
I 0.1
I 0.2
I 0.3
I 0.4
Q 0.0
S5T#30S
T1
Q0.0
SFB3 -
TP SFB3
Q IN . Q PT IN
. (Expired Time) ET
. SFB3 OB1
CALL SFB3,DB3
IN: I 0.0
PT : T#6S
Q : Q0.0
ET : MD0
. 1 0

n -
. MW20 IW0 LOOP
TEST:
L
T
L
T
L
*
T
L
LOOP
1
MW20
IW0
MW0
MW20
I
MW20
MW0
TEST
Address Register -
: AR1 QW0 IW0

L
IW0
IW0
0 IW0
LAR1
AR1 0
TAK
IW0
QW [AR1,P#0.0]
AR1 QW
QW0
P#2.0
QW2 2 AR1
IW0 AR1
. QW20 QW0
L
T
ABC: L
L
<=
JCN
L
L
LAR1
TAK
T
L
L
+
T
JU
END: NOP
0
MW0
MW0
160
I
END
IW0
MW0
QW [AR1,P#0.0]
MW0
16
I
MW0
ABC
0
-
. .
. . I 12.0
. .
:
. (QW2 ) BCD
.
. (Q0.1) x
. (Q0.0) x
A
CU
A
CD
LC
T
L
>=
=
LC
L
<
=
I 12.0
C1
I 12.1
C1
C1
QW2
C#90
I
Q 0.1
C1
C#100
I
Q0.0
. Start
:
NETWORK 1
A(
O
O
)
=
Conveyor1
NETWORK 2
A
L
SP
AN
A
=
Conveyor1
S5T#10S
T1
T1
Conveyor1
Conveyor2
Start
Conveyor1
. 0 I0.0 1
. FBD
: Q0.0
: Q0.1
: Q0.2
( ) : Q0.1
Simatic Manager File> Open STEP7

. Sample Projects
. ZEn01_08_STEP7_Mix
.
.
.
.
.
.
.
FB
DB .
FC
OB .
-
. B A
. .
-
:
: B A
(Inlet Valve) x
(Feed Pump) x
(Feed Valve) x
(Flow Sensor)
:
(Drain Valve)
:
x
x
x
x
-
:
. x
. x
. x
)
x
(
. x
. x
. x
:
. x
. x
. x
. x
:
. x
. Tank Empty x
. x
-
:
Stop / Start
Stop x
x
x
-
:
. FB ... Count Off On x
. FB1 Instance DB3 DB2 DB1 x
.
. FC Close Open x
-
: Symbol Table
Symbole
Agitator
Agitator_fault
Agitator_maint
Agitator_off
Agitator_on
Agitator_running
Agitator_start
Agitator_stop
DB_agitator
DB_feed_pump_A
DB_feed_pump_B
Drain
Drain_closed
Drain_closed_disp
Drain_open
Drain_open_disp
EMER_STOP_off
Feed_pump_A
Feed_pump_A_fault
Feed_pump_A_maint
Feed_pump_A_off
Feed_pump_A_on
Feed_pump_A_start
Feed_pump_A_stop
Feed_pump_B
Feed_pump_B_fault
Feed_pump_B_maint
Feed_pump_B_off
Feed_pump_B_on
Feed_pump_B_start
Feed_pump_B_stop
Feed_valve_A
Feed_valve_B
Flow_A
Flow_B
Inlet_valve_A
Inlet_valve_B
Motor_block
Reset_maint
Tank_above_min
Tank_below_max
Tank_empty_disp
Tank_max_disp
Tank_min_disp
Tank_not_empty
Valve_block
Address Data
Type
Q 8.0 BOOL
Q 8.3 BOOL
Q 8.4 BOOL
Q 8.2 BOOL
Q 8.1 BOOL
I 1.0 BOOL
I 1.1 BOOL
I 1.2 BOOL
DB 3
FB 1
DB 1
FB 1
DB 2
FB 1
Q 9.5 BOOL
I 0.7 BOOL
Q 9.7 BOOL
I 0.6 BOOL
Q 9.6 BOOL
I 1.6 BOOL
Q 4.4 BOOL
Q 4.5 BOOL
Q 4.6 BOOL
Q 4.3 BOOL
Q 4.2 BOOL
I 0.0 BOOL
I 0.1 BOOL
Q 5.4 BOOL
Q 5.5 BOOL
Q 5.6 BOOL
Q 5.3 BOOL
Q 5.2 BOOL
I 0.3 BOOL
I 0.4 BOOL
Q 4.1 BOOL
Q 5.1 BOOL
I 0.2 BOOL
I 0.5 BOOL
Q 4.0 BOOL
Q 5.0 BOOL
FB 1
FB 1
I 1.7 BOOL
I 1.4 BOOL
I 1.3 BOOL
Q 9.2 BOOL
Q 9.0 BOOL
Q 9.1 BOOL
I 1.5 BOOL
FC 1
FC 1
Comment
Activates the agitator
Display lamp for "Agitator motor fault"
Display lamp for "Agitator motor maintenance"
Display lamp for "Agitator OFF"
Display lamp for "Agitator ON"
Feedback signal from the agitator motor
Start pushbutton agitator
Stop pushbutton agitator
Instance DB for controlling agitator motor
Instance DB for controlling feed pump A
Instance DB for controlling feed pump B
Activates the drain valve
Pushbutton for closing drain valve
Display lamp for "Drain valve closed"
Pushbutton for opening drain valve
Display lamp for "Drain valve open"
EMERGENCY STOP switch
Activates the feed pump for ingredient A
Display lamp for "Feed pump A fault"
Display lamp for "Feed pump A maintenance"
Display lamp for "Feed pump OFF ingredient A"
Display lamp for "Feed pump ON ingredient A"
Start pushbutton feed pump for ingredient A
Stop pushbutton feed pump for ingredient A
Activates the feed pump for ingredient B
Display lamp for "Feed pump B fault"
Display lamp for "Feed pump B maintenance"
Display lamp for "Feed pump OFF ingredient B"
Display lamp for "Feed pump ON ingredient B"
Start pushbutton feed pump for ingredient B
Stop pushbutton feed pump for ingredient B
Activates the feed valve for ingredient A
Activates the feed valve for ingredient B
Ingredient A flows
Ingredient B flows
Activates the inlet valve for ingredient A
Activates the inlet valve for ingredient B
FB for controlling pumps and agitator motor
Reset pushbutton for maintenance display (all
Sensor "Mixing tank above minimum level"
Sensor "Mixing tank not full"
Display lamp for "Mixing tank empty"
Display lamp for "Mixing tank full"
Display lamp for "Mixing tank below minimum l
Sensor "Mixing tank not empty"
FC for controlling valves
( FB ) Function Block -
FB1 . OB FB
. LAD/STL/FBD
FB
.
: .
(Start)
(Stop)
(Response)
(Response_Time) .
.
(Timer_NO)
(Fault)
(Timer_BCD)
(Start_Dsp)
(Stop_Dsp)
(Starts)
(Maint)
(Reset_Maint)
. LAD FB1 OB1
(STAT) (out) (in) . FB

. FB LStack (Temp)
STL Code Section

: ( )LAD
STL
LAD
AND
OR .
. Start
Network 1 Start/stop and latching

A(
O #Start
O #Motor
)
AN #Stop
= #Motor

.
.
Network 2 Startup monitoring
A #Motor
L #Response_Time
SD #Timer_No
AN #Motor
R #Timer_No
L #Timer_No
T #Timer_bin
LC #Timer_No
T #Timer_BCD
A #Timer_No
AN #Response
S #Fault
R #Motor
Network 3 Start lamp and fault

reset
A #Response
= #Start_Dsp
R #Fault
Network 4 Stop lamp

AN #Response
= #Stop_Dsp
Network 5 Counting the starts
A #Motor
FP #Start_Edge
JCN lab1
L #Starts
+1
T #Starts
lab1: NOP 0

Network 6 Maintenance lamp

L #Starts
L 50
>=I
= #Maint
Network 7 Reset counter for

number of starts
A #Reset_Maint
A #Maint
JCN END
L0
T #Starts
END: NOP 0
DB -
. DB1 ,DB2 , DB3 DB
FB DB . Instance FB1
.
FC -
. OB1 OB1 FC1 FB1

. LAD/STL/FBD FC1
Close Open FC1
. (Latching) Valve
. OB1 FC1
OB1 FC1
OB1 . FC OB1
. ( ) ( ) FC
: FC
. LAD FC1
Network 1 : Open/Close and Latching
Network 2 : Display "Valve open"
Network 3 : Display "Valve Closed"
OB1 -
: OB1
. OB1
OB1 .
. Enable_motor .
LAD/STL/FBD . STL
. View > Display With

# .
.
STL Program Without Symbolic Name

A I
1.6
A I
1.3
AN Q
9.5
= #Enable_Motor
A I
0.0
A #Enable_Motor
= #Start_Fulfilled
A(
O I
0.1
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL FB 1 , DB1
Start
:=#Start_Fulfilled
Stop
:=#Stop_Fulfilled
Response :=I0.2
Reset_Maint :=I1.7
Timer_No :=T12
Response_Time:=S5T#7S
Fault
:=Q4.5
Start_Dsp :=Q4.2
Stop_Dsp :=Q4.3
Maint
:=Q4.6
Motor
:=Q4.4
A
L
SD
AN
R
A
=
Q
4.4
S5T#1S
T 13
Q
4.4
T 13
T 13
#Enable_Valve
AN I
0.2
AN Q
4.4
= #Close_Valve_Fulfilled
CALL FC 1
Open
:=#Enable_Valve
Close :=#Close_Valve_Fulfilled
Dsp_Open :=#Feed_Valve_A_Open
Dsp_Closed:=#Feed_Valve_A_Closed
Valve :=Q4.1
AN I
0.2
AN Q
4.4
CALL FC 1
Open
:=#Enable_Valve
Valve :=Q4.1
STL Program With Symbolic Name

Network 1 Interlocks for feed pump A
A "EMER_STOP_off"
A "Tank_below_max"
AN "Drain"
= #Enable_Motor
Network 2 Calling FB Motor for ingredient A

A "Feed_pump_A_start"
A #Enable_Motor
= #Start_Fulfilled
A(
O "Feed_pump_A_stop"
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL "Motor_block", "DB_feed_pump_A"
Start :=#Start_Fulfilled
Stop :=#Stop_Fullfilled
Response :="Flow_A"
Reset_Maint :="Reset_maint"
Timer_No :=T12
Reponse_Time:=S5T#7S
Fault :="Feed_pump_A_fault"
Start_Dsp :="Feed_pump_A_on"
Stop_Dsp :="Feed_pump_A_off"
Maint :="Feed_pump_A_maint"
Motor :="Feed_pump_A"
Network 3 Delaying the valve enable

ingredient A
A "Feed_pump_A"
L S5T#1S
SD T 13
AN "Feed_pump_A"
R T 13
A T 13
= #Enable_Valve
Network 4 Inlet valve control for ingredient A

AN "Flow_A"
AN "Feed_pump_A"
CALL "Valve_block"
Open :=#Enable_Valve
Dsp_Open :=#Inlet_Valve_A_Open
Dsp_Closed:=#Inlet_Valve_A_Closed
Valve :="Inlet_Valve_A"
Network 5 Feed valve control for ingredient A
AN "Flow_A"
AN "Feed_pump_A"
CALL "Valve_block"
Valve :="Feed_Valve_A"

Network 6 Interlocks for feed pump B
A I
1.6
A I
1.3
AN Q
9.5
= #Enable_Motor
A "EMER_STOP_off"
A "Tank_below_max"
AN "Drain"
= "Enable_Motor
A I
0.3
A #Enable_Motor
= #Start_Fulfilled
A(
O I
0.4
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL FB 1 , DB2
Start
:=#Start_Fulfilled
Stop
:=#Stop_Fulfilled
Response :=I0.5
Reset_Maint :=I1.7
Timer_No :=T14
Fault
:=Q5.5
Start_Dsp :=Q5.2
Stop_Dsp :=Q5.3
Maint
:=Q5.6
Motor
:=Q5.4
Network 7 Calling FB Motor for ingredient B

A "Feed_pump_B_start"
A #Enable_Motor
= #Start_Fulfilled
A(
O "Feed_pump_B_stop"
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL "Motor_block", "DB_feed_pump_B"
Response :="Flow_B"
Timer_No :=T14
Fault :="Feed_pump_B_fault"
Start_Dsp :="Feed_pump_B_on"
Stop_Dsp :="Feed_pump_B_off"
Maint :="Feed_pump_B_maint"
Motor :="Feed_pump_B"
Network 8 Delaying the valve enable

ingredient B
A Q
5.4
L S5T#1S
SD T 15
AN Q
5.4
R T 15
A T 15
= #Enable_Valve
A "Feed_pump_B"
L S5T#1S
SD T 15
AN "Feed_pump_B"
R T 15
A T 15
= #Enable_Valve
Network 9 Inlet valve control for ingredient B
AN I
0.5
AN Q
5.4
CALL FC 1
Open
:=#Enable_Valve
Dsp_Open :=#Inlet_Valve_B_Open
Dsp_Closed:=#Inlet_Valve_B_Closed
Valve :=Q5.0
AN "Flow_B"
AN "Feed_pump_B"
CALL "Valve_block"
Dsp_Open :=#Inlet_Valve_B_Open
Dsp_Closed:=#Inlet_Valve_B_Closed
Valve :="Inlet_Valve_B"
AN I
0.5
AN Q
5.4
CALL FC 1
Open
:=#Enable_Valve
Dsp_Open :=#Feed_Valve_B_Open
Dsp_Closed:=#Feed_Valve_B_Closed
Valve :=Q5.1
Network 10 Feed valve control for ingredient B

AN "Flow_B"
AN "Feed_pump_B"
CALL "Valve_block"
Dsp_Open :=#Feed_Valve_B_Open
Dsp_Closed:=#Feed_Valve_B_Closed
Valve :="Feed_Valve_B"
A I
1.6
A I
1.4
AN Q
9.5
= #Enable_Motor
Network 11 Interlocks for agitator

A "EMER_STOP_off"
A "Tank_above_min"
AN "Drain"
= #Enable_Motor
A I
1.1
A #Enable_Motor
= #Start_Fulfilled
A(
O I
1.2
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL FB 1 , DB3
Start
:=#Start_Fulfilled
Stop
:=#Stop_Fulfilled
Response :=I1.0
Reset_Maint :=I1.7
Timer_No :=T16
Fault
:=Q8.3
Start_Dsp :=Q8.1
Stop_Dsp :=Q8.2
Maint
:=Q8.4
Motor
:=Q8.0
Network 12 Calling FB Motor for agitator

A "Agitator_start"
A #Enable_Motor
= #Start_Fulfilled
A(
O "Agitator_stop"
ON #Enable_Motor
)
= #Stop_Fulfilled
CALL "Motor_block", "DB_Agitator"
Response :="Agitator_running"
Timer_No :=T16
Fault :="Agitator_fault"
Start_Dsp :="Agitator_on"
Stop_Dsp :="Agitator_off"
Maint :="Agitator_maint"
Motor :="Agitator"
A I
1.6
A I
1.5
AN Q
8.0
= #Enable_Valve
Network 13 Interlocks for drain valve

A "EMER_STOP_off"
A "Tank_not_empty"
AN "Agitator"
= "Enable_Valve
A I
0.6
A #Enable_Valve
= #Open_Drain
A(
O I
0.7
ON #Enable_Valve
)
= #Close_Drain
CALL FC 1
Open
:=#Open_Drain
Close :=#Close_Drain
Dsp_Open :=Q9.6
Dsp_Closed:=Q9.7
Valve :=Q9.5
Network 14 Drain valve control

A "Drain_open"
A #Enable_Valve
= #Open_Drain
A(
O "Drain_closed"
ON #Enable_Valve
)
= #Close_Drain
CALL "Valve_block"
Open :=#Open_Drain
Close :=#Close_Drain
Dsp_Open :="Drain_open_disp"
Dsp_Closed :="Drain_closed_disp"
Valve :="Drain"
AN
=
AN
=
AN
=
Network 15 Tank level display

AN "Tank_below_max"
= "Tank_max_disp"
AN "Tank_above_min"
= "Tank_min_disp"
AN "Tank_not_empty"
= "Tank_empty_disp"
I
Q
I
Q
I
Q
1.3
9.0
1.4
9.1
1.5
9.2
2.% Z] 1P.KPG Z^eY -7

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1
IEC1131
IEC1131
IEC 61131-1 General Information

TABLE OF CONTENT - IEC 61131-1
(incl. page number)
FOREWORD
INTRODUCTION
1
2
3
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
Scope
Normative references
Definitions
Functional characteristics
Basic functional structure of a programmable controller system
Characteristics of the CPU function
Characteristics of the interface function to sensors and actuators
Characteristics of the communication function
Characteristics of the human-machine interface (HMI) function
Characteristics of the programming, debugging, monitoring, testing and
documentation functions
Characteristics of the power supply functions
Availability and reliability
IEC 61131-2 - Equipment Requirements and Tests

Table of Content IEC 61131-2
(incl. page numbers)
1
1.1
1.2
1.3
1.4
1.5
1.6
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
General
Scope
Object of the Standard
Object of This Part
Compliance With This Standard
Type Tests
Normative References
Definitions
Analog Input
Analog Output
Accessible
Basic PLC (-system)
Battery
Clearance
Coating, Protective
Comparative Tracking index (CTI)
Creepage Distance
Current Sinking
Current Sourcing
Digital Input, Type 1
Digital Output
Earth

2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
2.33
2.34
2.35
2.36
2.37
2.38
2.39
2.40
2.41
2.42
2.43
2.44
2.45
2.46
2.47
2.48
2.49
2.50
2.51
2.52
2.53
2.54
2.55
2.56
2.57
2.58
2.59
3
3.1
3.2
3.3
3.4
3.5
4
4.1
4.2
4.3
4.4
4.5
4.6
IEC1131
EMC (electromagnetic compatibility)

Enclosed Equipment
Enclosure
Equipment class
Equipment Under Test (EUT)
External Wiring
Field wiring
Functional Earthing Conductor
Hand-Held Equipment
Hazardous Live
Immunity (to a disturbance)
Immunity Type Test (immunity test)
Insulation
Interface
Internal Wiring
Isolated (devices, circuits)
Live Part
Mains Power Supply
Material Group
Micro-Environment:
Module
Multi-Channel Module
Normal Use
Normal Condition
Open Equipment
Operator
Overvoltage Category (of a circuit or within an electrical system)
Permanent Installation
Pollution Degree (in the micro-environment)
Port
Portable Equipment
Protective Conductor
Protective Extra-Low Voltage (PELV) Circuit
Protective Impedance
Recurring Peak Voltage
Routine Test
Safety Extra-Low Voltage Circuit (SELV circuit)
Service Personnel
Total Output Current (of an output module)
Type Test
Unit
Withstand Type Test (withstand test)
Working Voltage
Normal Service Conditions and Requirements
Climatic Conditions and Requirements
Mechanical Service Conditions and Requirements
Transport and Storage Conditions and Requirments
Electrical Service Conditions and Requirements
Special Conditions and Requirements
Functional Requirements
Functional Power Supply and Memory Back-up Requirements
Digital I/Os
Analog I/Os
Communication Interface Requirements
Main Processing Unit(s) and Memory(ies) of the PLC-system Requirements
Remote Input/Output Stations (RIOSs) Requirements
IEC1131
4.7
4.8
4.9
4.10
4.11
4.12
4.13
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
7
7.1
7.2
7.3
7.4
7.5
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
9
Peripherals (PADTs, TEs, HMIs) Requirements

PLC-system Self-Tests and Diagnostics Requirements
Functional Earthing
Mounting Requirments
General Marking Requirements
Requirements for Normal Service and Functional Type Tests and Verifications
Requirements for Information on Normal Service and Function
Normal Service and Functional Type Tests and Verifications
Climatic Tests
Mechanical Tests
Verification of Special Functional Requirements for Power Ports and Memory Back-up
-- Special Immunity Limits for Power Ports
Verification of Input/Output Requirements
Verification of Communication Interface Requirements
Verification of MPU Requirements
Verification of Remote I/O Stations
Verification of Peripheral (PADTs, TEs, HMIs) Requirements
Verification of PLC-system Self-Tests and Diagnostics
Verification of Markings and Manufacturer's Documentation
General Information to be Provided by Manufacturer
Information on Type and Content of Documentation
Information on Compliance With This Standard
Information on Reliability
Information on Other Conditions
Information on Shipping and Storage
Information on AC and DC Power Supply
Information on Digital Inputs (current sinking)
Information on Digital Outputs for Alternating Currents (current sourcing)
Information on Digital Outputs for Direct Current (current sourcing)
Information on Analog Inputs
Information on Analog Outputs
Information on Communication Interfaces
Information on Main Processing Unit(s) and Memory(ies) of the PLC-system
Information on Remote Input/Output Stations (RIOSs)
Information on Peripherals (PADTs, TEs, HMIs)
Information on Self-Tests and Diagnostics
Electromagnetic Compatibility (EMC) Requirements
General
Emission Requirements
EMC Immunity Requirements
Requirements for EMC Tests and Verifications
Requirements for Information on EMC
Electromagnetic Compatibility (EMC) Type Tests and Verifications
Electromagnetic Compatibility Related Tests
Test Environment
Measurement of Radiated Interference
Measurement of Conducted Interference
Electrostatic Discharge
Radio Frequency Electromagnetic Field - Amplitude Modulated
Power Frequency Magnetic Fields
Fast Transient Bursts
High Energy Surges
Conducted Radio Frequency Interference
Damped Oscillatory Wave (for Zone C only)
Voltage Drops and Interruptions Power Ports Type Tests and Verifications
Electromagnetic Compatibility (EMC) Information to be Provided by Manufacturer
IEC1131
10
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
11
11.1
11.2
11.3
12
12.1
12.2
12.3
13
13.1
13.2
Annex
Annex
Annex
C.1
C.2
Annex
Annex
Annex
A
B
C
D
E
F
Safety Requirements
Protection Against Electrical Shock
Protection Against the Spread of Fire
Limited Power Circuits
Clearance and Creepage Distances Requirements
Flame Retardant Requirements for Non-Metallic Materials
Temperature Limits
Enclosures
Field Wiring Terminals Constructional Requirements
Provisions for Protective Earthing
Wiring
Switching Devices
Components
Battery Requirements
Maximum Voltage and Minimum Voltage
Markings and Identification
Requirements for Safety Type Tests and Verifications
Requirements for Safety Routine Tests and Verifications
Requirements for Information on Safety
Safety Type Tests and Verifications
Safety Related Mechanical Tests and Verifications
Safety Related Electrical Tests
Single Fault Condition Test General
Safety Routine Tests
Dielectric Withstand Test
Dielectric Withstand Verification Test
Protective Earthing Test
Safety Information to be Provided by the Manufacturer
Information on Evaluation of Enclosures for Open Equipment (power dissipation)
Information on Mechanical Terminal Connection
(Informative) Illustration of PLC-system Hardware Definitions
(Informative) Digital Input Standard Operating Range Equations
(Normative) Test Tools
Jointed Test Finger
Test Pins
(Informative) Zone C EMC Immunity Levels
(Informative) Overvoltage Example
(Informative) Bibliography
IEC 61131-3 Programming Languages

TABLE OF CONTENT IEC 61131-3
1.
1.1
1.2
1.3
1.4
1.5
2.
2.1
General
Scope
Definitions
Overview and general requirements
Compliance
Common elements
Use of printed characters
IEC1131
2.2
2.3
2.4
2.5
2.6
2.7
3.
3.1
3.2
3.3
4.
4.1
4.2
4.3
ANNEX
A.1
A.2
ANNEX
B.0
B.1
B.2
B.3
ANNEX
ANNEX
ANNEX
ANNEX
F.1
F.2
F.3
F.4
F.5
F.6
F.7
F.8
F.9
F.10
F.11
ANNEX
ANNEX
External representation of data

Data types
Variables
Program organization units
Sequential Function Chart (SFC) elements
Configuration elements
Textual languages
Common elements
Instruction list (IL)
Structured Text (ST)
Graphic languages
Common elements
Ladder Diagram (LD)
Function Block Diagram (FBD)
Specification method for textual languages (normative)
Syntax
Semantics
Formal specifications of language elements (normative)
Programming model
Common elements
Language IL (Instruction List)
Language ST (Structured Text)
Delimiters and Keywords (normative)
Implementation-dependent parameters (normative)
Error Conditions (normative)
Examples (informative)
Function WEIGH
Function block CMD_MONITOR
Function block FWD_REV_MON
Function block STACK_INT
Function block MIX_2_BRIX
Analog signal processing
Program GRAVEL
Program AGV
Use of enumerated data types
Function block RTC (Real Time Clock)
Function block ALRM_INT
Index (informative)
Reference character set (informative)
C
D
E
F
G
H
IEC 61131- 4
User Guidelines
1
1.1
1.2
1.3
2
2.1
2.2
General
Scope
References
Use of this report
Definitions
Application program (user program)
Automated system

2.3
2.4
2.5
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5
5.1
5.2
5.3
5.4
5.5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7.
7.1
7.2
7.3
7.4
7.5
8
8.1
8.2
8.3
8.4
9
9.1
9.2
9.3
9.4
Annex A
A.1
A.2
A.3
A.4
A.5
A.6
IEC1131
PLC-system
Programmable controller (PLC)
Programmable controller system (PLC-system)
Key elements of IEC 61131-1, Part 1: General information
PLC hardware model
Basic functional structure of a PLC system
CPU function
Programming languages
Availability and reliability
Re-start of PLC operating system
Documents supplied to the user
Key elements of IEC 61131-2: Part 2 - Equipment requirements and testing
Scope of Part 2
Definitions
Functional requirements
Electromagnetic compatibility (EMC) requirements
Safety requirements for PLC equipment
Information to be provided by the manufacturer
Compliance with IEC 61131-2 standard
Key elements of IEC61131-3: Part 3 - Programming Languages
Technical contents of Part 3
Common Elements
Programming languages
Applications program development
Implementation
Key Elements of IEC61131-5, Part 5 - Communication
Scope of Part 5
Technical contents of IEC61131-5 and the PLC model
Communication Model
PLC communication services
Application functions
Communication function blocks
Compliance
Key elements of IEC61131-7, Part 7 - Fuzzy Logic programming
General outline of Part 7
Integration of fuzzy control application into the programmable controllers
Fuzzy Control Language (FCL)
Exchange of fuzzy control programs
Compliance
General rules for installation
Environmental conditions
Field wiring
Electromagnetic compatibility
User system markings
PLC in Functional safety applications
Using a PLC in a safety-related application
Safety-related system Safety requirements
PLC requirements in a safety-related system
Integration of PLC into safety-related system
User checklists
Equipment data
General information checklist
Equipment requirements checklist
Checklist on programming languages
Checklist on communication
Checklist on Fuzzy control language
IEC1131
A.7
A.8
Annex
C1
C2
C2.1
C2.2
C2.3
C2.4
C3
C3.1
C3.2
C3.3
C4
C5
C5.1
C5.2
C5.3
Annex
Annex
Annex
Annex
Annex
C
D
E
F
G
Checklist on installation
Checklist on safety-related application
Comparism of EN and IEC61131
Advance Planning
Variable Naming Conventions / Methodologies
Naming Methodologies
Use of Upper & Lower Case
Consistent Project Prefixes, Suffixes and Acronyms
Sequential Function Chart (SFC) step naming
Structure / Organization
Program Structure by area / process flow
Structured Variables (Data Types) for multiple devices
Data Arrays for data storage & Manipulation
Use of the Appropriate Language
DFB requirements
Device Control
Frequently used Functions
Special Functions
Example of PLC software implementation
Example of PLC communications implementation
Example of PLC fuzzy control language implementation
Example of a PLC system in safety-related application
Reference standards
IEC 61131-5 Messaging service specification (Communication)

1
2
3
4
5
5.1
5.2
5.3
5.4
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.2
Scope
Definitions
Symbols and abbreviations
Models
PC Network communication model
PC functional model
PC hardware model
Software model
PC communication services
PC subsystems and their status
Application specific functions
PC communication function blocks
Overview of the communication function blocks
Semantic of communication FB parameters
Device verification
Polled data acquisition
Programmed data acquisition
Parametric control
Interlocked control
Programmed alarm report
Connection management
Example for the use of communication function blocks
Compliance and implementer specific features and parameters
Compliance
Implementation specific features and parameters
IEC1131
Annex A
A.1
A.2
A.3
A.4
A.5
(normative) Mapping to ISO/IEC 9506-5

Application specific functions
PC object mapping
Communication function block mapping to MMS objects and services
Annex B
B.1
B.2
(normative) PC behavior using ISO/IEC 9506-2

PC communications mapping to MMS
Annex C
Index
(informative)
IEC 61131-6 reserve for future use
IEC 61131-7 Fuzzy Control Programming

Detail not available
IEC 61131-8 Guidelines for the application and implementation of

programming languages
1.
1.1
1.2
1.3
2.
2.1
2.2
2.3
2.4
2.5
3.
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
General
Scope
Overview
Introduction to IEC 61131-3
General considerations
Overcoming historical limitations
Basic features in IEC 61131-3
New features in the second edition of IEC 61131-3
Software engineering considerations
Application guidelines
Use of data types
Data passing
Use of function blocks
Differences between function block instances and functions
Use of indirectly referenced function block instances
Recursion within programmable controller programming languages
Single and multiple invocation
Language specific features
Use of SFC elements
Scheduling, concurrency, and synchronization mechanisms
Communication facilities in ISO/IEC 9506/5 and IEC 61131-5
IEC1131
3.12
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.8.1
5.8.2
5.8.3
5.8.4
5.9
5.10
5.11
Annex A
A.1
A.2
A .3
A.3.1
A.3.2
A.3.3
A.3.4
A.3.5
A.3.6
A.3.7
A.3.8
A.3.9
A.3.10
A.3.11
A.3.12
A.3.13
A.3.14
A.3.15
A.3.16
A.3.17
ANNEX B
ANNEX C
Recommended programming practices

Implementation guidelines
Resource allocation
Implementation of data types
Execution of functions and function blocks
Implementation of Sequential Function Charts (SFCs)
Task scheduling
Error handling
System interface
Compliance
Compatibility with IEC 617-12, 617-13, and 848
Programming support environment (PSE) requirements
User interface
Programming of programs, functions and function blocks
Application design and configuration
Separate compilation
Separation of interface and body
Linking of configuration elements with programs
Library management
Analysis tools
Simulation and debugging
Performance estimation
Feedback loop analysis
SFC analysis
Documentation requirements
Security of data and programs
On-line facilities
Changes to IEC 61131-3 2nd Edition
Reasons for the 2nd edition of part 3
Corrigendum
Amendment
Numeric literals (2.2.1) typed literals
Elementary data types (2.3.1) - double-byte strings
Derived data types (2.3.3) - enumerated data types
Single element variables (2.4.1.1) - 'wild-card' direct addresses
Declaration (2.4.3) - Temporary variables
Type assignment (2.4.3.1) - RETAIN and NON_RETAIN Variable attributes
Function ( 2.5.1) Use EN/ENO
Declaration (2.5.1.3) - Function invocation with VAR_IN_OUT
Type conversion functions (2.5.1.5.1)
Functions of time data types (2.5.1.5.6)
Function blocks (2.5.2) - Extended initialisation facilities
Pulse action qualifiers (2.6.4.4)
Action control (2.6.4.5)
Configuration initialisation (2.7.1)
Instruction List (3.2)
Formal specification of language elements (Annex B)
Further amendments
SOFTWARE QUALITY MEASURES
INDEX
2
ZM Z my { {Z{Z
Digitized for Analog Input and Output Values
Resolution
. Resolution
Resolution in Bits (+ Sign)
Units
Analog Value
Low-Order Byte
1xxxxxxx
Decimal
128
Hex
80
High-Order Byte
VZ 0 0 0 0 0 0 0
64
40
VZ 0 0 0 0 0 0 0
01xxxxxx
10
32
20
VZ 0 0 0 0 0 0 0
001xxxxx
11
16
10
VZ 0 0 0 0 0 0 0
0001xxxx
12
VZ 0 0 0 0 0 0 0
00001xxx
13
VZ 0 0 0 0 0 0 0
000001xx
14
VZ 0 0 0 0 0 0 0
0000001x
15
VZ 0 0 0 0 0 0 0
00000001
. X ( 1 0 ) VZ
:
. Resolution x
Resolution x
.
Resolution x
. .
.
-

Voltage Ranges
Measuring
Range
80 mV
> 94.071
94.071
:
80.003
80.000
60.000
:
Measuring Measuring Measuring Measuring

Units
Range
Range
Range
Range
250 mV
500 mV
1 V
2.5 V
Decimal Hex
7FFF
> 293.97
> 587.94
> 1.175
> 2.9397
32767
H
7EFF
293.97
587.94
1.175
2.9397
32511
H
:
:
:
:
:
:
6C01
250.01
500.02
1.00004
2.5001
27649
H
6C00
250.00
500.00
1.000
2.500
27648
H
5100
187.50
375.00
0.750
1.875
20736
H
:
:
:
:
:
:
60.000
80.000
80.003
:
94.74
94.074
187.50
250.00
250.01
:
293.98
293.98
375.00
500.00
500.02
:
587.96
587.96
0.750
1.000
1.00004
:
1.175
1.175
1.875
2.500
2.5001
:
2.93398
2.93398
20736
27648
27649
:
32512
32768
Range
Overflow
Overrange
Nominal
range
AF00
9400
H
H
H
93FF
Underrange
H
8000
H
Underflow
8100

Voltage and Current Measuring Ranges
Measuring
Range
5V
> 5.8794
5.8794
:
5.0002
5.00
3.75
:
Measuring
Range
10 V 10 mA
> 11.7589
11.7589
:
10.0004
10.00
7.50
:
Measuring
Range
3.2 mA
> 3.7628
3.7628
:
3.2001
3.200
2.400
:
Measuring
Range
20 mA
> 23.515
23.515
:
20.0007
20.000
14.998
:
32767
32511
:
27649
27648
20736
:
7FFFH
3.75
5.00
5.0002
:
5.8796
5.8796
7.50
10.00
10.0004
:
11.759
11.759
2.400
3.200
3.2001
:
3.7629
3.7629
14.998
20.000
20.0007
:
23.516
23.516
20736
27648
27649
:
32512
32768
AF00H
Units
Decimal
Range
Hex
7EFFH
:
6C01H
Overflow
Overrange
6C00H
5100H
:
Nominal range
9400H
93FFH
:
8100H
8000H
Underrange
Underflow
Voltage and Current Measuring Ranges

Measuring
Range
1 to 5 V
> 5.7036
5.7036
:
5.0001
5.000
4.000
Measuring
Range
0 20 mA
> 23.515
23.515
:
20.0007
20.000
14.998
Measuring
Range
4 to 20 mA
> 22.810
22.810
:
20.0005
20.000
16.000
Decimal
32767
32511
:
27649
27648
20736
1.000
0.9999
:
0.2963
< 0.2963
0.000
-0.0007
:
3.5185
3.5185
4.000
3.9995
:
1.1852
< 1.1852
0
1
:
4864
32768
0H
Units
Hex
7FFFH
7EFFH
:
6C01H
Range
Overflow
Overrange
6C00H
5100H
Nominal range
FFFFH
:
ED00H
8000H
Underrange
Underflow

Resistance-Type Sensors
Measuring
Range
150 :
> 176.383
176.383
:
150.005
150.000
112.500
Measuring
Range
300 :
> 352.767
352.767
:
300.011
300.000
225.000
Measuring
Range
600 :
> 705.534
705.534
:
600.022
600.000
450.000
32767
32511
:
27649
27648
20736
7FFFH
0
1
:
4864
32768
0H
0.000
0.000
0.000
(negative values physically not possible)
Units
Range
Decimal
Hex
Overflow
7EFFH
:
Overrange
6C01H
6C00H
5100H
Nominal range
FFFFH
:
Underrange
ED00H
8000H
Underflow
Standard Temperature Range, Pt 100

Standard
Temperature
Range Pt 100
850 C
> 1000.0
1000.0
:
850.1
850.0
:
200.0
200.1
:
243.0
243.0
Units
Decimal
32767
10000
:
8501
8500
:
2000
2001
:
2430
32768
Range
Hex
7FFFH
Overflow
2710H
:
Overrange
2135H
2134H
:
Nominal range
F830H
F82FH
:
Underrange
F682H
8000H
Underflow
Climate Temperature Range, Pt 100

Standard
Temperature
Range Pt 100
130 C
> 155.00
155.00
:
130.01
130.00
:
120.00
120.01
:
145.00
145.00
Units
Decimal
Hex
32767
15500
:
13001
13000
:
12000
12001
:
14500
32768
7FFFH
3C8CH
:
32C9H
Range
Overflow
Overrange
32C8H
:
D120H
Nominal range
D11FH
:
C75CH
8000H
Underrange
Underflow

Standard Temperature Range, Ni 100
Standard
Temperature
Range Ni 100
250 C
>295.0
295.0
:
250.1
250.0
:
60.0
60.1
:
105.0
105,0
Units
Decimal
Range
Hex
7FFFH
32767
2950
:
2501
2500
:
600
601
:
1050
32768
Overflow
B86H
:
Overrange
9C5H
9C4H
:
Nominal range
FDA8H
FDA7H
:
Underrange
FBE6H
8000H
Underflow
Climate Temperature Range, Ni 100

Standard
Temperature
Range Ni 100
250 C
>295.00
295.00
:
250.01
250.00
:
60.00
60.01
:
105.00
105.00
Units
Range
Decimal
Hex
7FFFH
32767
29500
:
25001
25000
:
6000
6001
:
10500
32768
733CH
:
61A9H
Overflow
Overrange
61A8H
:
E890H
Nominal range
E88FH
:
D6FCH
8000H
Underrange
Underflow

Thermocouple Type K
Temperature
Range in C
Type K
>1622
1622
:
1373
1372
:
270
270
Units
Decimal
32767
16220
:
13730
13720
:
2700
2700
Hex
7FFFH
3FSCH
:
35A2H
Range
Overflow
Overrange
3598H
:
F574H
<F574H
Nominal range
Underrange
In the case of incorrect wiring (e. g. polarity reversal or open inputs) or of a sensor error in
the negative range (e. g. incorrect thermocouple type), the analog input module signals
underflow below F0C5H and Outputs 8000H

Thermocouple Type N
Temperature
Range in C
Type N
>1550
1550
:
1301
1300
:
270
270
Units
Decimal
32767
15500
:
13010
13000
:
2700
2700
Hexadecimal
7C8CH
3C8CH
:
32D2H
Range
Overflow
Overrange
32C8H
:
F574H
<F574H
Nominal range
Underrange
Thermocouple Type J
Temperature
Range inC
Type J
>1450
1450
:
1201
1200
:
210.0
210
Units
Decimal
32767
14500
:
12010
12000
:
2100
2100
Hexadecimal
7FFFH
38A4H
:
2EEAH
Range
Overflow
Overrange
2EE0H
:
F7CCH
<F7CCH
Nominal range
Underrange
Thermocouple Type E
Temperature
Range inC
Type E
>1201
1200
:
1001
1000
:
270
271
Units
Decimal
32767
12000
:
10010
10000
:
2700
2700
Hexadecimal
7FFFH
2EE0H
:
271AH
Range
Overflow
Overrange
2710H
:
F574H
<F574H
Nominal range
Underrange
Thermocouple Type L
Temperature
Range inC
Type L
Decimal
>1150
1150
:
901
900
:
200
200
32767
11500
:
9010
9000
:
2000
2000
Units
Range
Hexadecimal
7FFFH
2CECH
:
2332H
Overflow
Overrange
2328H
:
F830H
<F830H
Nominal range
Underrange
In the case of incorrect wiring (e. g. polarity reversal or open inputs) or of a sensor error in the
negative range (e. g. incorrect thermocouple type), the analog input module signals underflow
below F0C5H and Outputs 8000H
-
Voltage Output Ranges
Output
Range
0 to 10 V
0
11.7589
:
10.0004
10.0000
:
Output
Range
1 to 5 V
0
5.8794
:
5.0002
5.0000
:
Output
Range
10 V
0
11.7589
:
10.0004
10.0000
:
1.0000
Units
Decimal
Hex
>32511
32511
:
27649
27648
:
>7EFFH
0
:
0H
6912
6913
:
E500H
27648
27649
:
32512
32512
9400H
10.0000
10.0004
:
11.7589
0
:0.9999
0
7EFFH
:
6C01H
Range
Overflow
Overrange
6C00H
:
Nomial range
E4FFH
:
93FFH
:
8100H
<8100H
Underrange
Underflow
Current Output Ranges

Output
Range
0 to 20 mA
0
23.515
:
20.0007
20.000
:
Output
Range
4 to 20 mA
0
22.81
:
20.005
20.000
:
Output
Range
20 mA
0
23.515
:
20.0007
20.000
4.000
>32511
32511
:
27649
27648
:
>7EFFH
0
:
0H
6912
6913
:
E500H
27648
27649
:
32512
32512
9400H
20.000
0
3.9995
0
0
Units
Decimal
Hex
:
23.515
0
7EFFH
:
6C01H
Range
Overflow
Overrange
6C00H
:
Nominal range
E4FFH
:
93FFH
:
8100H
<8100H
Underrange
Underflow
3
STL
S7-400 S7-300
STL
English
Mnemonics
+
=
)
+AR1
+AR2
+D
-D
*D
/D
?D
+I
-I
*I
/I
?I
+R
-R
*R
/R
?R
A
A(
ABS
ACOS
AD
AN
AN(
ASIN
ATAN
AW
BE
BEC
BEU
BLD
BTD
BTI
CAD
CALL
CALL
Program Elements
Catalog
Integer math Instruction
Description
Bit logic Instruction
Assign
Nesting Closed
Accumulator
AR1 Add ACCU 1 to Address Register 1
Accumulator
AR2 Add ACCU 1 to Address Register 2
Add ACCU 1 and ACCU 2 as Double Integer (32-Bit)
Multiply ACCU 1 and ACCU 2 as Double Integer (32-Bit)
Divide ACCU 2 by ACCU 1 as Double Integer(32-Bit)
Add Integer Constant (16, 32-Bit)
Compare Double Integer (32-Bit) ==, <>, >, <, >=, <=
Compare
Add ACCU 1 and ACCU 2 as Integer (16-Bit)
Subtract ACCU 1 from ACCU 2 as Integer (16-Bit)
Multiply ACCU 1 and ACCU 2 as Integer (16-Bit)
Divide ACCU 2 by ACCU 1 as Integer (16-Bit)
Compare Integer (16-Bit) ==, <>, >, <, >=, <=
Compare
Add ACCU 1 and ACCU 2 as a Floating-Point Number (32-Bit IEEE-FP)
Floating point Instruction
Subtract ACCU 1 from ACCU 2 as a Floating-Point Number (32-Bit IEEE-FP)
Multiply ACCU 1 and ACCU 2 as Floating-Point Number (32-Bit IEEE-FP)
Divide ACCU 2 by ACCU 1 as a Floating-Point Number (32-Bit IEEE-FP)
Number (32-Bit IEEE-FP)
Compare
Compare Floating-Point Number (32-Bit) ==, <>, >, <, >=, <=
And
Absolute Value of a Floating-Point Number (32-Bit IEEE-FP)
Generate the Arc Cosine of a Floating-Point Number (32-Bit)
Word logic Instruction
AND Double Word (32-Bit)
And Not
Generate the Arc Sine of a Floating-Point Number (32-Bit)
Generate the Arc Tangent of a Floating-Point Number (32-Bit)
AND Word (16-Bit)
Program control
Block End
Program control
Program control
Program control
Convert
BCD to Integer (32-Bit)
Convert
BCD to Integer (16-Bit)
Convert
Change Byte Sequence in ACCU 1 (32-Bit)
Program control
Block Call
Program control
STL
English
Mnemonics
CALL
CAR
CAW
CC
CD
CDB
CLR
COS
CU
DEC
DTB
DTR
ENT
EXP
FN
FP
FR
FR
INC
INVD
INVI
ITB
ITD
JBI
JC
JCB
JCN
JL
JM
JMZ
JN
JNB
JNBI
JO
JOS
JP
JPZ
JU
JUO
JZ
L
L DBLG
L DBNO
Program Elements
Catalog
Description
Program control
Call Block from a Library
Load/Transfer
Exchange Address Register 1 with Address Register 2
Convert
Change Byte Sequence in ACCU 1-L (16-Bit)
Program control
Conditional Call
Counters
Counter Down
Convert
Exchange Shared DB and Instance DB
Clear RLO (=0)
Generate the Cosine of Angles as Floating-Point Numbers (32-Bit)
Counters
Counter Up
Accumulator
Decrement ACCU 1-L-L
Convert
Double Integer (32-Bit) to BCD
Convert
Convert Double Integer (32-Bit) to Floating-Point (32-Bit IEEE-FP)
Accumulator
Enter ACCU Stack
Generate the Exponential Value of a Floating-Point Number (32-Bit)
Edge Negative
Edge Positive
Counters
Enable Counter (Free) (free, FR C 0 to C 255)
Timers
Enable Timer (Free)
Accumulator
Increment ACCU 1-L-L
Convert
Ones Complement Double Integer (32-Bit)
Convert
Ones Complement Integer (16-Bit)
Convert
Integer (16-Bit) to BCD
Convert
Integer (16-Bit) to Double Integer (32-Bit)
Jumps
Jump if BR = 1
Jumps
Jump if RLO = 1
Jumps
JCB SPBB Jumps Jump if RLO = 1 with BR
Jumps
Jump if RLO = 0
Jumps
Jumps Jump to Labels
Jumps
Jump if Minus
Jumps
Jump if Minus or Zero
Jumps
Jump if Not Zero
Jumps
Jumps
Jump if BR = 0
Jumps
Jump if OV = 1
Jumps
Jump if OS = 1
Jumps
Jump if Plus
Jumps
Jump if Plus or Zero
Jumps
Jump Unconditional
Jumps
Jump if Unordered
Jumps
Jump if Zero
Load/Transfer
Load
Load/Transfer
Load Length of Shared DB in ACCU 1
Load/Transfer
Load Number of Shared DB in ACCU 1
STL
English
Mnemonics
L DILG
L DINO
L STW
L
Program Elements
Catalog
Load/Transfer
Description
Load/Transfer
Load Number of Instance DB in ACCU 1
Load Length of Instance DB in ACCU 1
Load/Transfer
Load Status Word into ACCU 1
Timers
Counters
LAR1
LAR1 <D>
LAR1 AR2
LAR2
LAR2 <D>
LC
Load/Transfer
Load Current Timer Value into ACCU 1 as Integer (the current timer
value can be a number from 0 to 255, for example, L T 32)
Load Current Counter Value into ACCU 1 (the current counter value
can be a number from 0 to 255, for example, L C 15)
Load/Transfer
Load Address Register 1 with Double Integer (32-Bit Pointer)
Load/Transfer
Load Address Register 1 from Address Register 2
Load/Transfer
Load/Transfer
Load Address Register 2 with Double Integer (32-Bit Pointer)
Counters
LC
Timers
LEAVE
LN
LOOP
MCR(
)MCR
MCRA
MCRD
MOD
NEGD
NEGI
NEGR
NOP 0
NOP 1
NOT
O
O(
OD
ON
ON(
OPN
OW
POP
POP
POP
PUSH
R
R
Accumulator
Load Current Counter Value into ACCU 1 as BCD (the current timer
value can be a number from 0 to 255, for example, LC C 15)
Load Current Timer Value into ACCU 1 as BCD (the current counter
alue can be a number from 0 to 255, for example, LC T 32)
Leave ACCU Stack
Timers
Generate the Natural Logarithm of a Floating-Point Number (32-Bit)
Jumps
Loop
Program control
Save RLO in MCR Stack, Begin MCR
Program control
End MCR
Program control
Activate MCR Area
Program control
Deactivate MCR Area
Division Remainder Double Integer (32-Bit)
Convert
Twos Complement Double Integer (32-Bit)
Convert
Twos Complement Integer (16-Bit)
Convert
Negate Floating-Point Number (32-Bit, IEEE-FP)
Accumulator
Null Instruction
Accumulator
Null Instruction
Negate RLO
Or
OR Double Word (32-Bit)
Or Not
DB call
Open a Data Block
OR Word (16-Bit)
Accumulator
CPU with Two ACCUs
Accumulator
CPU with Four ACCUs
Accumulator
CPU with Two ACCUs
Accumulator
CPU with Four ACCUs
Reset
Counters
Reset Counter (the current counter can be a number from 0 to 255,

for example, R C 15)
Reset Timer (the current timer can be a number from 0 to 255, for
example, R T 32)
STL
English
Mnemonics
Program Elements
Catalog
Description
RLD
RLDA
RND
RNDRND+
RRD
RRDA
S
S
Shift/Rotate
Rotate Left Double Word (32-Bit)
Shift/Rotate
Rotate ACCU 1 Left via CC 1 (32-Bit)
Convert
Round
Convert
Round to Lower Double Integer
SAVE
SD
SE
SET
SF
SIN
SLD
SLW
SP
SQR
SQRT
SRD
SRW
SS
SSD
SSI
T
T
TAK
TAN
TAR1
TAR1
TAR1
TAR2
TAR2
TRUNC
UC
X
X(
XN
XN(
XOD
XOW
Convert
Round to Upper Double Integer
Shift/Rotate
Rotate Right Double Word (32-Bit)
Shift/Rotate
Rotate ACCU 1 Right via CC 1 (32-Bit)
Set
Counters
Set Counter Preset Value (the current counter can be a number from
0 to 255, for example, S C 15)
Save RLO in BR Register
Timers
On-Delay Timer
Timers
Set
Timers
Off-Delay Timer
Generate the Sine of Angles as Floating-Point Numbers (32-Bit)
Shift/Rotate
Shift Left Double Word (32-Bit)
Shift/Rotate
Shift Left Word (16-Bit)
Timers
Pulse Timer
Generate the Square of a Floating-Point Number (32-Bit)
Generate the Square Root of a Floating-Point Number (32-Bit)
Shift/Rotate
Shift Right Double Word (32-Bit)
Shift/Rotate
Shift Right Word (16-Bit)
Timers
Shift/Rotate
Shift Sign Double Integer (32-Bit)
Shift/Rotate
Shift Sign Integer (16-Bit)
Load/Transfer
Transfer
Load/Transfer
Transfer ACCU 1 into Status Word
Accumulator
Toggle ACCU 1 with ACCU 2
Generate the Tangent of Angles as Floating-Point Numbers (32-Bit)
Load/Transfer
Load/Transfer
Transfer Address Register 1 to Destination (32-Bit Pointer)
Load/Transfer
Transfer Address Register 1 to Address Register 2
Load/Transfer
Load/Transfer
Transfer Address Register 2 to Destination (32-Bit Pointer)
Convert
Truncate
Program control
Unconditional Call
Exclusive Or
Exclusive Or Not
Exclusive OR Double Word (32-Bit)
Exclusive OR Word (16-Bit)
4
S7-400 Z Z cYf{ YmY Z
cYf{ YmY Z -1
Z SFC YmY Z -2
Z SFB YmY Z -3
S7-400
314
S7-400
Instr.
Address
ID
Description
Bit Logic Instructions

A/AN
I/Q
M
L
DBX
DIX
c [d]
c [AR1,m]
a.b
a.b
a.b
a.b
a.b
c [AR2,m]
O/ON
[AR1,m]
[AR2,m]
Parameter
I/Q
M
L
DBX
DIX
c [d]
c [AR1,m]
a.b
a.b
a.b
a.b
a.b
c [AR2,m]
X/XN
[AR1,m]
[AR2,m]
Parameter
I/Q
M
L
DBX
DIX
c [d]
c [AR1,m]
c [AR2,m]
[AR1,m]
[AR2,m]
Parameter
a.b
a.b
a.b
a.b
a.b
AND/AND NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
Memory-indirect, area-internal
Register-ind., area-internal
(AR1)
(AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
OR/OR NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
(AR1)
(AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
Exclusive OR/
Exclusive OR NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
(AR1)
(AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
Length
in
Words
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
1*/2
1**/2
2
2
2
2
2
0.2/0.3
0.2/0.3
0.3
0.3
0.3
0.3+
0.3+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.08
0.08
0.08
0.08
0.08
0.08+
0.08+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.3+
0.1+
0.08+
0.1+
2
2
2
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
1*/2
1**/2
2
2
2
2
2
0.2/0.3
0.2/0.3
0.3
0.3
0.3
0.3+
0.3+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.08
0.08
0.08
0.08
0.08
0.08+
0.08+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.3+
0.1+
0.08+
0.1+
2
2
2
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
2
2
2
2
2
2
2
0.3
0.3
0.3
0.3
0.3
0.3+
0.3+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.08
0.08
0.08
0.08
0.08
0.08+
0.08+
0.1
0.1
0.1
0.1
0.1
0.1+
0.1+
0.3+
0.1+
0.08+
0.1+
2
2
2
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
Bit Logic Instructions with Parenthetical Expressions

A(
AND left parenthesis
0.1
0.1
0.08
0.1
AN(
AND NOT left parenthesis
0.1
0.1
0.08
0.1
O(
OR left parenthesis
0.1
0.1
0.08
0.1
ON(
OR NOT left parenthesis
0.1
0.1
0.08
0.1
X(
Exclusive OR left parenthesis
0.1
0.1
0.08
0.1
XN(
Exclusive OR NOT left

parenthesis
Right parenthesis, removing
an entry from the nesting
stack.
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
+ Plus time required for loading the address of the instruction (see page 20)
* With direct instruction addressing; Address area 0 to 127
** With direct instruction addressing; Address area 0 to 255
S7-400
Instr.
Address
ID
Description
Length
in
Words
CPU 412
CPU 414
Execution Time in s
CPU 416
CPU 417
0.1
0.1
0.08
0.1
1 /2
2
1)
0,3
0.3+
0.1
0.1+
0.08
0.08+
0.1
0.1+
1 /2
2
1)
0,3
0.3+
0.1
0.1+
0.08
0.08+
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
1 /2
2
1)
1 /2
2
1)
0.3
0.3+
0.3
0.3+
0.1
0.1+
0.1
0.1+
0.08
0.08+
0.08
0.08+
0.1
0.1+
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
2
2
2
2
0.3
0.3+
0.3
0.3+
0.1
0.1+
0.1
0.1+
0.08
0.08+
0.08
0.08+
0.1
0.1+
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
ORing of AND Instructions

O
ORing of AND operations

according to the rule: AND
before OR
Logic Instructions with Timers and Counters

A/AN
O/ON
X/XN
T
T
f
[e]
C
C
f
[e]
Timer
para.
Counter
para.
T
T
C
C
Timer/counter (addressing via

parameter)
f
[e]
f
[e]
Timer
para.
Counter
para.
T
T
C
C
Timer
para.
Counter
para.
AND/AND NOT
Timer
Timer, memory-indirect
addressing
Counter
Counter, memory-indirect
addressing
OR/OR NOT
Timer
Timer, memory-indirect addr.
Counter
Counter, memory-indirect
addressing
Timer/counter (addressing via
parameter)
f
[e]
f
[e]
EXCLUSIVE OR/EXCLUSIVE
OR NOT
Timer
Timer, memory-indirect addr.
Counter
Counter, mem.-indirect addr.
EXCLUSIVE OR
timer/counter (addressing
via parameter)
Word Logic Instructions with the Contents of Accumulator 1

AW
AW
W#16#p
OW
OW
W#16#p
XOW
XOW
W#16#p
AD
AD
DW#16#p
OD
OD
DW#16#p
XOD
XOD
+
1)
DW#16#p
AND ACCU2-L
0.1
0.1
0.08
0.1
AND 16-bit constant
0.2
0.1
0.08
0.1
OR ACCU2-L
0.1
0.1
0.08
0.1
OR 16-bit constant
0.2
0.1
0.08
0.1
EXCLUSIVE OR ACCU2-L
0.1
0.1
0.08
0.1
EXCLUSIVE OR 16-bit
constant
AND ACCU2
0.2
0.1
0.08
0.1
0.1
0.1
0.08
0.1
AND 32-bit constant
0.3
0.15
0.12
0.15
OR ACCU2
0.1
0.1
0.08
0.1
OR 32-bit constant
0.3
0.15
0.12
0.15
EXCLUSIVE OR ACCU2
0.1
0.1
0.08
0.1
EXCLUSIVE OR 32-bit
constant
0.3
0.15
0.12
0.15
Plus time required for loading the address of the instruction (see page 20)
With direct instruction addressing ;Address area 0 to 255
S7-400
Instr.
Address
ID
Description
Length
in
Words
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
Evaluating Conditions Using AND, OR and EXCLUSIVE OR

A/AN
O/ON
X/XN
AND/AND NOT
OR/OR-NOT
EXCLUSIVE OR/
EXCLUSIVE-OR-NOT
Result=0
(A1=0 and A0=0)
==0
0.1
0.1
0.08
0.1
>0
Result>0
(CC1=1 and CC0=0)
0.1
0.1
0.08
0.1
<0
Result<0
(CC1=0 and CC0=1)
0.1
0.1
0.08
0.1
<>0
Result<>0
((CC1=0 and CC0=1) or
(CC1=1 and
CC0=0))
Result>=0
(CC1=0 and
CC0=0))
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
>=0
<=0
Result<=0
(CC1=0 and
CC0=0))
0.1
0.1
0.08
0.1
UO
Unordered math instruction

(CC1=1 and CC0=1)
0.1
0.1
0.08
0.1
OS
AND OS=1
0.1
0.1
0.08
0.1
BR
AND BR=1
0.1
0.1
0.08
0.1
OV
AND OV=1
0.1
0.1
0.08
0.1
2
2
2
2
0.4
0.4
0.4
0.4
0.2
0.2
0.2
0.2
0.16
0.16
0.16
0.16
0.2
0.2
0.2
0.2
Edge-Triggered Instructions
FP/FN
I/Q
M
L
DBX
a.b
a.b
1)
a.b
a.b
The positive/negative edge is

indicated by RLO = 1. The bit
addressed in the instruction is
the auxiliary edge bit
memory.
DIX
a.b
2
0.4
0.2
0.16
0.2
c [d]
2
0.4+
0.2+
0.16+
0.2+
c [AR1,m]
2
0.4+
0.2+
0.16+
0.2+
c [AR2,m]
2
0.4+
0.2+
0.16+
0.2+
[AR1,m]
2
0.4+
0.2+
0.16+
0.2+
[AR2,m]
2
0.4+
0.2+
0.16+
0.2+
Parameter
2
0.4+
0.2+
0.16+
0.2+
1) Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running).
Setting/Resetting Bit Addresses

S
R
I/Q
M
L
DBX
DIX
c [d]
c [AR1,m]
c [AR2,m]
[AR1,m]
[AR2,m]
Parameter
a.b
a.b
a.b
a.b
a.b
Set addressed bit to 1

Set addressed bit to 0
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
Memory-indirect, areainternal
Register-indirect, areainternal (AR1)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
1 /2
2)
1 /2
2
2
2
2
1)
0.3/0.4
0.3/0.4
0.4
0.4
0.4
0.4+
0.2
0.2
0.2
0.2
0.2
0.2+
0.16
0.16
0.16
0.16
0.16
0.16+
0.2
0.2
0.2
0.2
0.2
0.2+
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
2
2
2
0.4+
0.4+
0.4+
0.2+
0.2+
0.2+
0.16+
0.16+
0.16+
0.2+
0.2+
0.2+
S7-400
Length
in
Words
Instr.
Address
ID
Description
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
Setting/Resetting Bit Addresses, continued

=
Assign RLO
1)
To input/output
1 /2
2)
To bit memory
1 /2
To local data bit
2
To data bit
2
To instance data bit
2
Memory-indirect, area2
internal
c [AR1,m]
Register-indirect, area2
internal (AR1)
c [AR2,m]
Register-indirect, area2
internal (AR2)
[AR1,m]
Area-crossing (AR1)
2
[AR2,m]
Area-crossing (AR2)
2
Parameter
Via parameter
2
With direct instruction addressing; Address area 0 to 127
I/Q
M
L
DBX
DIX
c [d]
a.b
a.b
a.b
a.b
a.b
Instructions Directly Affecting the RLO

CLR
SET
NOT
SAVE
Set RLO to 0
Set RLO to 1
Negate RLO
Save RLO to the BR bit
Timer Instructions
SP
Tf
T [e]
SE
Tf
1)
Start timer as pulse on edge 1 /2

change from 0 to 1
Timer para.
T [e]
2
1)
Start timer as extended pulse 1 /2

on
edge change from 0 to 1
Timer para.
SD
Tf
T [e]
2
Start timer as ON delay on
edge
change from 0 to 1
Timer para.
SS
Tf
T [e]
Tf
T [e]
Timer para.
FR
Tf
T [e]
Timer para.
Tf
T [e]
1)
1 /2
2
Start timer as retentive ON
delay
on edge change from 0 to
1
Timer para.
SF
1
1
1
1
1)
1 /2
2
Start timer as OFF delay on
edge
change from 0 to 1
1)
1 /2
2
1)
Enable timer for restarting on 1 /2

edge change from 0 to 1
(reset edge bit memory for
starting timer)
2
1)
Reset timer
1 /2
Timer para.
2
With direct instruction addressing Timer No.: 0 to 255
0.3/0.4
0.3/0.4
0.4
0.4
0.4
0.4+
0.2
0.2
0.2
0.2
0.2
0.2+
0.16
0.16
0.16
0.16
0.16
0.16+
0.2
0.2
0.2
0.2
0.2
0.2+
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
0.4+
0.4+
0.4+
0.2+
0.2+
0.2+
0.16+
0.16+
0.16+
0.2+
0.2+
0.2+
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.08
0.08
0.08
0.08
0.1
0.1
0.1
0.1
0.3/0.4
0.3+0.4+
0.2
0.2+
0.16
0.16+
0.2
0.2+
0.4+
0.2+
0.16+
0.2+
0.3/0.4
0.2
0.16
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
0.3/0.4
0.2
0.16
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
0.3/0.4
0.2
0.16
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
0.3/0.4
0.2
0.16
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
0.3/0.4
0.4+
0.2
0.2+
0.16
0.16+
0.2
0.2+
0.4+
0.3/0.4
0.4+
0.2+
0.2
0.2+
0.16+
0.16
0.16+
0.2+
0.2
0.2+
0.4+
0.2+
0.16+
0.2+
S7-400
Length
in
Words
Instr.
Address
ID
Description
Counter Instructions
S
CU
Cf
C [e]
Counter para.
Cf
C [e]
Counter para.
Cf
C [e]
Counter para.
CD
Cf
C [e]
Counter para.
FR
C [e]
Counter para.
Load Instructions
L
CPU 417
0)
0.3/0.4
0.4+
0.4+
0.3/0.4
0.4+
0.2
0.2+
0.2+
0.2
0.2+
0.16
0.16+
0.16+
0.16
0.16+
0.2
0.2+
0.2+
0.2
0.2+
2
0)
1 /2
0.4+
0.3/0.4
0.2+
0.2
0.16+
0.16
0.2+
0.2
0.4+
0.4+
0.2+
0.2+
0.16+
0.16+
0.2+
0.2+
1 /2
0.3/0.4
0.2
0.16
0.2
0.4+
0.4+
0.2+
0.2+
0.16+
0.16+
0.2+
0.2+
Increment counter by 1 on
edge
change from 0 to 1
Decrement counter by 1 on
edge
change from 0 to 1
0)
Enable counter on edge

1 /2
change
from 0 to 1 (reset edge bit
memory for up and down
counting and setting the
2
counter)
0.3/0.4
0.2
0.16
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
1 /2
1)
1 /2
2
3)
1 /2
2
2
2
2
0.2/0.3
0.2/0.3
0.3
0.2/0.3
0.3
0.3
0.3
0.3+
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1+
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.08+
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
2
2
2
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
1 /2
1)
1 /2
2
1)
0.2/0.3
0.2/0.3
0.3
0.1
0.1
0.1
0.08
0.08
0.08
0.1
0.1
0.1
3)
IW
QW
PIW
MW
LW
a
a
Bit memory word

Local data word
1 /2
2
0.2/0.3
0.3
0.1
0.1
0.08
0.08
0.1
0.1
DBW
DIW
a
a
Data word
Instance data word
... into ACCU1-L
2
2
0.3
0.3
0.1
0.1
0.08
0.08
0.1
0.1
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
a
a
a
a
a
a
a
g [AR2,m]
B[AR1,m]
B[AR2,m]
Parameter
h [d]
h [AR1,m]
h [AR2,m]
W[AR1,m]
W[AR2,m]
Parameter
0)
1)
2)
3)
CPU 416
Load ...
Input byte
Output byte
2)
Peripheral input byte
Bit memory byte
Local data byte
Data byte
Instance data byte
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
Load ...
Input word
Output word
2)
Peripheral input word
IB
QB
PIB
MB
LB
DBB
DIB
g [d]
g [AR1,m]
CPU 414
Presetting of counter on edge 1 /2

change from 0 to 1
2
0)
Reset counter to 0
1 /2
when RLO = 1
0)
Cf
Execution Time in s
CPU 412
1)
0.3+
0.1+
0.08+
0.1+
2
2
2
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
With direct instruction addressing Counter No.: 0 to 255
With indirect instruction addressing; Address area 0 to 127
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo 37 s, redundant 67 s
S7-400
Length
in
Words
Instr.
Address
ID
Description
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
Load Instructions, continued

L
IDa
QD
PID
a
a
Load ...
1)
Input double word
1 /2
1)
Output double word
1 /2
Peripheral input double word 2
MD
LD
a
a
Bit memory double word

Local data double word
DBD
DID
a
a
Data double word

Instance data double word
... in ACCU1
Memory-indirect, area
internal
Register-ind., area internal
(AR1)
(AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
Load ...
8-bit constant into ACCU1-LL
16-bit constant into ACCU1-L
32-bit constant into ACCU1
Load constant into ACCU1
(addressed via parameter)
Load 16-bit binary constant
into
ACCU1-L
Load 32-bit binary constant
into
ACCU1
Load 8-bit-hexadecimal
constant
into ACCU1-L
Load 16-bit hexadecimal
constant into ACCU1-L
Load 32-bit hexadecimal
Load ...
Load 1 character
Load 2 characters
Load 3 characters
Load 4 characters
Load IEC date
i [d]
i [AR1,m]
i [AR2,m]
D[AR1,m]
D[AR2,m]
Parameter
k8
k16
k32
Parameter
2#n
B#16#p
W#16#p
DW#16#p
x
xx
xxx
xxxx
D# time
value
S5T# time value
TOD# time value
T# time value
C# count value
B# (b1, b2)
B# (b1, b2, b3,
b4)
P# bit
pointer
L# integer
Real number
+
1)
2)
3)
0.3/0.4
0.3/0.4
0.3/0.4
0.2
0.2
0.2
0.16
0.16
0.16
0.2
0.2
0.2
1 /2
2
0.3/0.4
0.4
0.2
0.2
0.16
0.16
0.2
0.2
2
2
0.4
0.4
0.2
0.2
0.16
0.16
0.2
0.2
0.4+
0.2+
0.16+
0.2+
0.4+
0.2+
0.16+
0.2+
2)
3)
0.4+
0.2+
0.16+
0.2+
2
2
2
0.4+
0.4+
0.4+
0.2+
0.2+
0.2+
0.16+
0.16+
0.16+
0.2+
0.2+
0.2+
2
2
3
2
0.2
0.2
0.3
0.2/0.3+
0.1
0.1
0.15
0.1+
0.08
0.08
0.12
0.08+
0.1
0.1
0.15
0.1+
0.2
0.1
0.08
0.1
0.3
0.15
0.12
0.15
0.1
0.1
0.08
0.1
0.2
0.1
0.08
0.1
0.3
0.15
0.12
0.15
2
2
3
3
3
0.2
0.2
0.3
0.3
0.3
0.1
0.1
0.15
0.15
0.15
0.08
0.08
0.12
0.12
0.12
0.1
0.1
0.15
0.15
0.15
0.2
0.1
0.08
0.1
3
2
3
2
0.3
0.2
0.3
0.2
0.15
0.1
0.15
0.1
0.12
0.08
0.12
0.08
0.15
0.1
0.15
0.1
0.2
0.1
0.08
0.1
0.3
0.15
0.12
0.15
0.3
0.15
0.12
0.15
Load 32-bit integer constant 3

Load floating-point number 3
0.3
0.3
0.15
0.15
0.12
0.12
0.15
0.15
Load S7 time constant (16

bits)
Load IEC time constant
Load 16-bit time constant
Load 32-bit time constant
Load counter constant (BCD
code)
Load constant as byte (b1,
b2)
Load constant as 4 bytes
(b1, b2, b3, b4)
Load bit pointer
With indirect instruction addressing; Address area 0 to 127
S7-400
Length
in
Words
Instr.
Address
ID
Description
Load Instructions for Timers and Counters

L
LC
1)
Tf
T (e)
Load time value
1 /2
2
Timer para.
Load time value (addressed 2

via parameter)
Cf
C (e)
Load count value
Counter para.
Load count value (addressed 2

via parameter)
Tf
T (e)
Load time value in BCD
Timer para.
Cf
C (e)
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
0.2/0.3
0.3+
0.1
0.1+
0.08
0.08+
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.2/0.3
0.3+
0.1
0.1+
0.08
0.08+
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
1 /2
2
0.3
0.3+
0.3
0.3+
0.24
0.24+
0.3
0.3+
Load time value in BCD

0.3+
0.3+
0.24+
0.3+
Load count value in BCD
1 /2
2
0.3
0.3+
0.3
0.3+
0.24
0.24+
0.3
0.3+
0.3+
0.3+
0.24+
0.3+
1 /2
1)
1 /2
2
1)
0.2/0.3
0.2/0.3
0.3
0.1
0.1
0.1
0.08
0.08
0.08
0.1
0.1
0.1
3)
0.2/0.3
0.3
0.3
0.3
0.3+
0.1
0.1
0.1
0.1
0.1+
0.08
0.08
0.08
0.08
0.08+
0.1
0.1
0.1
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
1)
1 /2
2
1)
1)
Counter para.
Load count value in BCD

2
1) With direct instruction addressing; Timer/counter No.: 0 to 255
Transfer Instructions
T
IB
QB
PQB
a
a
a
MB
LB
DBB
DIB
g [d]
a
a
a
a
Transfer contents of
ACCU1-LL to ...
input byte
output byte
2)
peripheral output byte
bit memory byte

1 /2
local data byte
2
data byte
2
instance data byte
2
2
internal
g [AR1,m]
2
(AR1)
g [AR2,m]
2
(AR2)
B[AR1,m]
Area-crossing (AR1)
2
B[AR2,m]
Area-crossing (AR2)
2
Parameter
Via parameter
2

Transfer contents of ACCU1L to ...
1)
IW
a
input word
1 /2
1)
QW
a
output word
1 /2
2)
PQW
a
peripheral output word
2
3)
MW
a
bit memory word
1 /2
LW
a
local data word
2
DBW
a
data word
2
DIW
a
instance data word
2
h [d]
2
internal
h [AR1.m]
2
(AR1)
h [AR2,m]
2
(AR2)
W[AR1.m]
Area-crossing (AR1)
2
W[AR2,m]
Area-crossing (AR2)
2
Parameter
Via parameter
2
3)
0.2/0.3
0.2/0.3
0.3
0.2/0.3
0.3
0.3
0.3
0.3+
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1+
0.08
0.08
0.08
0.08
0.08
0.08
0.08
0.08+
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.1+
0.08+
0.1+
0.3+
0.3+
0.3+
0.1+
0.1+
0.1+
0.08+
0.08+
0.08+
0.1+
0.1+
0.1+
S7-400
Length
in
Words
Instr.
Address
ID
Description
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
Transfer Instructions, continued

T
ID
QD
PQD
a
a
a
Transfer contents of
ACCU1 to ...
1)
Input double word
1 /2
1)
Output double word
1 /2
2)
periph. output double word 2
MD
LD
a
a

DBD
DID
a
a
Data double word

0.3/0.4
0.3/0.4
0.4
0.2
0.2
0.2
0.16
0.16
0.16
0.2
0.2
0.2
1 /2
2
0.3/0.4
0.4
0.2
0.2
0.16
0.16
0.2
0.2
2
2
0.4
0.4
0.2
0.2
0.16
0.16
0.2
0.2
3)
i [d]
2
0.4+
0.2+
0.16+
0.2+
internal
i [AR1,m]
2
0.4+
0.2+
0.16+
0.2+
(AR1)
i [AR2,m]
2
0.4+
0.2+
0.16+
0.2+
(AR2)
D[AR1,m]
Area-crossing (AR1)
2
0.4+
0.2+
0.16+
0.2+
D[AR2,m]
Area-crossing (AR2)
2
0.4+
0.2+
0.16+
0.2+
Parameter
Via parameter
2
0.4+
0.2+
0.16+
0.2+
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo 36s, redundant 65 s
3) With direct instruction addressing; Address area 0 to 255
Load and Transfer Instructions for Address Registers

LAR1
LAR2
AR2
DBD
DID
m
LD
MD
DBD
DID
m
LD
MD
a
a
a
a
a
a
a
a
Load contents from ...

ACCU1
Data double word
32-bit constant as pointer
... into AR2
Transfer contents from AR1
in ...
ACCU1
Address register 2
Data double word
a
a
a
a
Transfer contents from AR2

in ...
ACCU1
Data double word
a
a
a
a
TAR1
AR2
DBD
DID
LD
MD
TAR2
DBD
DID
LD
MD
CAR
Load contents from ...

ACCU1
Address register 2
Data double word
32-bit constant as pointer
... into AR1
Exchange the contents of

AR1 and AR2
1
1
2
2
3
2
2
0.2
0.2
0.4
0.4
0.3
0.4
0.4
0.2
0.2
0.3
0.3
0.2
0.3
0.3
0.16
0.16
0.24
0.24
0.16
0.24
0.24
0.2
0.2
0.3
0.3
0.2
0.3
0.3
1
2
2
3
2
2
0.2
0.4
0.4
0.3
0.4
0.4
0.2
0.3
0.3
0.2
0.3
0.3
0.16
0.24
0.24
0.16
0.24
0.24
0.2
0.3
0.3
0.2
0.3
0.3
1
1
2
2
2
2
0.1
0.2
0.4
0.4
0.4
0.4
0.1
0.2
0.2
0.2
0.2
0.2
0.08
0.16
0.16
0.16
0.16
0.16
0.1
0.2
0.2
0.2
0.2
0.2
1
2
2
2
2
0.1
0.4
0.4
0.4
0.4
0.1
0.2
0.2
0.2
0.2
0.08
0.16
0.16
0.16
0.16
0.1
0.2
0.2
0.2
0.2
0.4
0.4
0.32
0.4
0.1
0.1
0.1
0.1
0.08
0.08
0.1
0.1
Load and Transfer Instructions for the Status Word

L
T
STW
STW
Load status word into ACCU1

Transfer ACCU1 (bits 0 to 8)
to the status word
S7-400
Length
in
Words
Instr.
Address
ID
Description
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
Load Instructions for DB Number and DB Length

L
L
DBNO
DINO
DBLG
DILG
0.1
0.1
0.1
0.1
0.08
0.08
0.1
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
Add 2 integers (16 bits)

1
(ACCU1-L)=(ACCU1L)+(ACCU2-L)
Subtract 1 integer from
1
another (16 bits)
(ACCU1-L)=(ACCU2-L)(ACCU1-L)
Multiply 1 integer by another 1
(16 bits)
(ACCU1)=(ACCU2-L) (ACCU1-L)
*
Divide 1 integer by another 1
(16 bits)
(ACCU1-L)=(ACCU2L):(ACCU1-L)
The remainder is in ACCU1-H
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.8
0.8
0.64
0.8
0.8
0.8
0.64
0.8
+D
Add 2 integers (32-bit)

1
(ACCU1)=(ACCU2)+(ACCU1)
0.1
0.1
0.08
0.1
Subtract 1 integer from

1
another (32 bits)
(ACCU1)=(ACCU2)-(ACCU1)
0.1
0.1
0.08
0.1
Multiply 1 integer by another 1

(32 bits)
(ACCU1)=(ACCU2) (ACCU1)
*
Divide 1 integer by another 1
(32 bits)
(ACCU1)=(ACCU2):(ACCU1)
1.3
1.3
1.04
1.3
1.3
1.3
1.04
1.3
Divide 1 integer by another

(32 bits) and
load the remainder into
ACCU1:
(ACCU1)=remainder of
1.3
1.3
1.04
1.3
[(ACCU2):(ACCU1)]
Add 2 real numbers (32 bits) 1
(ACCU1)=(ACCU2)+(ACCU1)
0.6
0.6
0.48
0.6
0.6
0.6
0.48
0.6
1.4
1.4
1.12
1.4
2.1
2.1
1.68
2.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
Integer Math (16 Bits)

+I
I
/I
Integer Math (32 Bits)
/D
MOD
Load number of data block

1
Load number of instance data 1
block
Load length of data block into 1
byte
Load length of instance data 1
block into byte
Floating-Point Math (32 Bits)

+R
R
*R
/R
NEGR
ABS
Subtract 1 real number from

another (32 bits)
(ACCU1)=(ACCU2)-(ACCU1)
Multiply 1 real number by
another (32 bits)
(ACCU1)=(ACCU2) (ACCU1)
*
Divide 1 real number by
another (32 bits)
(ACCU1)=(ACCU2):(ACCU1)
Negate the real number in
ACCU1
Form the absolute value of
the real
number in ACCU1
Square Root and Square Instructions (32 Bits)

SQRT
Calculate the square root of a 1

real number in ACCU1
72
40
37 - 39
40
SQR
Form the square of the real

number in ACCU1
1.4
1.4
1.12
1.4
S7-400
Length
in
Words
Instr.
Address
ID
Description
Logarithmic Function (32 Bits)
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
LN
Form the natural logarithm of 1

a
real number in ACCU1
63
35
33
35
EXP
Calculate the exponential

1
value
of a real number in ACCU1 to
the
base e (= 2.71828)
63
35
32 - 34
35
56
31
30
31
Trigonometrical Functions (32 Bits)

SIN
Calculate the sine of a real

number
ASIN
Calculate the arcsine of a real 1

number
117 - 133
65 - 74
62 - 70
65 - 74
COS
Calculate the cosine of a real 1

number
58
32
30
32
ACOS
Calculate the arccosine of a

real
number
122 - 139
68 - 77
65 - 72
68 - 77
TAN
Calculate the tangent of a

real
number
58 - 63
32 - 35
30 - 33
32 - 35
ATAN
Calculate the arctangent of a 1

real
number
43 - 58
24 - 32
23 - 30
24 - 32
Adding Constants
+
i8
Add an 8-bit integer constant 1
0.1
0.1
0.08
0.1
i16
Add a 16-bit integer constant 2
0.2
0.1
0.08
0.1
i32
Add a 32-bit integer constant 3
0.3
0.15
0.12
0.15
Add the contents of ACCU1-L 1

to
those of AR1
0.2
0.2
0.16
0.2
Add a pointer constant to the 2

contents of AR1
0.2
0.2
0.16
0.2
Add the contents of ACCU1-L 1

to
those of AR2
0.2
0.2
0.16
0.2
Add pointer constant to the

contents of AR2
0.2
0.2
0.16
0.2
Adding Using Address Registers

+AR1
+AR1
m (0 to
4095)
+AR2
+AR2
m (0 to
4095)
Comparison Instructions (16-Bit Integers)

==I
ACCU2-L=ACCU1-L
0.1
0.1
0.08
0.1
<>I
ACCU2-L_ACCU1-L
0.1
0.1
0.08
0.1
<I
ACCU2-L<ACCU1-L
0.1
0.1
0.08
0.1
<=I
ACCU2-L<=ACCU1-L
0.1
0.1
0.08
0.1
>I
ACCU2-L>ACCU1-L
0.1
0.1
0.08
0.1
>=I
ACCU2-L>=ACCU1-L
0.1
0.1
0.08
0.1
S7-400
Length
in
Words
Instr.
Address
ID
Description
Comparison Instructions (32-Bit Integers)
Execution Time in s
CPU 412
0.1
CPU 414
0.1
CPU 416
0.08
CPU 417
==D
ACCU2=ACCU1
0.1
<>D
ACCU2_ACCU1
0.1
0.1
0.08
0.1
<D
ACCU2<ACCU1
0.1
0.1
0.08
0.1
<=D
ACCU2<=ACCU1
0.1
0.1
0.08
0.1
>D
ACCU2>ACCU1
0.1
0.1
0.08
0.1
>=D
ACCU2>=ACCU1
0.1
0.1
0.08
0.1
==R
ACCU2=ACCU1
0.1
0.1
0.08
0.1
<>R
ACCU2_ACCU1
0.1
0.1
0.08
0.1
<R
ACCU2<ACCU1
0.1
0.1
0.08
0.1
<=R
ACCU2<=ACCU1
0.1
0.1
0.08
0.1
>R
ACCU2>ACCU1
0.1
0.1
0.08
0.1
>=R
ACCU2>=ACCU1
0.1
0.1
0.08
0.1
Shift the contents of ACCU1-L to the

left. Positions
that become free are provided with
zeros.
0.1
0.1
0.08
0.1
Shift the contents of ACCU1 to the left. 1

Positions that
become free are provided with zeros.
0.1
0.1
0.08
0.1

1
right. Positions
zeros.
Shift the contents of ACCU1 to the left. 1
Positions that
become free are provided with zeros.
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1

right. Positions
zeros.
0.1
0.1
0.08
0.1
Shift the contents of ACCU1 to the right. 1

Positions
zeros.
0.1
0.1
0.08
0.1
Shift the contents of ACCU1-L with sign 1

to the right.
Positions that become free are provided
with with the
sign (bit 15).
Shift the contents of ACCU1 with sign to 1
the right.
Positions that become free are provided
with with the
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
Rotate the contents of ACCU1 to the right 1
0.1
0.1
0.08
0.1
Rotate the contents of ACCU1 one

bit position to the left through
0.1
0.08
0.1
RLDA
Shift Instructions
SLW
1)
SLW
0 ... 15
SLD
SLD
SRW
0 ... 32
1)
SRW
0 ... 15
SLD
SLD
SRW
0 ... 32
1)
SRW
0 ... 15
SRD
SRD
SSI
0 ... 32
1)
SSI
0 ... 15
SSD
1)
No. of places shifted: 0 to 16
Rotate Instructions
RLD
RLD
RRD
RRD
RLDA
Rotate the contents of ACCU1 to the left
0 ... 32
0 ... 32
0.1
S7-400
Length
in
Words
Instr.
Address
ID
Description
Rotate Instructions, continued

RRDA
Rotate the contents of ACCU1 one

bit position to the right through
condition code bit CC 1
0.1
Execution Time in s
CPU 412
0.1
CPU 414
0.08
CPU 416
CPU 417
0.1
RRDA
Accumulator Transfer Instructions, Incrementing and Decrementing

CAW
Reverse the order of the bytes in

ACCU1-L.
Reverse the order of the bytes in
ACCU1.
Swap the contents of ACCU1 and
ACCU2
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
ENT
The contents of ACCU2 and ACCU3 are 1

transferred to ACCU3 and ACCU4.
0.1
0.1
0.08
0.1
LEAVE
The contents of ACCU3 and ACCU4 are 1

transferred to ACCU2 and ACCU3.
0.1
0.1
0.08
0.1
PUSH
The contents of ACCU1, ACCU2 and

ACCU3
are transferred to ACCU2, ACCU3 and
ACCU4
The contents of ACCU2, ACCU3 and
ACCU4
are transferred to ACCU1, ACCU2 and
ACCU3
Increment ACCU1-LL
Decrement ACCU1-LL
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
1
1
0.1
0.1
0.1
0.1
0.08
0.08
0.1
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.3
0.3
0.24
0.3
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.2
0.2
0.16
0.2
0.4
0.4
0.32
0.4
CAD
TAK
POP
INC
DEC
k8
k8
Program Display and Null Operation Instructions

BLD
k8
NOP
0
1
Program display instruction:

Is treated by the CPU as a null
operation instruction
Null operation instruction
Data Type Conversion Instructions

BTI
BTD
DTR
ITD
ITB
DTB
RND+
RND
RND-
TRUNC
Convert contents of ACCU1-L

from BCD (0 to +/- 999) to integer
(16 bits) (BCD To Int)
Convert contents of ACCU1 from
BCD (0 to +/-9 999 999) to
double integer (32 bits) (BCD To
Doubleint)
double integer (32 bits) to real
number (32 bits) (Doubleint To
Real)
integer (16 bits) to double integer
(32 bits) (Int To Doubleint)
Convert contents of ACCU1-L from
integer (16 bits) to BCD from 0 to
+/- 999 (Int To BCD)
double integer (32 bits) to BCD from 0
to +/- 9 999 999 (Doubleint To BCD)
Convert a real number into a
32-bit integer. The number is
rounded up to the next whole
number.
32-bit integer.
32-bit integer. The number is
rounded down to the next whole
number.
32-bit integer. The places after
the decimal point are truncated.
0.4
0.4
0.32
0.4
0.4
0.4
0.32
0.4
0.4
0.4
0.32
0.4
S7-400
326
Length
in
Words
Instr.
Address
ID
Description
Forming the Ones and Twos Complements
Execution Time in s
CPU 412
CPU 414
CPU 416
CPU 417
INVI
Form the ones complement of 1

ACCU1-L
0.1
0.1
0.08
0.1
INVD
Form the ones complement of 1

ACCU1
Form the twos complement of 1
ACCU1-L (integer)
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
NEGI
NEGD
Form the twos complement of 1

ACCU1 (double integer)
Block Call Instructions
1)
CALL
FB q, DB q
Unconditional call of an FB,

with
parameter transfer
CALL
SFB q,
DB q
Unconditional call of an SFB, 2

with parameter transfer
CALL
FC q
Unconditional call of a
function,
CALL
SFC q
Unconditional call of an SFC, 2

UC
FB q
FC q
FB [e]
FC [e]
Parameter
Unconditional call of blocks,

without parameter transfer
Memory-indirect FB call
Memory-indirect FC call
FB/FC call via parameter
FB q
Conditional call of blocks,

1 /2
without
parameter transfer
Memory-indirect FB call
2
Memory-indirect FC call
2
FB/FC call via parameter
2
1)
Open:
1 /2
Data block
Instance data block
Data block, memory-indirect
Instance DB, memory-indirect
Data block using parameters
CC
OPN
1)
1 /2
1)
1 /2
2
2
2
1)
FC q
FB [e]
FC [e]
Parameter
DB
DI
DB
DI
Parameter
1 /2
q
q
[e]
[e]
8.2
3)
3.2
3)
2.56
3)
XX
8.2
3)
3.2
3)
2.56
3)
XX
4.6
3)
1.8
3)
1.44
3)
XX
4.6
3)
1.8
3)
1.44
3)
XX
2.1/2.2
2.1/2.2
2.2+
2.2+
2.2+
1.4
1.4
1.4+
1.4+
1.4+
2.3/2.4/0.4
4)
1.4/0.4
2.3/2.4/0.4
4)
2.4+/0.4
4)
2.4+/0.4
4)
2.4+/0.4
4)
1.12
1.12
1.12+
1.12+
1.12+
4)
1.12/0.32
1.4/0.4
4)
1.4+/0.4
4)
1.4+/0.4
4)
1.4+/0.4
4)
0.6/0.7
0.7
0.7+
0.7+
0.7+
2.8
2.8
2.2
1)
0.4
1.4
1.4
1.4+
1.4+
1.4+
4)
1.4/04
1.12/0.32
4)
1.12+/0.32
4)
1.12+/0.32
4)
1.12+/0.32
4)
1.4/0.4
4)
1.4+/0.4
4)
1.4+/0.4
4)
1.4+/0.4
0.3
0.3
0.3+
0.3+
0.3+
0.24
0.24
0.24+
0.24+
0.24+
0.3
0.3
0.3+
0.3+
0.3+
2.0
2.0
1.76
1)
0.32
1.60
1.60
2.2
1)
0.4
2.0
2.0
0.2
0.16
4)
With direct instruction (DB) addressing; Block No. 0 to 255
Depending on RLO, sets RLO = 1
Plus time required for supplying parameters
4) If call is not executed
Block End Instructions

BE
BEU
BEC
If jump is not executed
End block
End block unconditionally
End block conditionally if
RLO = 1
1
1
3.0
1)
0.4
Exchanging Shared Data Block and Instance Data Block

CDB
Exchange shared data block 1

and instance data block
0.2
4)
S7-400
327
Length
in
Words
Instr.
Address
ID
Jump Instructions
JU
JC
JCN
JCB
LABEL
LABEL
LABEL
LABEL
JNB
LABEL
JBI
JNBI
JO
LABEL
LABEL
LABEL
JOS
LABEL
JUO
LABEL
JZ
LABEL
JP
LABEL
JM
LABEL
JN
LABEL
JMZ
LABEL
JPZ
LABEL
JL
LABEL
LOOP
Description
1)
Jump unconditionally
1 /2
1)
Jump if RLO = 1
1 /2
Jump if RLO = 0
2
Jump if RLO = 1.
2
Save the RLO in the BR bit
Jump if RLO = 0.
2
Save the RLO in the BR bit
Jump if BR = 1
2
Jump if BR = 0
2
1)
Jump on stored overflow
1 /2
(OV = 1)
Jump on stored overflow
2
(OS = 1)
Jump if unordered math
2
instruction (CC1=1 and
CC0=1)
1)
Jump if result = 0
1 /2
(CC1=0 and CC0=0)
1)
Jump if result > 0
1 /2
(CC1=1 and CC0=0)
1)
Jump if result < 0
1 /2
(CC1=0 and CC0=1)
Jump if result _ 0 (CC1=1 and 11)/2
CC0=0) or (CC1=0 and
CC0=1)
Jump if result _ 0 (CC1=0 and 2
CC0=0)
Jump if result _ 0 (CC1=1 and 2
CC0=0)
Jump distributor
2
LABEL
Decrement ACCU1-L and

jump if ACCU1-L <> 0
1 word long for jump widths between -128 and +127
2) If jump is not executed
Execution Time in s
CPU 412
0.5/0.6
2)
0.5/0.6
2)
0.6/0.2
2)
0.6/0.2
0.6/0.2
CPU 414
0.5
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
CPU 416
0.4
2)
0.4/0.16
2)
0.4/0.16
2)
0.4/0.16
2)
0.4/0.16
2)
0.4/0.16
2)
0.4/0.16
2)
0.4/0.16
0.6/0.2
0.5/0.2
2)
2)
0.6/0.2
0.5/0.2
2)
2)
0.5/0.6/0.2 0.5/0.2
CPU 417
0.5
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.5/0.2
2)
0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.5/0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.5/0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.5/0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.5/0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.6/0.2
2)
0.5/0.2
2)
0.4/0.16
2)
0.5/0.2
2)
0.8
0.6/0.2
0.7
1)
0.5/0.2
0.56
1)
0.4/0.08
0.7
1)
0.5/0.2
Instructions for the Master Control Relay (MCR)

MCR(
)MCR
MCRA
MCRD
MCR(
)MCR
MCRA
Open an MCR zone.

Save the RLO to the MCR
stack.
Close an MCR zone.
Pop an entry off the MCR
stack.
Activate the MCR
Deactivate the MCR
Open an MCR zone.
Save the RLO to the MCR
stack.
Close an MCR zone.
Pop an entry off the MCR
stack.
Activate the MCR
2)
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
1
1
0.1
0.1
0.1
0.1
0.08
0.08
0.1
0.1
0.1
0.1
0.08
0.1
0.1
0.1
0.08
0.1
1)
S7-400
System Functions
SFC
NO.
SFC
Name
SET_CLK
READ_CLK
SET_RTM
CTRL_RTM
READ_RTM
GADR_LGC
6
7
RD_SINFO
DP_PRAL
EN_MSG
10
DIS_MSG
11
DPSYC_FR
1
2
3
4
5
11
DPSYC_FR
12
D_ACT_DP
12
D_ACT_DP
12
D_ACT_DP
12
D_ACT_DP
12
D_ACT_DP
Function
Set clock
Read clock
Set run-time meter
Start and stop run-time meter
Read run-time meter
Find logical address of a channel
Rack 0
internal DP
Read start information of current OB
Trigger a process interrupt at the DP
master First call
Intermediate call
Enable block-related, symbol-related, and
group status messages.
First call, REQ = 1
Last call
Disable block-related, symbol-related, and
group status messages.
First call, REQ = 1
Last call
Synchronize groups of DP Slaves
First call, internal DP interface,
REQ = 1
Intermediate call, internal DP interface,
1)
BUSY = 1
1)
Last call, internal DP interface, BUSY=0
First call, external DP interface, REQ=1
Intermediate call, external DP interface,
1)
BUSY = 1
Last call, external DP interface,
1)
BUSY= 0
Deactivate and activate DP slaves via
integrated DP interface, MODE = 0
First call
Intermediate call
Last call
First call
Intermediate call
Last call
external DP interface, MODE = 0

Intermediate call
Last call
12
D_ACT_DP
First call
Intermediate call
13
DP_NRMDG
Read slave diagnostic data
First call
Intermediate call
14
DPRD_DAT
Read consistent user data (n bytes)
via integrated DP interface 3 bytes
via external DP interface 3 bytes
1)
n = number of active jobs with the same logic address
Execution Time in
s
CPU
CPU
416
417
CPU
412
CPU
414
249
29
26
23
30
39
CPU
414-H
417-H
(SOLO)
289
29
25
22
29
38
CPU
414-H
417-H
(Redun)
288
54
26
22
58
38
340
40
35
30
41
55
249
29
26
23
30
39
215
23
20
18
23
31
66
54
294
46
38
208
36
30
166
46
38
208
46
39
--
46
39
--
43
176
30
122
24
97
30
122
-128
-232
61
176
44
122
34
97
44
122
39
128
62
232
61
170
44
110
34
90
44
110
39
--
63
--
51 + n*
4
51 + n*
4
94
64 + n*
4
64 + n*
4
117
36 + n*
3
36 +
n* 3
71
50 + n*
3
50 + n*
3
76
28 + n*
2
28 + n*
2
60
39 + n*
2
39 + n*
2
61
36 + n*
3
36 + n*
3
71
50 + n*
3
50 + n*
3
76
--
--
--
--
---
---
--
--
--
--
269
179
142
179
--
--
114
231
378
73
167
268
59
121
202
73
167
268
----
----
113
72
58
72
--
--
119
X
76
X
62
X
76
X
---
---
--
--
X
X
X
X
X
X
X
X
X
X
X
X
----
----
X
300
X
200
X
165
X
200
-210
-290
-83
-56
-45
-56
79
70
79
96
94
86
181
67
62
156
54
50
137
67
62
156
88
76
152
122
99
209
S7-400
329
SFC
NO.
15
17
SFC
Name
DPWR_DAT
Function
CPU
412
CPU
414
1)
57 /
2)
61
1)
67 /
2)
97
1)
62 /
2)
67
1)
150 /
2)
181
305
Write consistent user data (n bytes)

96 /127
88 /94
178 /
2)
209
440
ALARM_SQ
84 /91
2)
1)
2)
1)
2)
1)
1)
Execution Time in
s
CPU
CPU
416
417
1)
45 /
2)
49
1)
53 /
2)
78
1)
50 /
2)
54
1)
130 /
2)
154
240
1)
57 /
2)
61
1)
67 /
2)
97
1)
62 /
2)
67
1)
150 /
2)
181
305
Generate acknowledgeable block-related

messages.
First call, SIG = 0 > 1
Empty call
130
90
72
90
18
ALARM_S
Generate unacknowledgeable
460
310
250
310
block-related messages.
First call, SIG = 0 > 1
Empty call
140
90
75
90
2)
1) without data transmission to the process image
with data transmission to the process image
19
ALARM_SC
20
BLKMOV
21
FILL
22
CREAT_DB
23
24
25
DEL_DB
TEST_DB
COMPRESS
26
UPDAT_PI
27
UPDAT_PO
28
29
30
31
32
33
34
35
36
37
38
SET_TINT
CAN_TINT
ACT_TINT
QRY_TINT
SRT_DINT
CAN_DINT
QRY_DINT
MP_ ALM
MSK_FLT
DMSK_FLT
READ_ERR
39
DIS_IRT
40
41
1)
Acknowledgment status of the last

ALARM_SQ entering state message.
Copy variable
within the work memory
(n = number of bytes to be copied)
Source = Load memory
Set array default variables
within the work memory
(n = length of target variables in bytes)
Create data block
n = DB length [bytes]
Occupy last free DB No. from a field of
100 DBs
Delete data block
Test data block
Compress user memory
First call (trigger)
Intermediate call (active)
Update process image input table (runtime entry for 1 DI 32 in the central rack)
AI 8* 13Bit
Update process image output table (runtime entry for 1 DO 32 in the central rack)
AO 8* 13Bit
Set time-of-day interrupt
Cancel time-of-day interrupt
Activate time-of-day interrupt
Query time-of-day interrupt
Start time-delay interrupt
Cancel time-delay interrupt
Query time-delay interrupt
Trigger multicomputing interrupt
Mask synchronous faults
Demask synchronous faults
Read error register
CPU
414-H
417-H
(SOLO)
1)
72 /
2)
76
1)
88 /
2)
119
1)
2)
77 /83
171 /
2)
201
266
CPU
414-H
417-H
(Redun)
1)
94 /
2)
98
1)
110 /
2)
142
1)
100 /
2)
105
1)
193 /
2)
224
358
90
275
156
365
97
163
1)
85
60
46
60
56
82
60 + n *
0.3
41 + n *
0.13
32 + n *
0.23
41 + n *
0.13
42 + n *
0.17
42 + n *
0.17
1400 +
n* 1.0
60 + n *
0.15
1160 +
n* 0.7
44 + n *
0.13
1100 +
n* 0.7
34 + n *
0.1
1160 +
n * 0.7
44 + n *
0.13
1124 +
n * 1.0
45 + n *
0.12
2065 +
n * 1.98
45 + n *
0.12
142
94
72
94
606
400
320
400
155 + n * 424 + n *
0.1
0.1
2877
13601
122
47
112
81
32
78
64
25
63
81
32
78
179
68
93
625
248
173
32
45
23
35
18
29
23
35
22
67
22
103
70
45
59
35
51
29
59
35
155
54
192
81
66
108
40
73
44
65
41
43
240
30
31
32
55
75
29
53
34
46
30
33
171
22
23
23
48
60
22
41
27
36
23
26
138
17
18
18
55
75
29
53
34
46
30
33
171
22
23
23
122
74
34
51
33
44
36
32
-21
22
23
149
98
34
75
34
44
36
32
-21
23
23
Discard new events

555
535
580
535
731
732
Block all events (MODE = 0)
Block all events of a priority class
70 - 190 50 - 145 40 - 160 50 - 145 42 - 194 42 - 194
(MODE = 1)
Block one event (MODE = 2)
40 - 50
30 - 37
24 - 28
30 - 37
31 - 36
31 - 37
EN_IRT
Stop discarding events
555
535
580
535
736
737
Enable all events (MODE = 0)
Enable all events in a priority class
70 - 190 50 - 145 40 - 160 50 - 145 42 - 197 42 - 197
(MODE = 1)
Enable an event (MODE = 2)
40 - 50
30 - 37
24 - 28
30 - 37
31 - 37
31 - 37
DIS_AIRT
Delay interrupt events
248
166
132
166
165
165
1)
the first time delay is activated
if the delay is already activated
26
19
14
19
18
18
When activating the delay for the first time, the SFC 41 runtime depends on the priority class in which the SFC 41 is called. The
specified runtime refers to the call in OB 1. It decreases while the priority class number increases.
S7-400
SFC
NO.
SFC
Name
42
EN_AIRT
51
RDSYSST
Function
CPU
412
CPU
414
Execution Time in
s
CPU
CPU
416
417
CPU
414-H
417-H
(SOLO)
18
CPU
414-H
417-H
(Redun)
18
Stop delaying interrupt events

26
19
14
19
2)
when canceling the last delay
if other delays are present
435
320
272
320
343
343
43
RE_TRIGR
Retrigger watchdog monitoring
155
104
84
104
118
307
44
REPL_VAL
Transfer substitute value to ACCU1
30
21
16
21
20
20
46
STP
Force CPU into STOP mode
cannot be measured
47
WAIT
Delay program execution
13 - 18
7 - 15
4 - 11
7 - 15
6 - 13
6 - 13
in addition to waiting time
48
SNC_RTCB
Synchronize slave clocks
25
19
14
19
18
41
49
LGC_GADR
Find slot with logical address
55
40
31
40
41
41
50
RD_LGADR
Find all logical addresses of a block
146
101
80
101
104
104
(run-time entry for 1 DI 32 in the central
rack)
When cancelling the last delay, the SFC 42 runtime depends on the priority class in which the SFC 42 is called. The specified runtime
refers to the call in OB 1. It decreases while the priority class number increases.
51
RDSYSST
51
RDSYSST
51
51
51
51
RDSYSST
RDSYSST
RDSYSST
RDSYSST
51
RDSYSST
51
RDSYSST
51
RDSYSST
List of all system status list information

(0000)
List of all system status list information
(0F00)
Module Identification partial list
Display all data records (0011)
Display one data record (0111)
Display header information (0F11)
CPU Characteristics partial list
Save partial list
System Areas partial list
Block Types partial list
Dispaly one data record (0115)
Priority Classes partial list
Status of Module LEDs partial list
Display status of all LEDs (0019)
Display status of one LED (0119)
Interrupt/Error Assignment partial list
Display all data records of one interrupt
class (0121)
Display all assigned interrupts of one
class (0921)
Alternative: n= number of loaded OBs
(0921)
51
RDSYSST
Interrupt/Error Assignment partial list

Display all assigned interrupts (0A21)
618
493
395
493
477
477
140
97
77
97
97
97
224
170
135
170
169
168
175
145
317
125
100
235
100
80
187
125
100
235
123
99
233
122
99
232
190 215
145
185
135 155
100
134
108 123
80
105
135 155
100
134
185
145
220
134
100
145
105
80
120
170
745
196
117
480
425
165 185
142
858
135 - 155 135 - 154

99
134
98
133
134
100
145
134
100
145
133
99
144
93
480
425
117
99
145
117
99
145
117
99
144
118 128
100
740
94 - 102
119 - 128 118 - 127
78
765
118 128
100
740
196 347
153
322
110 250
106
216
110 135
85
175
110 250
106
216
137 - 291 137 - 290
225
206
1225
150
136
1010
120
110
1055
150
136
1010
210 590
195 215
225 640
(225/
375)+
n*34
930 1510
145 410
135 150
155 440
(155/
260)+
n*23
795 1285
115 330
110 120
125 390
(125/
245)+
n*18
835 1390
145 410
135 150
155 440
(155/
260)+
n*23
795 1285
155
107
85
107
98
947
98
947
107
225
106
--
151
136
1298
--1297
145 - 365 144 - 364

135 - 152 135 - 151
155 - 485 155 - 485
(155/
305)+
n*23
1037 1697
(155/
305)+
n*23
1037 1697
108
107
S7-400
331
SFC
NO.
51
SFC
Name
RDSYSST
Function
Interrupt Status partial list

Display all data records of one interrupt
class (0122)
Display all assigned interrupts of one
class (0822)
Alternative: n = number of loaded OBs
51
RDSYSST
51
RDSYSST
51
RDSYSST
51
RDSYSST
51
RDSYSST
51
RDSYSST
Execution Time in
s
CPU
CPU
416
417
CPU
412
CPU
414
225 660
160 490
125 390
160 490
210 225
235 720
(235/
375)+
n*45
158
210
148 158
165 515
(165/
260)+
n*35
110
147
118 128
130 470
(130/
245)+
n*25
87
117
148 158
165 515
(165/
260)+
n*35
110
147
535 +
n*52
145
200
450 +
n*35
100
140
443 +
n*28
80
111
175
205
125
150
CPU
CPU
414-H
414-H
417-H
417-H
(SOLO) (Redun)
157 - 432 160 - 450
148 - 155 148 - 158
165 - 560 165 - 560
(165/
305)+
n*35
44
147
(165/
305)+
n*35
108
147
450 +
n*35
100
140
540 +
n*36
101
139
540 +
n*36
100
138
100
120
125
150
125
157
125
181
235
425
190 225
128 155
102 135
128 155
127 - 168 127 - 167
210 395
190 225
128 305
128 155
102 255
102 135
128 305
128 155
128 - 318 127 - 317
190 390
190 225
190 240
160
145 295
130 160
130 170
112
115 235
102 135
102 145
90
145 295
130 160
130 170
112
142 - 293 141 - 293
Start Information List partial list

All synchronization error start events of
one priority class (0282)
190 220
128 150
102 125
128 150
128 - 156 128 - 155
All start events of one priority class (0382)
210 305
128 225
102 185
128 225
129 - 230 128 - 229

one priority class before processing
(0682)
190 220
128 150
102 125
128 150
128 - 156 128 - 155
All start events of one priority class before

processing (0782)
210 310
145 225
115 180
145 225
143 - 225 142 - 223

one priority class in process (0A82)
190 220
130 150
102 125
130 150
130 - 158 129 - 161
All start events of one priority class in process (0B82)
190 225
130 155
102 130
130 155
130 - 162 130 - 161
160
112
90
112

Status of Priority Classes partial list
All priority classes in process (0223)
(n= number of priority classes)
Operating Mode partial list
Display the last operating mode transition
(0124)
Display the current operating mode
Status Information Communication partial list
Display status information of a
communication unit (0132) INDEX = 5
Status Information Communication partial list
Display status information of a
communication unit (0232) INDEX = 4
Start Information List partial list
All synchronization error start information
of one priority class (0281)
All start information of one priority class
(0381)
of one priority class before processing
(0681)
All start information of one priority class
before processing (0781)
of one priority class in process (0A81)
All start information of one priority class in
process (0B81)
Display one header information (0F81)
127 - 168 127 - 167
129 - 170 128 - 169

129 - 179 129 - 179
112
113
111
112
S7-400
SFC
NO.
51
51
SFC
Name
RDSYSST
RDSYSST
Function
51
RDSYSST
CPU
414
CPU
414-H
417-H
(SOLO)
--
CPU
414-H
417-H
(Redun)
--
660 + n*
22
508 + n* 408 + n*
19
16
508 + n*
19
Display the status information:

of all modules/racks with incorrect type ID
(0191)
570 + n*
70
427 + n* 365 + n*
60
40
405 + n*
24
--
--
of all faulty modules (0291)
580 + n*
138
428 + n* 344 + n*
22
18
428 + n*
22
--
--
of all unavailable modules (0391)
585 + n*
72
430 + n*
60
370 + n
* 40
430 + n*
60
--
--
Display the status information:

of all submodules of the host module in
the specified rack (0991)
354 + n*
30
250 + n* 200 + n*
26
21
250 + n*
26
--
--
centralized
of one module with logical base address
(0C91)
200 315
180
145
180
177
242
315
225
180
225
224
289
200 315
145 240
130 190
145 240
242
305
Module Status Information partial list of a

module (distributed) with a logical base
address (4C91)
intermediate call
--
--
--
--
148
148

address (4C91)
last call
--
--
--
--
167
167
distributed
of one module with logical base address
(0C91)
address (4C91)
first call
distributed
of all modules in the specified distributed
I/O station (0D91)
RDSYSST
CPU
412
Execution Time in
s
CPU
CPU
416
417
Module Status Information partial list

Display the status information of all
inserted modules (n = number of the data
records) (0091)
local
of all modules in the specified rack
(n = number of the DS) (0D91)
51
377 + n*
13
275 + n* 240 + n*
16
10
275 + n
* 16
260 + n * 405 + n *
20
23
330 390
250 300
200 240
250 300
305
408 - 420

Rack/Station Status Information partial
list, local, Display the setpoint status of the
racks 0 (0092)
560
180
435
127
350
100
435
127
-130
-154
distributed, Display the setpoint status of

distributed I/O system 1 (0092)
900
725
585
725
712
743
local, Display the actual status of the

racks 0 (0292)
180
127
103
127
131
155
distributed, Display the actual status of

distributed I/O system 1 (0292)
940
745
600
745
725
757
160
195 525
113
138 410
90
110 330
113
138 410

Diagnostic Buffer partial list
Display all available current operating
mode event information (max. 23) (00A0)
Display the n newest entries (n = 1-23)
(01A0)
Display the standard OB start information
(04A0). Max value of -04A0 is calculated
195 + n*
14.5
195 1270
138 + n* 110 + n*
12
9.5
138 110 1530
1095
113
113
140 - 412 140 - 412
138 + n* 140 + n*
12
12
138 140 1530
1540
140 + n*
12
140 1540
S7-400
333
SFC
NO.
SFC
Name
51
51
Function
CPU
412
CPU
414
138 1530
CPU
414-H
417-H
(SOLO)
140 1540
CPU
414-H
417-H
(Redun)
140 1540
195 1270
138 1530
110 1095
167
--
90
--
114
114
Display header information (0FA0)
167
--
90
--
114
114
Diagnostic Data DS 0, partial list

Display via logical address (00B1)
local
406
286
233
286
300
360
distributed
First call
392
270
217
270
278
356
distributed
Intermediate call, REQ = 0
215
150
120
150
153
152
distributed
Last call
Diagnostic Data DS 1 partial list
Display via graphical address (00B2)
Display a 16-byte long DS 1
Diagnostic Data DS 1 partial list
Display via logical address (00B3)
Display a 16-byte long DS 1 local
405
165
132
165
170
169
408
300
250
300
313
375
447
324
268
324
340
402
395
270
218
270
272
356
Display all communication information

(05A0)
Display all object management system information (06A0)
Display all test and startup information
(07A0)
Display all operating mode information
(08A0)
Display all asynchronous error start information (09A0)
Display all synchronous error start information (0AA0)
Display all STOP/cancel/operating mode
transition information (0BA0)
Display all fault-tolerant/failsafe information (0CA0)
Display all diagnostic information (0DA0)
Display all user information (0EA0)
Display header information (0FA0)
RDSYSST
51
RDSYSST
51
RDSYSST
distributed First call
51
RDSYSST
distributed Intermediate call
218
150
120
150
153
153
distributed Last call
257
178
142
178
182
182
Diagnostic Data DP Slave partial list

Display via configured diagnostic address
(00B4)
First call
385
266
213
266
272
351
--
--
115
--
149
148
Last call (6 - 240 bytes)

Write user entry in diagnostic buffer
write with message
without message
246
186
170
128
135
102
170
128
174
75
173
100
107
75
60
75
74
98
Read dynamic parameters

local AI 8*13 bits
180
125
95
125
126
153
distributed AI 8*12 bits (DS1 = 14 bytes)
200
135
105
135
121
121
Write dynamic parameters

local AI 8*13 bits
distributed
First call AI 8*12 bits (14 - 240 bytes)
485
345
280
345
360
418
370
260
210
260
268
347
distributed
Intermediate/last call, REQ = 0
175
115
90
115
122
122

52
WR_USMSG
54
RD_DPARAM
55
WR_PARM
Execution Time in
s
CPU
CPU
416
417
S7-400
SFC
NO.
56
57
58
59
SFC
Name
WR_DPARM
PARM_MOD
WR_REC
RD_REC
Function
Write predefined dynamic parameters

AI 8*13 bits
local
distributed
First call AI 8*12 bits (2 - 240 bytes)
Intermediate/last call
Assign module parameters
local
Module/DS number/DS lengths in bytes
AI 8*13 bits
distributed
AO 8*12 bits
First call (16 - 240 bytes)
distributed
Intermediate/last call
Write parameter data record
local (n = number of bytes)
First call, integrated DP interface module
(n = number of bytes)
integrated DP interface module
Last call, integrated DP interface module
GD_SND
61
GD_RCV
62
CONTROL
64
65
TIME_TCK
X_SEND
66
X_RCV
CPU
414
336
CPU
414-H
417-H
(SOLO)
353
CPU
414-H
417-H
(Redun)
411
445
336
280
300
205
165
205
217
296
145
770
100
580
80
490
100
580
106
609
106
695
300
205
165
205
215
295
145
100
80
100
104
104
390 + n* 267 + n* 217 + n* 267 + n* 282 + n* 311 + n*

2.87
2.71
2.52
2.71
2.68
2.71
334 + n* 228 + n* 182 + n* 228 + n* 222 + n* 276 + n*
0.42
0.35
0.30
0.35
0.39
0.32
138
90
70
90
94
94
138
332 + n*
0.32
139
Read data record

local (n = number of bytes)
First call, integrated DP interface module
390 + n*
3.13
322
Last call, integrated DP interface module

Execution Time in
s
CPU
CPU
416
417
CPU
412
First call, external DP interface module

external DP interface module
Last call, external DP interface module

integrated DP interface module
60
140
138
198 + n*
0.35
90
70
215 + n* 171 + n*
0.26
0.23
90
72
91
72
267 + n* 218 + n*
2.90
2.71
217
172
90
70
132 + n* 106 + n*
0.33
0.27
90
95
215 + n* 208 + n*
0.26
0.26
90
95
91
95
267 + n* 282 + n*
2.90
2.97
217
212
90
95
132 + n* 138 + n*
0.33
0.33
94
208 + n*
0.29
94
95
342 + n*
3.13
264
94
138 + n*
0.33
First call, external DP interface module
304
204
163
204
198
197

external DP interface module
139
91
72
91
95
94
Last call, external DP interface module

Send GD packet
1 byte
32 bytes
Receive GD package
(1 - 32 Byte)
Check status of the connection belonging
to a local communication-SFB-instance
200 + n*
0.33
295
132 + n* 105 + n*
0.2
0.2
215
175
132 + n* 136 + n*
0.2
0.33
215
--
136 + n*
0.27
--
910
145
640
105
515
85
640
105
---
---
116
87
69
87
107
136
24
860 910
19
710 740
15
765 795
19
710 740
19
--
47
--
590 635
400 430
320 345
400 430
--
--
Intermediate call
(1-76 bytes)
180
130
100
130
--
--
Last call, BUSY = 0

Receive data from external partner
Test reception (1-76 bytes)
Read data
(1-76 bytes)
285
92
195
65
155
55
195
65
---
---
275 315
190 220
150 175
190 220
--
--
Display millisecond timer

Transmit data to external partner
First call, establish a connection
(1 - 76 bytes) REQ = 1
First call, connection present
(1-76 bytes)
S7-400
335
SFC
NO.
67
SFC
Name
X_GET
Function
CPU
412
CPU
414
645
CPU
414-H
417-H
(SOLO)
--
CPU
414-H
417-H
(Redun)
--
Read data from external partner

(1-76 bytes) REQ = 1
760
645
715

(1-76 bytes)
490
335
265
335
--
--
Intermediate call
(1-76 bytes)
195
135
110
135
--
--
450 490
880 925
310 340
725 755
245 270
780 810
310 340
725 755
--
--
--
--
610 655
415 445
330 360
415 445
--
--
Intermediate call
(1-76 bytes)
195
135
110
135
--
--
Last call, BUSY = 0
300
205
162
205
--
--
Abort connection to external partner

First call, REQ = 1
Intermediate call
220
160
125
160
--
--
Last call BUSY = 0

68
X_PUT
Write data to external partner

(1-76 bytes)
69
72
73
74
X_ABORT
Last call, BUSY = 0

Read data from internal partner
I_GET
I_PUT
I_ABORT
1)
79
SET
80
RSET
81
UBLKMOV
90
H_CTRL
100
SET_CLKS
1)
1)
Execution Time in
s
CPU
CPU
416
417
125
90
70
90
--
--
365
815
375
680
75 - 500
745
375
680
---
---
First call, connection present (1-76 bytes)
505
345
275
345
--
--
Intermediate call (1-76 bytes)
205
145
115
145
--
--
Last call, BUSY = 0
460 505
315 345
250 275
315 345
--
--
Write data to internal partner

(1-76 bytes)
Intermediate call (1-76 bytes)
Last call, BUSY = 0
690 980
430 800
340 840
430 800
--
--
625 665
205
310
425 455
145
215
340 365
115
170
425 455
145
215
--
--
---
---
225
160
125
160
--
--
125
365
90
380
75
70 / 503
90
380
---
---
43 +
n * 0.39
43 +
n * 0.39
62 + n*
0.30
--
28 +
n * 0.32
28 +
n * 0.32
44 + n*
0.17
--
23 +
n * 0.26
23 +
n * 0.26
33 + n*
0.17
--
28 +
n * 0.32
28 +
n * 0.32
44 + n*
0.17
--
53 +
n * 1.35
53 +
n * 1.35
43 + n*
0.17
19 - 21
80 +
n * 1.32
80 +
n * 1.32
42 + n*
0.17
19 - 21
370
263
227
263
439
1169
125
375
84
266
67
232
84
266
192
442
403
1167
Abort connection to internal partner

First call, REQ = 1
Intermediate call
Last call, without / with connection
BUSY = 0
Set bit array in I/O area
n = number of bits to set at 1
Delete bit array in I/O area
n = number of bits to set at 0
Copy variable without interruption
n = number of bytes to copy
Influence processes involving
fault-tolerant systems
Set time-of-day and clock status
MODE = 1
MODE = 2
MODE = 3
Measured with I/O modules of the type Binary Simulator C79459-A1002-A1, Release 1 in the central rack
S7-400
SFC
NO.
105
0)
SFC
Name
READ_SI
Function
CPU
412
CPU
414
Execution Time in
s
CPU
CPU
416
417
Read dynamically assigned system

resources MODE = 0
MODE = 1
176 117 94 117 0)

0)
0)
0)
1807
3574
2859
3574
204 138 110 138 1)
1)
1)
1)
2098
4128
3302
4128
MODE = 2
205 140 111 140 1)
1)
1)
1)
1478
2868
2294
2868
MODE = 3
206 140 111 140 2)
2)
2)
2)
2152
4129
3303
4129
106 DEL_SI
Enable dynamically assigned system
176 125 97 125 1)
1)
1)
1)
resources MODE = 1
1289
2666
2131
2666
MODE = 2
180 127 99 127 1)
1)
1)
1)
1272
2580
2061
2580
MODE = 3
177 125 98 125 2)
2)
2)
2)
1350
2705
2162
2705
Depending on the size of the SYS_INST target area and on the number of the system resources to be read
CPU
414-H
417-H
(SOLO)
117 0)
3205
136 1)
3802
137 1)
2901
137 2)
3802
145 1)
6954
147 1)
2668
145 2)
6974
CPU
414-H
417-H
(Redun)
117 0)
3206
303 1)
3971
304 1)
3069
305 2)
3970
507 1)
23875
510 1)
3033
507 2)
23906
1)
Depending on the number of active messages (assigned system resources)
2)
Depending on the number of active messages (assigned system resources) and on the number of assigned instances with the desired
CMP_ID.
107
108
ALARM_DQ
ALARM_D
Acknowledgeable block-related messages

create first call, SIG = 0 -> 1
Call (without message)
497
336
267
336
349
566
145
98
78
98
101
157
Not achnowledgeable block-related

messages create first call, SIG = 0 -> 1
Call (without message)
499
337
266
337
350
548
146
98
78
98
101
156
S7-400
337
System Function Blocks
SFB
NO.
0
1
2
3
4
5
8
12
SFB
Name
CTU
CTD
CTUD
TP
TON
TOF
USEND
URCV
BSEND
Function
CPU
412
CPU
414
26
25
29
34
34
36
473 737
16
17
19
23
23
24
318 509
13
13
15
18
18
19
253 407
JOB checked
159
107
JOB finished (DONE = 1)
152
Receive data without coordination

(one receive parameter supplied)
JOB activated
JOB checked
Count up
Count down
Count up and down
Generate pulse
Generate on-delay
Generate off-delay
Send data without coordination
(one send parameter supplied)
JOB activated (1 - 440 bytes)
JOB finished
(NDR = 1; 1 - 440 bytes)
Send data block by block
JOB checked
13
14
BRCV
GET
Execution Time in
s
CPU
CPU
416
417
16
17
19
23
23
24
317 509
CPU
414-H
417-H
(SOLO)
17
17
19
24
24
20
330 436
CPU
414-H
417-H
(Redun)
16
17
19
52
52
53
425 542
86
108
115
145
103
82
104
107
137
137
93
74
94
100
130
137
93
74
94
100
130
345 610
386
232 421
258
186 337
207
233 421
258
243 363
264
314 435
323
171
115
92
116
122
152
165
110
88
111
115
145
Receive data block by block

203
138
110
139
145
175
JOB checked
161
110
88
111
117
147
JOB finished
162
109
87
110
113
143
Read data from remote CPU

(one area specified)
JOB activated
336
227
183
228
227
297
JOB checked
JOB finished (NDR = 1; 1 - 450 bytes)
161
109
87
110
116
146
344 626
498 748
161
231 431
337 513
108
185 345
269 410
87
232 432
337 515
109
243 369
349 458
116
314 441
443 552
146
15
PUT
Write data to remote CPU

JOB checked
154
104
83
105
108
138
16
PRINT
Send data to a printer

JOB activated, REQ = 1
JOB checked
513 757
160
338 516
107
271 414
86
339 518
108
354 462
115
449 545
145
19
START
20
STOP
JOB finished, DONE = 1
153
103
82
104
107
137
Start remote device

JOB checked
497
333
265
333
339
408
169
114
91
115
121
151
164
110
88
111
115
146
Stop remote device

JOB checked
472
314
251
314
322
384
169
114
91
115
121
151
164
110
88
111
115
146
S7-400
SFB
NO.
21
22
23
32
33
34
35
SFB
Name
RESUME
STATUS
USTATUS
DRUM
ALARM
ALARM_8
ALARM_8P
Function
37
52
52
NOTIFY
AR_SEND
RDREC
RDREC
Execution Time in
s
CPU
CPU
416
417
CPU
412
CPU
414
332
CPU
414-H
417-H
(SOLO)
339
CPU
414-H
417-H
(Redun)
399
Restart remote device

JOB checked
496
334
265
169
114
91
115
121
151
164
Query status of remote partner

JOB checked
268
110
88
111
115
145
183
146
184
188
258
161
108
87
109
116
146
JOB finished, NDR = 1
604
404
323
404
415
486
Receive status of remote device without

coordination
JOB activated, NDR = 1
JOB checked
137
93
74
94
100
131
137
93
74
94
100
130
604
52
581 843
404
33
386 587
323
26
307 470
404
33
385 589
415
35
392 518
486
62
527 652
JOB checked
205
136
109
137
141
171

Generate block-related message
without accompanying values for 8
signals JOB activated, SIG = 0> 1
(1 - 420 bytes)
JOB checked
207
416
137
278
110
222
138
279
136
278
166
372
203
135
108
136
140
170
206
137
109
138
135
166
580 842
384 587
308 469
385 597
392 517
526 651
204
136
108
137
140
170
207
561 823
137
373 580
110
301 462
138
379 578
135
384 510
166
519 644
JOB checked
186
125
100
126
133
163

Send archive data
(1 - 3000 bytes)
JOB checked
191
388
128
258
102
208
129
258
130
265
160
328
173
116
92
116
123
155
167
111
88
112
115
147
Read data record from a DP slave via

integrated DP interface,
First call (2-16 bytes)
Intermediate call
341
221
177
221
228
269
173
111
89
111
117
114
JOB finished
Implement sequencer
Generate block-related message with
acknowledgment
JOB activated, SIG = 0> 1
(1 - 420 bytes)
Generate block-related message with

accompanying values for 8 signals
(1 - 420 bytes)
JOB checked
36

Generate block-related message
without acknowledgment
(1 - 420 bytes)
Last call
236
157
127
157
164
161
Read data record from a DP slave via

external DP interface,
Intermediate call
323
211
170
211
213
210
174
112
90
112
117
114
Last call
238
154
124
154
161
158
S7-400
339
SFB
NO.
53
53
SFB
Name
WRREC
WRREC
54
RALRM
54
RALRM
Function
CPU
414
Write data record in a DP slalve via

integrated DP interface,
Intermediate call
354
234
170
110
88
110
116
112
Last call
171
110
89
110
116
113
Write data record in a DP slave via

external DP interface,
Intermediate call
339
224
180
224
226
223
170
110
89
110
116
113
Last call
172
111
89
111
117
113
Receive interrupt from a DP slave

Runtime measurement for
non-I/O-dependent OBs, MODE = 1,
OB 1
Runtime measurement at integrated DP
interface, MODE = 1,
OB 40, OB 83, OB 86
OB 55 to OB 57, OB 82
133
81
70
81
83
83
250
164
135
164
245
245
257
171
140
171
251
251
--
--
--
--
242
242
429
290
234
290
458
458
704
499
413
499
747
747
--
--
--
--
460
460
215
138
111
138
143
143
619
472
414
472
567
567
OB 70
54
RALRM

Runtime measurement at external DP
interface, MODE = 1,
OB 40, OB 83, OB 86
OB 55 to OB 57, OB 82
OB 70
54
RALRM
Execution Time in
s
CPU
CPU
416
417
CPU
412

Runtime measurement at central I/O,
MODE = 1,
OB 40, OB 82, OB 83, OB 86
OB 55 to OB 57
187
234
CPU
414-H
417-H
(SOLO)
241
CPU
414-H
417-H
(Redun)
281
5
f Z ] d
Sysytem Blocks
f Z ] d
342
List of SFCs
No.
Short Name
Function
SFC 0
SET_CLK
Set System Clock
SFC 1
READ_CLK
Read System Clock
SFC 2
SET_RTM
Set Run-time Meter
SFC 3
CTRL_RTM
Start/Stop Run-time Meter
SFC 4
READ_RTM
Read Run-time Meter
SFC 5
GADR_LGC
Query Logical Address of a Channel
SFC 6
RD_SINFO
Read OB Start Information
SFC 7
DP_PRAL
Trigger a Hardware Interrupt on the DP Master
SFC 9
EN_MSG
Enable Block-Related, Symbol-Related and Group Status Messages
SFC 10
DIS_MSG
Disable Block-Related, Symbol-Related and Group Status Messages
SFC 11
DPSYC_FR
Synchronize Groups of DP Slaves
SFC 12
D_ACT_DP
Deactivation and activation of DP slaves
SFC 13
DPNRM_DG
Read Diagnostic Data of a DP Slave (Slave Diagnostics)
SFC 14
DPRD_DAT
Read Consistent Data of a Standard DP Slave
SFC 15
DPWR_DAT
Write Consistent Data to a DP Standard Slave
SFC 17
ALARM_SQ
Generate Acknowledgeable Block-Related Messages
SFC 18
ALARM_S
Generate Permanently Acknowledged Block-Related Messages
SFC 19
ALARM_SC
Query the Acknowledgment Status of the last ALARM_SQ Entering State Message
SFC 20
BLKMOV
Copy Variables
SFC 21
FILL
Initialize a Memory Area
SFC 22
CREAT_DB
Create Data Block
SFC 23
DEL_DB
Delete Data Block
SFC 24
TEST_DB
Test Data Block
SFC 25
COMPRESS
Compress the User Memory
SFC 26
UPDAT_PI
Update the Process Image Update Table
SFC 27
UPDAT_PO
Update the Process Image Output Table
SFC 28
SET_TINT
Set Time-of-Day Interrupt
SFC 29
CAN_TINT
Cancel Time-of-Day Interrupt
SFC 30
ACT_TINT
Activate Time-of-Day Interrupt
SFC 31
QRY_TINT
Query Time-of-Day Interrupt
SFC 32
SRT_DINT
Start Time-Delay Interrupt
SFC 33
CAN_DINT
SFC 34
QRY_DINT
Cancel Time-Delay Interrupt

Query Time-Delay Interrupt
SFC 35
MP_ALM
Trigger Multicomputing Interrupt
SFC 36
MSK_FLT
Mask Synchronous Errors
SFC 37
DMSK_FLT
Unmask Synchronous Errors
SFC 38
READ_ERR
Read Error Register
SFC 39
DIS_IRT
Disable New Interrupts and Asynchronous Errors
SFC 40
EN_IRT
Enable New Interrupts and Asynchronous Errors
SFC 41
DIS_AIRT
Delay Higher Priority Interrupts and Asynchronous Errors
SFC 42
SFC 43
EN_AIRT
RE_TRIGR
Enable Higher Priority Interrupts and Asynchronous Errors

Re-trigger Cycle Time Monitoring
f Z ] d
No.
Short Name
SFC 44
REPL_VAL
Function
Transfer Substitute Value to Accumulator 1
SFC 46
STP
Change the CPU to STOP
SFC 47
WAIT
Delay Execution of the User Program
SFC 48
SNC_RTCB
Synchronize Slave Clocks
SFC 49
LGC_GADR
Query the Module Slot Belonging to a Logical Address
SFC 50
RD_LGADR
Query all Logical Addresses of a Module
SFC 51
RDSYSST
Read a System Status List or Partial List
SFC 52
WR_USMSG
Write a User-Defined Diagnostic Event to the Diagnostic Buffer
SFC 54
RD_PARM
Read Defined Parameters
SFC 55
WR_PARM
Write Dynamic Parameters
SFC 56
WR_DPARM
Write Default Parameters
SFC 57
PARM_MOD
Assign Parameters to a Module
SFC 58
WR_REC
Write a Data Record
SFC 59
RD_REC
Read a Data Record
SFC 60
GD_SND
Send a GD Packet
SFC 61
GD_RCV
Fetch a Received GD Packet
SFC 62
CONTROL
Query the Status of a Connection Belonging to a Communication SFB Instance
SFC 63 *
AB_CALL
Assembly Code Block
SFC 64
TIME_TCK
Read the System Time
SFC 65
X_SEND
Send Data to a Communication Partner outside the Local S7 Station
SFC 66
X_RCV
Receive Data from a Communication Partner outside the Local S7 Station
SFC 67
X_GET
Read Data from a Communication Partner outside the Local S7 Station
SFC 68
X_PUT
Write Data to a Communication Partner outside the Local S7 Station
SFC 69
X_ABORT
Abort an Existing Connection to a Communication Partner outside the Local S7 Station
SFC 72
I_GET
Read Data from a Communication Partner within the Local S7 Station
SFC 73
I_PUT
Write Data to a Communication Partner within the Local S7 Station
SFC 74
I_ABORT
Abort an Existing Connection to a Communication Partner within the Local S7 Station
SFC 78
OB_RT
Determine OB program runtime
SFC 79
SET
Set a Range of Outputs
SFC 80
RSET
Reset a Range of Outputs
SFC 81
UBLKMOV
Uninterruptible Block Move
SFC 82
CREA_DBL
Generating a Data Block in the Load Memory
SFC 83
READ_DBL
Reading from a Data Block in Load Memory
SFC 84
WRIT_DBL
Writing from a Data Block in Load Memory
SFC 87
C_DIAG
Diagnosis of the Actual Connection Status
SFC 90
H_CTRL
Control Operation in H Systems
SFC 100
SET_CLKS
Setting the Time-of-Day and the TOD Status
SFC 101
RTM
Handling runtime meters
SFC 102
RD_DPARA
Redefined Parameters
SFC 103
DP_TOPOL
Identifying the bus topology in a DP master system
SFC 104
CiR
Controlling CiR
SFC 105
READ_SI
Reading Dynamic System Resources
SFC 106
DEL_SI
Deleting Dynamic System Resources
SFC 107
ALARM_DQ
Generating Always Acknowledgeable and Block-Related Messages
SFC 108
ALARM_D
Generating Always Acknowledgeable and Block-Related Messages
SFC 126
SYNC_PI
Update process image partition input table in synchronous cycle
SFC 127
SYNC_PO
Update process image partition output table in synchronous cycle
* SFC 63 "AB_CALL" only exists for CPU 614. For a detailed description, refer to the corresponding Manual
f Z ] d
List of SFBs
No.
SFB 0
SFB 1
SFB 2
SFB 3
SFB 4
SFB 5
SFB 8
SFB 9
SFB 12
SFB 13
SFB 14
SFB 15
SFB 16
SFB 19
SFB 20
SFB 21
SFB 22
SFB 23
SFB 29 *
SFB 30 *
SFB 31
SFB 32
SFB 33
SFB 34
SFB 35
SFB 36
SFB 37
SFB 38 *
SFB 39 *
SFB 41
SFB 42
SFB 43
SFB 44
SFB 46
SFB 47
SFB 48
SFB 49
SFB 52
Short Name
CTU
CTD
CTUD
TP
TON
TOF
USEND
URCV
BSEND
BRCV
GET
PUT
PRINT
START
STOP
RESUME
STATUS
USTATUS
HS_COUNT
FREQ_MES
NOTIFY_8P
DRUM
ALARM
ALARM_8
ALARM_8P
NOTIFY
AR_SEND
HSC_A_B
POS
CONT_C 1)
CONT_S 1)
PULSEGEN 1)
ANALOG 2)
DIGITAL 2)
COUNT 2)
FREQUENC 2)
PULSE 2)
RDREC
Function
Count Up
Count Down
Count Up/Down
Generate a Pulse
Generate an On Delay
Generate an Off Delay
Uncoordinated Sending of Data
Uncoordinated Receiving of Data
Sending Segmented Data
Receiving Segmented Data
Read Data from a Remote CPU
Write Data to a Remote CPU
Send Data to Printer
Initiate a Warm or Cold Restart on a Remote Device
Changing a Remote Device to the STOP State
Initiate a Hot Restart on a Remote Device
Query the Status of a Remote Partner
Receive the Status of a Remote Device
Counter (high-speed counter, integrated function)
Frequency Meter (frequency meter, integrated function
Generating block related messages without acknowledgement indication
Implement a Sequencer
Generate Block-Related Messages with Acknowledgment Display
Generate Block-Related Messages without Values for 8 Signals
Generate Block-Related Messages with Values for 8 Signals
Generate Block-Related Messages without Acknowledgment Display
Send Archive Data
Counter A/B (integrated function)
Position (integrated function)
Continuous Control
Step Control
Pulse Generation
Positioning with Analog Output
Positioning with Digital Output
Controlling the Counter
Controlling the Frequency Measurement
Controlling Pulse Width Modulation
Reading a Data Record from a DP Slave
SFB 53
SFB 54
SFB 60
SFB 61
SFB 62
SFB 63
SFB 64
SFB 65
SFB 75
WRREC
RALRM
2)
SEND_PTP
2)
RCV_PTP
2)
RES_RECV
2)
SEND_RK
2)
FETCH_RK
2)
SERVE_RK
SALRM
Writing a Data Record in a DP Slave

Receiving an Interrupt from a DP Slave
Sending Data (ASCII, 3964(R))
Receiving Data (ASCII, 3964(R))
Deleting the Receive Buffer (ASCII, 3964(R))
Sending Data (RK 512)
Fetching Data (RK 512)
Receiving and Providing Data (RK 512)
Send interrupt to DP master
SFB 29 "HS_COUNT" and SFB 30 "FREQ_MES" only exist on the CPU 312 IFM and
CPU 314 IFM. SFBs 38 "HSC_A_B" and 39 "POS" only exist on the CPU 314 IFM
1) SFBs 41 "CONT_C," 42 "CONT_S" and 43 "PULSEGEN" only exist on the CPU 314 IFM
2) SFBs 44 to 49 and 60 to 65 only exist on the S7-300C CPUs
6

S5 S7
S5 S7 ] Zf{ d cYf{ Z
346
S5 S7
Data Class
Data Types in S5
Data Types in S7
Elementary data types
BOOL,
BYTE,
WORD,
DWORD,
Integer,
Double integer,
Floating point,
Time value,
ASCII character
BOOL,
BYTE,
WORD,
DWORD,
INT,
DINT,
REAL,
S5TIME,
TIME, DATE; TIME_OF_DAY,
CHAR
Complex data types
DATE_AND_TIME,
STRING,
ARRAY,
STRUCT
Parameter types
Timers,
Counters,
Blocks
TIMER,
COUNTER,
BLOCK_FC, BLOCK_FB,
BLOCK_DB, BLOCK_SDB,
POINTER,
ANY
S5 S7
Formats in S5
Example
Formats in S7
Example
KB
L KB 10
K8
L B#16# A
KF
L KF 10
K16
L 10
KH
L KH FFFF
16#
L 16# FFFF
KM
L KM 1111111111111111
2#
L 2# 11111111_11111111
KY
L KY 10,12
B#
L B# (10,12)
KT
L KT 10.0
S5TIME# (S5T#)
L S5TIME# 100ms
KC
L KC 30
C#
L C#30
DH
L DH FFFF FFFF
16#
L DW#16# FFFF_FFFF
KS
L KS WW
xx
L WW
KG
L KG +234 +09
Floating Point
L +2.34 E+08
S7 S5 OB
Function
S5
S7
Main program
Free cycle
OB1
OB1
Interrupts
Time-delay
(delayed)
interrupt
OB6
OB20 to OB23
Time-of-day
(clock-controlled)
interrupt
OB9
OB10 to OB17
Hardware interrupts
OB2 to OB5
OB40 to OB47
Process interrupts
OB2 to OB9
Replaced by hardware
interrupts
Cyclic (timed)
interrupts
OB10 to OB18
OB30 to OB38
Multicomputing
interrupt
OB60
Manual complete
(cold)
restart
OB100
OB21 (S5-115U)
OB20 (S5-135U)
OB100
Manual (warm)
restart
OB21 (from S5135U)
OB101
Automatic (warm)
restart
OB22
OB101
Errors
Error
OB19 to OB35
Other
Processing in STOP
mode
OB39
OB121, OB122, OB80

to OB87
Omitted
Background
processing
OB90
Startup
348
S5 S7
Instruction Type
Accumulator
instructions
S5
TAK, ENT, I, D, ADDBN,
ADDKF, ADDDH
S7
TAK, ENT, INC, DEC, +,
Address register
instructions /
Register instructions
MA1, MBR, ABR,MAS, MAB,

MSB,MSA, MBA, MBS;
TSG, LRB, LRW,LRD, TRB,
TRW,TRD
Bit logic instructions
A, AN, O, ON, A(,

O(, ), O, S, R, RB,RD=
New in S7:
CAW, CAD, PUSH,POP, LEAVE
New in S7:
LAR1, LAR2,
TAR1, TAR2,
+AR1, +AR2,
CAR
A, AN, O, ON, A(,
O(, ), O, S, R, =
TB, TBN, SU, RU
SET; A, SET; AN,SET; S, SET; R
Timer instructions
SP, SE, SD,SS/SSU, SF/SFD,

FR, SEC
New in S7:
X, XN, X(, XN(,FP, FN, NOT, SET,CLR,
SAVE
SP, SE, SD, SS, SF,
FR, S T
Counter instructions
CU/SSU, CD/SFD,FR, SEC
CU, CD, FR, S C
Load and transfer

instructions
L, LD, LW, LDW, TL PB,L QB

L PW, L QW, T PB,
T QB, T PW, T QW
L, LC, T
L PIB, L PIW,
T PQB, T PQW
LY GB / GW / GD /CB / CW /
CD,LW GW / GD / CW /
CD,TY GB / GW / GD /
CB / CW / CD,TW GW / GD /
CW /CD
+F, F, xF, :F, +D,D
Integer math
instructions
Floating-point math
instructions
Comparison
instructions
Conversion
instructions
+I, I, *I, /I, +D, D, *D, /D
+G, G, xG, :G
New in S7:
MOD
+R, R, *R, /R
!=F, ><F, >F, <F,

>=F, <=F, !=D,
><D, D, <D, >=D,
<=D, !=G, ><G,
>G, <G, >=G, <=G
CFW, CSW, CSD,DEF, DED,
DUF, DUD, GFD, FDG
==I, <>I, >I, <I;

>=I, <=I, ==D,
<>D, >D, <D, >=D,
<=D, ==R, <>R,
>R, <R, >=R, <=R
INVI, NEGI, NEGD, BTI, BTD,
DTB, ITB, RND, DTR
New in S7:
ITD, RND+, RND, TRUNC, INVD, NEGR
S5 S7
Instruction Type
Word logic
instructions
Shift and rotate

instructions
Data block
instructions
Logic control
instructions, jump
Block instructions
Command output
instructions/ Master
control relay
instructions
S5
AW, OW, XOW
AW, OW, XOW
SLW, SLD, SRW,

SRD, SVW, SVD,
RLD, RRD
New in S7:
AD, OD, XOD
SLW, SLD, SRW,
SRD, SSI, SSD,
RLD, RRD
G, CX
New in S7:
RLDA, RRDA
OPN
G, GX
SFC22
JU, JC, JN, JZ, JP,

JM, JO, JOS, JUR
New in S7:
CDB
L DBLG, L DBNO,L DILG, L DINO
JU, JC, JN, JZ, JP,
JM, JO, JOS
JU, JC, DOU,

DOC, BE, BEU,BEC
BAS, BAF
S7
New in S7:
JCN, JCB, JNB,JBI, JNBI, JMZ,
JPZ, JUO, LOOP, JL
CALL, BE, BEU,
BEC
New in S7:
MCRA, MCRD,
MCR(, )MCR
Stop commands
STP, STS, STW
SFC46
Processing functions
DO <Formal parameter>
DO FW, DO DW
DO RS
LIR, TIR, LDI, TDI
Memory-indirect addressing
Area-crossing register-indirect addressing
TNB, TNW, TXB, TXW

LIM, SIM, IAE,
RAE, IA, RA
SFC20
SFC39 to 42
Page commands
ACR, TSC, TSG
Math functions
ABS, COS, SIN,

TAN, ACOS,
ASIN, ATAN, EXP, LN
Null instructions
BLD xxx
NOP 0, NOP 1
BLD xxx
NOP 0, NOP 1
Absolute memory
addressing
Block transfers
Interrupt commands
mY ]Z
351
Working with Step7
Siemens
x
Programming with Step7
Siemens
Configuring Hardware with Step7
Siemens
x
From S5 to S7
Siemens
Statement List For S7-300,S7-400
Siemens
x
Ladder Logic for S7-300 and S7-400
Siemens
x
Function Block Diagram for S7-300 and S7-400
Siemens
x
System and Standard Functions for S7-300 , S7-400
Siemens
S7-300 Hardware and Installation
Siemens
x
S7-300 Module Specification
Siemens
S7-400 Hardware and Installation
Siemens
x
S7-400 Module Specification
Siemens
x
S7-400 Instruction List
Siemens
x
Simatic S7 Supplement to Manual
Siemens
S7-300 Quick Start
Siemens
x
FAQ
x
PLC History
x
General Introduction into IEC 61131 all parts
www.ad.siemens.de
www.plcs.net
PLC
Step7
www.plcopen.org

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Simatic Manager On-Line

PLC (International Elctro-technical Commission) IEC

( ... HMI ) PLC

(Equipment Requirements and Tests)

FunctionBlock Diagram (FBD)

LOGO! Logic Modules

. Operator Control S7-300 C7

2004 Step7 V5.3 Step7

. Step7V5.1 2002 Step7 V5.2

. ( Configuration in Run) CiR

(V5.2 V5.1 ) Step7 Step7

. FBD STL LAD

STEP 7 PLC STEP 5

Start AuthorzW Authorization

Move Authorization Tab

. PLC MPI MPI

C7 S7-400 ( CPU315) S7-300

. S7-400 ( CPU314) S7-300 PLC ( Diagnostic ) : S7 PDIAG

Standard PID Control

. C7 S7-400 ( CPU31C) S7-300

. LAD , FBD , STL

. . Simatic Manager Wizard Cancel

Insert > Program Insert > Station

: Insert > Station .

. H 400 300 Station

Properties Rename Cut Paste Copy

Toolbar Simatic Manager

Station 300 Hwconfig

Central Processing Unit

simatic Manager Station 300 -

I/O . Expansion Central

Drag Rail Hwconfig

Digital Input SM-300

CPU315 ) 300 CPU . S7-300

(6ES7 331-7KF01-0AB0 ) AI 8x12 Bit

. Input Low Limit High Limit

. Reaction to Open Thermocouple AI 8xTC

Resolution . Integration time AI

Group Diagnostics Diagnostic Interrupt

CPU 300 CPU

4096 byte Input

CPU . PII Process Image Input CPU

Step7 PLC > Clear / Reset : Step7

. (400 300 ) S7 CPU

. (Download) CPU : Load Memory

. Load Memory CPU (Micro Memory Card)

MMC . Load Memory FEPROM Card

. STOP CPU STOP PG

: STARTUP STOP CPU

(PLC Step7 ) STOP

EXIT HOLD Breakpoint

(PLC Step7 ) STOP

(PLC Step7 ) STOP

EXIT HOLD Breakpoint

318 300 CPU S7-400 CPU

. Cold , Warm CPU 318 S7-300

. Warm CPU S7-300

PLC > Operating Mode . Step7 PLC

Retentive Memory Warm

CPU . CPU CPU

CPU Function Modules

. CPU FM Parameters Basic