Verilog Tutorial: 1-Bit Full Adder

B A

Cin

1-bit full adder

Sum

Cout

A B

S1 Sum

C2 Cout C1 Cin
2012 Chang Choo

Verilog Tutorial: 1-Bit Full Adder

module fulladd (sum, cout, a, b, cin); input a, b, cin; // comments output sum, cout; wire s1, c1, c2; xor (s1, a, b); and (c1, a, b); xor (sum, s1, cin); and (c2, s1, cin); or (cout, c1, c2); endmodule

2012 Chang Choo

Verilog Tutorial: 4-Bit Full Adder

B[3] C4 3 A[3] C3 2 B[2] A[2] C2 1 B[1] A[1] C1 0 B[0] A[0] Cin full adder full adder full adder full adder

S4

S[3]

S[2]

S[1]

S[0]

module fulladd4 (sum, cout, a, b, cin); output [3:0] sum; output cout; input [3:0] a, b; input cin; wire c3, c2, c1; fulladd fa0 (sum[0], c1, a[0], b[0], cin); fulladd fa1 (sum[1], c2, a[1], b[1], c1); fulladd fa2 (sum[2], c3, a[2], b[2], c2); fulladd fa3 (sum[3], cout, a[3], b[3], c3); endmodule
2012 Chang Choo

Verilog Tutorial: 4-Bit Full Adder

// Data Flow Model module adder (sum, a, b); input [3:0] a, b; output [4:0] sum; wire [4:0] sum; assign sum = a + b; // assign p=a*b; endmodule

2012 Chang Choo

HDL Design Flow Behavior. Simulation

VHDL Library VHDL Model
VHDL Testbench

Optional

Simulation Compiler

Simulation Model

Test Vectors

Waveform

VHDL Simulation

Text Output

2012 Chang Choo

Some Verilog Examples

// 4-bit comparator module four_bit_comp (gt, A, B); output gt; input [3:0] A, B; assign gt = (A > B); endmodule // 4-bit max another way module four_bit_max (max, A, B); output [3:0] max; input [3:0] A, B; assign max = (A > B) ? A : B; endmodule

2012 Chang Choo

Some Verilog Examples

// 4-bit ALU module alu4 (A, B, S, Y); input [3:0] A, B; input [1:0] S; // selection inputs output [3:0] Y; reg [3:0] Y; always @ (A or B or S) case (S) 2'b00: Y = A+B; // A*B for multiplication 2'b01: Y = A-B; 2'b10: Y = A&B; 2'b11: Y = A|B; endcase endmodule
2012 Chang Choo

Some Verilog Examples

// 4-bit 2-to-1 MUX module mux4 (y, a, b, sel); input [3:0] a, b; input sel; output [3:0] y; reg [3:0] y; always @(a or b or sel) begin if (sel==0) y = a; else y = b; end endmodule
2012 Chang Choo