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Accurate Power Circuit Loss Estimation Method for Power Converters With Si-IGBT and SiC-Diode Hybrid Pair
Kazuto Takao and Hiromichi Ohashi, Life Member, IEEE
AbstractAn accurate power circuit loss estimation method has been developed for designing power converters with hybrid pairs of silicon (Si) insulated-gate bipolar transistor (Si-IGBT) and silicon carbide (SiC) Schottky barrier diode/SiC p-i-n diode. An analytical model of the switching losses of the hybrid pairs is proposed to achieve high accuracy and short calculation time. The nonlinearity of the device parameters and the stray inductance in the circuit are considered in the model. For the accurate power loss calculation, an empirical parameter extraction method is introduced for extracting device parameters. The calculated circuit power losses are compared with measurement results, and good agreements are conrmed. By using the proposed method, the power loss of a power converter utilizing 4.5-kV Si-IGBT/SiC-p-i-n-diode hybrid pairs is estimated to investigate the upper limitation of the switching frequency. Index TermsInsulated-gate bipolar transistors (IGBTs), p-i-n diode, power loss, Schottky barrier diode.

I. I NTRODUCTION

IGH-POWER medium-voltage power converters support various social infrastructures including railway systems, industrial drive systems, and electric power systems. Insulatedgate bipolar transistor (IGBT) and p-i-n diode are frequently utilized in high-power medium-voltage power converters. Recently, hybrid pairs of silicon (Si) IGBT (Si-IGBT) and silicon carbide (SiC) Schottky barrier diode (SiC-SBD)/SiC p-i-n diode have been actively developed for high-power converter applications [1][4]. In the power converter design, power losses of the power devices are important design parameters because they determine efciency of the power converter circuits and cooling systems of the power devices [5], [6]. An accurate power loss estimation method of the power devices is needed for the efcient power converter circuit design. In addition, the short calculation time is also an important feature to calculate the power losses in various circuit conditions.

Manuscript received July 15, 2012; revised October 3, 2012; accepted October 10, 2012. Date of publication January 9, 2013; date of current version January 18, 2013. The review of this paper was arranged by Editor E. Seebacher. K. Takao is with the Electron Devices Laboratory, Corporate Research and Development Center, Toshiba Corporation, Kawasaki 212-8582, Japan, on leave from Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology, Tsukuba 305-8561, Japan (e-mail: kazuto.takao@toshiba.co.jp). H. Ohashi is with the Energy Technology Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba 305-8561, Japan (e-mail: h.oohashi@aist.go.jp). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TED.2012.2226179

Power losses of the power devices consist of conduction losses and switching losses. The conduction loss can be estimated based on the static I V characteristic of the power device, while the switching loss is inuenced by the circuit stray parameters such as stray inductances and capacitances [7][9]. This means that the consideration of the correlation between the power semiconductor device parameters and circuit stray parameters is indispensable for the accurate power loss estimation. Circuit simulators are widely utilized to estimate the power losses of power devices. They calculate the voltage and current waveforms of the power devices based on device compact models such as SPICE models. The inuence of the circuit stray parameters can be estimated by using circuit simulators. From the simulated voltage and current waveforms, the switching losses are calculated. For this purpose, a lot of physics-based IGBT and p-i-n diode models have been developed [10][13]. In order to make physics-based models, the physical device parameters of the IGBTs are needed. Generally, the information of the internal structure of the IGBTs is not opened to circuit designers. Hence, the extraction of the accurate physical device parameters is difcult. Other issues of the circuit simulator are inaccurate switching waveforms and nonconvergences. These are often encountered in particularly high-speed switching conditions. Furthermore, it is not suitable for massive data processing to compare a lot of circuit design cases. For these reasons, power converter circuit designers have difculty in the power loss estimation by using the circuit simulators. In order to resolve the aforementioned issues, an analytical power loss model is successfully developed for power converter circuits utilizing power MOSFETs [7][9]. The model considers the inuences of circuit stray inductances and the nonlinearity of the junction capacitances of the power MOSFETs. The model demonstrates good tradeoff between the accuracy and simulation time. However, the analytical loss model for IGBTs and p-i-n diodes, which are bipolar devices, has not been developed. This paper proposes a novel power loss estimation method based on an analytical power loss model of Si-IGBT and SiCSBD/p-i-n-diode pairs. In the proposed method, switching loss of the hybrid pairs is calculated by analytical power loss models derived based on the equivalent circuits for the Si-IGBT, SiCSBD, and SiC p-i-n diode. To realize accurate power loss estimation, an empirical method for the parameter extraction is introduced. Experimental verications of the power losses estimated by the proposed method are carried out. By using the proposed method, power losses of the high-voltage Si-IGBT

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Fig. 1.

Equivalent circuits for the Si-IGBT, SiC-SBD, and SiC p-i-n diode.

and SiC-p-i-n-diode hybrid pair are calculated to investigate the upper limitation of the switching frequency. II. A NALYTICAL P OWER L OSS M ODELS FOR Si-IGBT/SiC-D IODE H YBRID PAIRS In the proposed analytical power loss estimation method, the power losses are estimated from their switching waveforms. The switching waveforms are described by analytical model derived based on the equivalent circuit of power devices. The device parameters in the analytical model are described by approximation formulas. Fitting coefcients in the approximation formulas are empirically extracted based on measured switching waveforms.
Fig. 2. Equivalent circuit of a chopper.

A. Equivalent Circuits of Si-IGBT, SiC-SBD, and SiC p-i-n Diode Power loss of a power device consists of conduction loss and switching loss. The conduction loss is calculated from the static I V characteristic. In the proposed power loss estimation method, measured static I V characteristics are utilized to calculate the conduction loss. The switching loss is inuenced by the circuit voltage, current, stray inductances in the circuit, and gate drive conditions. In the proposed method, analytical switching models are utilized to calculate the switching loss. Fig. 1 shows equivalent circuits for the Si-IGBT, SiC-SBD, and SiC p-i-n diode to establish the analytical switching loss models. The Si-IGBT and SiC p-i-n diode are bipolar devices so that they have diffusion capacitances (CD ) that represent minority carrier storage in the drift regions. To realize the accurate power loss estimation, the model parameters in Fig. 1 are described with empirically obtained tting parameters or equations extracted from switching waveforms. The intention of employing the empirical model is to improve the accuracy of the calculation results. In addition,

other advantages of the empirical model are simple and easy to implement. B. Switching Models and Parameter Extraction Procedures for the Si-IGBT To analyze the switching behavior of power devices, a chopper circuit with an inductive load is assumed. Fig. 2 shows the equivalent circuit of the chopper. Stray inductances (Ls1 , Ls2 , Ls3 , Ls4 , Ls5 , and Lsg ) are taken into account in the equivalent circuit. The schematic of typical switching waveforms of the Si-IGBT in the chopper is shown in Fig. 3. The switching waveforms of the power devices can be divided in some periods based on the physical behavior [7][9]. 1) Turn-On Phase: In the period of I, the collector current ic increases toward the load current IL with increasing the gateemitter voltage vge . The ic is given as follows [14]: ic = gm (vge Vth ) (1)

where gm is the transconductance and Vth is the threshold voltage of the Si-IGBT. The analytical model of vge which

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(= IL ) in this period. From the waveforms of vge and vce , Cgc can be extracted. In this period, the SiC diode is reverse biased, and the reverse diode current idiode is added to the ic . Therefore, ic is described by the following equation: ic = IL + idiode . (6)

Fig. 3. Schematic of typical switching waveforms under a low-gate-resistance condition.

considered the inuence of the source stray inductance Ls5 is described in [3]. In the proposed method, ic is described with an empirical equation as a function of vge . The empirical equation is extracted from the ic vge curve. Because the Si-IGBT is the bipolar device, the carrier distribution in the n drift region at the turn-on transient is different from that of the steady state. Therefore, the empirical equation of ic is extracted from turnon waveforms. The collectoremitter voltage vce is decreased by inductive voltage of the stray inductance in the main circuit loop Ls (= Ls1 + Ls2 + Ls3 + Ls4 + Ls5 ) and is described as follows: vce = Vcc Ls dic dt (2)

In the case of the SiC-SBD, idiode is the charging current of the junction capacitance. In the case of the SiC p-i-n diode, idiode is the reverse recovery current by discharging the diffusion capacitance. An analytical model of idiode of the SiC p-i-n diode is described in Section II-C. 2) Turn-Off Phase: In the period of III, vge decreases rapidly and becomes smaller than Vth before vce reaches Vcc under low-gate-resistance conditions [16]. The channel current disappears in this situation. Therefore, ic is independent of vge , and vce is given by the following equation [15]: vce = 1 WB b NB IL t 2 Q0 1 + b (7)

where WB is the width of drift region, Q0 is the stored charge in the n drift region at steady ON state, and b is the mobility ratio. Equation (7) is redescribed into the following form: vce = a IL t (8)

where a represents 1/2 NB WB /Q0 b/(1 + b) and is extracted from the vce waveform. Notice that a is the function of the IL because Q0 is the function of the IL . In the period of IV, ic is the discharge current of the diffusion capacitance CD of the Si-IGBT. This current is expressed as follows under high lifetime situation [11]: ic = IL exp (1 p-n-p ) t c (9)

where Vcc is the dc link voltage. In the period of II, the collector-emitter voltage vce decreases and is described as follows: vce = Vce (VGH + VGL ) VGPon Rg Cgc t (3)

where VGH and VGL are applied gate drive voltages at the ON state and OFF state, respectively, VGPon is the gateemitter voltage during this period, and Vce is vce at t = t2 . Cgc is the junction capacitance between the gate and collector electrodes and is described as follows: Cgc = Agd = WSC 2 vce q NB
1 2

Agd

(4)

where is the permittivity of silicon, WSC is the width of the depletion layer in the drift region, Agc is the cross-sectional area between the gate and collector electrodes, q is the unit charge, and NB is the total carrier density in the depletion layer. NB consists of the doping carrier density in the drift region, the carrier density by the hole current, and the carrier density by the electron current [15]. By using the vce and vge waveforms, Cgc is described as follows: Cgc = Ig dvce dt =
VGPon Rg dvce dt

where p-n-p is the common-base current gain of the p-n-p transistor in the Si-IGBT at this period and c is the carrier transit time. These parameters can be extracted from the ic waveform. Fig. 4 shows the parameter extraction owchart for the Si-IGBT. First of all, the gate input capacitance Ciss is extracted by the static C V characteristic. Then, other model parameters are extracted from the switching waveforms. By using the extracted parameters, waveform and switching loss calculations are implemented. The calculated waveforms and switching losses are compared with the measured ones. In some case, the extracted device parameters do not perfectly represent the nonlinearity of the real devices, and some errors may be observed in calculated waveforms and switching losses. When the error is not acceptable, the coefcients in approximation formulas of device parameters should be adjusted. The criterion to adjust device parameters is the acceptable error determined by circuit designers. C. Switching Models and Parameter Extraction Procedures for the SiC Diodes A schematic of the turn-off waveforms of the SiC p-i-n diode is shown in Fig. 5. In the period of I-d, the diode current id decreases until the peak reverse recovery current IRM with the same current slope di/dt before time td1 . The reverse recovery

(5)

where Ig is the gate current and VGPon is the gate voltage at this period. VGPon has a constant value because ic is constant

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Fig. 7. Flowchart of parameter extraction for the SiC diodes. TABLE I D EVICE PARAMETERS Fig. 4. Flowchart of parameter extraction for the Si-IGBT.

Fig. 5.

Schematic of turn-off waveforms of the SiC p-i-n diode.

from the current waveform. The diode voltage vd is described as follows: vd = Vcc vce + Ls did . dt (11)

Fig. 6.

Schematic of turn-off waveforms of the SiC-SBD.

current consists of the discharge currents of CD and Cj . In the case of the p-i-n diode, CD is much larger than Cj . In the period of II-d, id is still in the reverse recovery state. In this period, the diode voltage vd enters the reverse-blocking state. id is described as follows [17]: id = IRM exp t RR (10)

where IRM is the peak reverse recovery current and RR is the diode reverse recovery time constant which can be measured

At time td3 , vd corresponds to (Vcc vce ). In the period of III-d, id is constant to its OFF-state current, and vd reverse biased until Vcc . The turn-off waveforms of the SiC-SBD are shown in Fig. 6. The reverse current of the SiC-SBD is caused by the charging of the Cj . At time td1 , the SiC-SBD enters its reverse-blocking state. The Cj of the SiC-SBD starts charging, and the charging current ows. id and vd form the ringing waveforms by the resonance of the Cj and Ls . Therefore, the id and vd waveforms after td1 can be formulated by using Cj and Ls . Fig. 7 shows the parameter extraction owcharts for the SiC-SBD and SiC p-i-n diode. First of all, the static Cj V characteristics are measured. The Cj is represented as a function of

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Fig. 8. (Dashed) Calculated and (solid) measured waveforms. (a) Turn-on of the 600 V/6 A Si-IGBT. (b) Turn-off of the 600 V/6 A Si-IGBT. (c) Turn-on of the 4.5-kV Si-IGBT. (d) Turn-off of the 4.5-kV Si-IGBT.

the reverse-biased voltage. In the case of the SiC p-i-n diode, the reverse recovery charge Qrr and rr are extracted from the switching waveforms. By using all the extracted parameters, the switching waveforms and reverse recovery loss are calculated and compared with the measured ones. If the calculated results are not acceptable, the parameters should be adjusted to obtain the acceptable error. III. E XPERIMENTAL V ERIFICATION OF THE A NALYTICAL S WITCHING M ODELS The switching waveforms, which are calculated with the analytical switching models shown in Section II, are compared with the measured waveforms to evaluate the accuracy of the models. The 600-V Si-IGBT/SiC-SBD and 4.5-kV SiIGBT/SiC-p-i-n-diode hybrid pairs are demonstrated. Furthermore, the switching energies are estimated from the calculated waveforms and compared to the measured values. The model parameters of the 600 V/6 A Si-IGBT and 600 V/6 A SiC-SBD both produced by Inneon, 4.5 kV/50 A Si-IGBT produced by Toshiba, and 4.5 kV/25 A SiC p-i-n diode fabricated by the Advanced Industrial Science and Technology [18] are extracted. Two 4.5 kV/25 A SiC-p-i-n-diode chips are connected in parallel to use with the 4.5 kV/50 A Si-IEGT. Table I summarizes the extracted parameters of the semiconductor devices. The parameters of the 600-V Si-IGBT and SiC-SBD are extracted at the temperature of 150 C, and the parameters of the 4.5-kV Si-IGBT and SiC p-i-n diode are extracted at the temperature of 125 C. Fig. 8 shows the calculated (dashed) and measured (solid) switching waveforms for the 600 V/6 A Si-IGBT and

4.5 kV/50 A Si-IGBT. The switching waveforms are obtained in the chopper shown in Fig. 2. In the case of the 600 V/6 A Si-IGBT, input dc voltage is 300 V, and stray inductance in the main circuit loop Ls is 82 nH. The gate resistance is 10 , and the gate applied voltage is +15 V. In the case of the 4.5 kV/50 A Si-IGBT, input dc voltage is 2500 V, and stray inductance in the main circuit loop Ls is 3.5 H. The gate resistance is 100 , and the gate applied voltage is +15/10 V. The waveform calculations are implemented by using the circuit parameters of the experiment. In Fig. 8(a) and (b), device parameters of the 600 V/6 A Si-IGBT and 600-V SiC-SBD are utilized. On the other hand, in Fig. 8(c) and (d), device parameters of the 4.5 kV/50 A Si-IGBT and 5-kV SiC p-i-n diode are utilized. As seen in Fig. 8, a good agreement between the measured waveforms and calculated waveforms is obtained. The results indicate that the proposed method can exactly estimate the inuence of circuit parameters including the stray inductance. Turn-on and turn-off switching energies are estimated by time integrating the products of vce and ic waveforms. The switching energies obtained by measured and calculated waveforms are shown in Fig. 9. As seen in the gure, the difference between the measured and calculated switching energies is within 10%. The error of the Si-IGBT switching energies, which are calculated with the circuit simulator (PSPICE), is evaluated in [13]. In that simulation, despite utilizing the optimized device parameters of the physics-based IGBT model, the error in the worst case is 52%. Therefore, the accuracy of the proposed method is signicantly improved compared to the conventional circuit simulator.

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Fig. 9. Dependence on switching energies on load current IL . (a) Turn-on switching energy Eon of the 600 V/6 A Si-IGBT. (b) Turn-off switching energy Eo of the 600 V/6 A Si-IGBT. (c) Eon of the 4.5-kV Si-IGBT. (d) Eo of the 4.5-kV Si-IGBT.

IV. E STIMATION OF THE S WITCHING -F REQUENCY L IMITATION OF THE H IGH -VOLTAGE Si-IGBT/SiC-p-i-n-D IODE H YBRID PAIR Reduction in size and weight of high-power medium-voltage power converters is essential for saving space and cutting the cost. One of the issues is that they often need bulky and heavy magnetic components such as transformers and LC lters [19]. In order to shrink the size of the magnetic components, a high-switching-frequency operation of power converters is required. For realizing the high-switching-frequency operation, high-voltage Si-IGBT/SiC-p-i-n-diode hybrid pairs have been investigated [20]. In this section, the switching-frequency limitation of the high-voltage Si-IGBT/SiC-p-i-n-diode hybrid pair is investigated from the point of view of the power loss. The power loss of the Si-IGBT is calculated by the proposed method in this work. The model parameters of 4.5 kV/50 A Si-IGBT and two parallel 4.5 kV/25 A SiC p-i-n diodes extracted in the previous section are utilized for the power loss calculation. Fig. 10 shows the turn-on and turn-off switching energies (Eon and Eo , respectively) dependence on the gate resistance Rg of the Si-IEGT at Tj = 125 C. The Eon is proportional to the Rg . In contrast, the Eo is not inuenced by the Rg in the range smaller than 100 . Both Eon and Eo increase with increasing the IL . Utilizing the Eon and Eo data shown in Fig. 10, the dependence of the total power loss of the Si-IGBT Ptotal , which consists of the conduction loss and switching loss, on the switching frequency is estimated. In the power loss calculation, a standard two-level inverter circuit shown in Fig. 11 is assumed. The inverter specications are listed in Table II. Fig. 12 shows the dependence of the total power loss Ploss of the Si-IEGT on the switching frequency fsw .

Fig. 10. Calculated switching energies of the 4.5 kV/50 A Si-IGBT. (a) Turnon switching energy Eon . (b) Turn-off switching energy Eo . TABLE II I NVERTER S PECIFICATIONS

With a conventional forced liquid cooling technique, the maximum allowable power loss per chip of the Si-IEGT is about 270 W. Therefore, the switching frequencies of

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Fig. 11. Equivalent circuit of a two-level inverter used for power loss calculation of the 4.5 kV/50 A Si-IGBT.

Fig. 12. Dependence of the total power loss Ploss of the 4.5 kV/50 A Si-IGBT on the switching frequency fsw .

2 kHz at Rg = 100 and 2.9 kHz at Rg = 20 can be available. V. C ONCLUSION A novel power loss estimation method for Si-IGBT/SiC-SBD and Si-IGBT/SiC-p-i-n-diode hybrid pairs has been presented to realize high accuracy and fast calculation. The proposed method is validated by comparing the calculated results with the measurement results. The error of the calculated switching energies is within 10%. The results indicate that the proposed method could implement an accurate power loss design of power converters utilizing hybrid pairs. By using the proposed method, the switching-frequency limitation of the high-voltage Si-IGBT/SiC-p-i-n-diode hybrid pair is investigated from the viewpoint of the power loss. The results indicate that 2.9-kHz operations of a 4.5-kV Si-IGBT would be possible with the SiC p-i-n diode. R EFERENCES
[1] W. Bartsch, S. Gediga, H. Koehler, R. Sommer, and G. Zaiser, Comparison of Si- and SiC-powerdiodes in 100 A-modules, in Proc. 12th EPE, Aalborg, Denmark, Sep. 2007, pp. 18, [CD-ROM]. [2] K. Takao, Y. Tanaka, K. Sung, K. Wada, T. Shinohe, T. Kanai, and H. Ohashi, 3-level power converter with high-voltage SiC-PiN diode and hard-gate-driving of IEGT for future high-voltage power conversion systems, in Proc. IEEE Appl. Power Electron. Conf., 2010, pp. 11011107. [3] H. Mirzaee, A. De, A. Tripathi, and S. Bhattacharya, Design comparison of high power medium-voltage converters based on 6.5 kV Si-IGBT/ Si-PiN diode, 6.5 kV Si-IGBT/SiC-JBS diode, 10 kV SiC MOSFET/SiCJBS diode, in Proc. IEEE ECCE, 2011, pp. 24212428. [4] T. Duong, A. Hefner1, K. Hobart, S. Ryu, D. Grider, D. Berning, J. M. Ortiz-Rodriguez, E. Imhoff, and J. Sherbondy, Comparison of 4.5 kV SiC JBS and Si PiN diodes for 4.5 kV Si IGBT anti-parallel diode applications, in Proc. IEEE Appl. Power Electron. Conf., 2012, pp. 10571063.

[5] U. Drofenik and J. W. Kolar, A general scheme for calculating switchingand conduction-losses of power semiconductors in numerical circuit simulations of power electronic systems, in Proc. IPEC, 2005, pp. 1604 1610, [CD-ROM]. [6] Y. Hayashi, K. Takao, T. Shimizu, and H. Ohashi, Power converter integration design based on evaluation platform concept, in Proc. 4th Int. CIPS, 2006, pp. 14, [CD-ROM]. [7] Y. Xiao, H. Shah, T. P. Chow, and R. J. Gutmann, Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics, in Proc. APEC, 2004, pp. 516521. [8] K. Takao, Y. Hayashi, S. Harada, and H. Ohashi, Novel evaluation approach for an ultra high speed low loss power converter, in Proc. EPEPEMC, 2004, [CD-ROM]. [9] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, Analytical loss model of power MOSFET, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310319, Mar. 2006. [10] A. R. Hefner and D. L. Blackburn, An analytical model for the steadystate and transient characteristics of the power insulated-gate bipolar transistor, Solid State Electron., vol. 31, no. 10, pp. 15131532, Oct. 1988. [11] P. R. palmer, E. Santi, J. L. Hudgins, X. Kang, J. C. Joyce, and P. Y. Eng, Circuit simulator models for the diode and IGBT with full temperature dependent features, IEEE Trans. Power Electron., vol. 18, no. 5, pp. 12201229, Sep. 2003. [12] T. R. McNutt, A. R. Hefner, Jr., H. Alan Mantooth, J. Duliere, D. W. Berning, and R. Singh, Silicon carbide PiN and merged PiN Schottky power diode models implemented in the Saber circuit simulator, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 573581, May 2004. [13] A. T. Bryant, X. Kang, E. Santi, P. R. Palmer, and J. L. Hudgins, Twostep parameter extraction procedure with formal optimization for physicsbased circuit simulator IGBT and p-i-n diode models, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 295309, Mar. 2006. [14] B. J. Baliga, Power Semiconductor Devices. Boston, MA: PWS-Kent, 1995, pp. 388395. [15] T. Ogura, H. Ninomiya, K. Sugiyama, and T. Inoue, Turn-off switching analysis considering dynamic avalanche effect for low turn-off loss highvoltage IGBTs, IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 629 635, Apr. 2004. [16] K. Sheng, F. Udera, and G. A. J. Amaratunga, Optimum carrier distribution of the IGBT, Solid State Electron., vol. 44, no. 9, pp. 15731583, Sep. 2000. [17] P. O. Lauritzen and C. L. Ma, A simple diode model with reverse recovery, IEEE Trans. Power Electron., vol. 6, no. 2, pp. 188191, Apr. 1991. [18] Y. Tanaka, K. Takao, K. Sung, K. Wada, T. Kanai, and H. Ohashi, Development of 6 kV-class SiC-PiN diodes for high-voltage power inverter, in Proc. Int. Symp. Power Semicond. Devices ICs, 2010, pp. 213216. [19] K. Kunomura, M. Onishi, M. Kai, N. Iio, and N. Nakajima, Electronic frequency converter feeding single phase circuit for Shinkansen, in Proc. IPEC, 2010, pp. 31363143. [20] K. Takao, Y. Tanaka, K. Sung, K. Wada, T. Shinohe, T. Kanai, and H. Ohashi, High-frequency switching high-power converter with SiCPiN diodes and Si-IEGTs, in Proc. IEEE ECCE, 2010, pp. 45584563.

Kazuto Takao received the Ph.D. degree in energy science from Toyama University, Toyama, Japan, in 2002. He is currently with the Electron Devices Laboratory, Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Japan.

Hiromichi Ohashi (LM12) received the Ph.D. degree in electronics from Tohoku University, Sendai, Japan. He is with the Energy Technology Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan.