Control Unit

CS1251 Computer Organization Carl Hamacher

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Control Unit
MEM

MAR PC IR

MDR R0 R1
. . .

Control

ALU

Rn-1

Processor

MAR - Memory Address Register MDR - Memory Data Register

copyright 2011-2015

PC - Program Counter IR - Instruction Register

2

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Fetch and Execute

MOVE NUM1,R1

Fetch
MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]

Execute
MAR NUM1 MDR [MEM([MAR])] R1 [MDR]

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Single-Bus Architecture
BUS A

MAR MEM
1

PC MDR
MUX
2 1 2 1

IR
2

MUX

REGS
A ALU R B

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Instruction Execution
Perform one or more of the following operations in some specified sequence
Transfer a word of data from one processor register to another or to the ALU Perform an arithmetic or logic operation and store the result in a processor register Load the contents of a given memory location into a processor register Store a word of data from a processor register into a given memory location

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Memory Timing
MOVE NUM1,R1 1. MAR NUM1 2. MDR [MEM([MAR])] 3. R1 [MDR] One Clock Cycle ? Clock Cycles One Clock Cycle

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Memory Detail
MEM
ADDRESS

MAR
REG
DATA_OUT DATA_IN Enable_Out CLK Enable_In

BUS_A

RAM
Write Enable_In1 DATA_IN1 DATA_OUT1 Enable_Out1 CLK Enable_Out2 DATA_OUT2 DATA_IN2 Enable_In2

Read MFC CLK

DATA_OUT DATA_IN

REG_2PORT

MDR

MFC = Memory-Function-Completed copyright 2011-2015 WWW.VidyarthiPlus.in 7

Memory Timing
Step 1 2 3 RTN MAR NUM1 MDR [MEM([MAR])] R1 [MDR] Control Signals

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Memory Timing
Step 1 2 3 RTN MAR NUM1 Control Signals MAR_En_In, IR_En_Out1

MDR [MEM([MAR])] MEM_Read, MDR_En_In1, Wait MCF R1 [MDR] MDR_En_Out2, REGS_Sel, REGS_Write

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Step Clock MAR_En_In Address MEM_Read MDR_En_In1 Data_Out MFC MDR_En_Out2

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Another Example
ADD (R3),R1

Fetch
MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]

Execute
MAR [R3] MDR [MEM([MAR])] Y [R1] Z [Y] + [MDR] R1 [Z]

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Control Signals
ADD (R3),R1
Step 1 2 3 4 5 6 7 RTN MAR [PC], PC [PC] + 1 MDR [MEM([MAR])] IR [MDR] MAR [R3] MDR [MEM([MAR])], Y [R1] Z [Y] + [MDR] R1 [Z] Control Signals

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Control Signals
ADD (R3),R1
Step 1 2 3 4 5 6 7 RTN MAR [PC], PC [PC] + 1 MDR [MEM([MAR])] IR [MDR] MAR [R3] MDR [MEM([MAR])], Y [R1] Z [Y] + [MDR] R1 [Z] Control Signals MAR_En_In, PC_En_Out, PC_Inc MEM_Read, MDR_En_In1 MDR_En_Out2, IR_En_In1 MAR_EN_In, REGS_Sel, REGS_Read MEM_Read, MDR_En_In1, REGS_Sel, REGS_Read, Y_En_In1 Y_En_Out1, MDR_En_Out2, ALU_Op = Add, Z_En_In Z_En_Out, REGS_Sel, REGS_Write

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Branch Instructions
MOVE MOVE MOVE LOOP ADD ADD ADD BGTZ MOVE HALT N,R1 #NUM1,R2 #0,R0 (R2),R0 #1,R2 #-1,R1 LOOP R0,SUM

BGTZ -4 PC

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Branch Instructions
BGTZ LOOP

Execute
if CC>0, PC [PC] + [IR]

Condition Code
Z = 0, N = 0

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Multiple Bus Architecture

BUS A BUS B BUS C

PC
1

IR 2
A1 A2

1 2

REGS

MUX

ALU R
B NZVC
2 3

MDR 1

MAR

MEM
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Example Revisited
ADD (R3),R1

Fetch
MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]

Execute
MAR [R3] MDR [MEM([MAR])] R1 [MDR] + [R1]

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Control Signals
ADD (R3),R1
Step 1 2 3 4 5 6 RTN MAR [PC], PC [PC] + 1 MDR [MEM([MAR])] IR [MDR] MAR [R3] MDR [MEM([MAR])] R1 [MDR] + [R1] Control Signals

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Control Signals
ADD (R3),R1
Step 1 2 3 4 5 6 RTN MAR [PC], PC [PC] + 1 IR [MDR] MAR [R3] Control Signals MAR_En_In, PC_En_Out, ALU_Op = Pass_B, PC_Inc MDR_En_Out2, IR_En_In1, ALU_Op = Pass_A MAR_EN_In, REGS_Read1, ALU_Op = Pass_A MDR_En_Out2, REGS_Read2, ALU_Op = Add, REGS_Write

MDR [MEM([MAR])] MEM_Read, MDR_En_In1

MDR [MEM([MAR])] MEM_Read, MDR_En_In1 R1 [MDR] + [R1]

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Questions?
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