APPLICATION

NOTE
AP-258
Febiuaiy 1986
High Speed Numerics with the
8018680188 and 8087
STEVE FARRER
APPLICATIONS FNOINFFR
Order Number 231590-001
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COPYRIGHT INTEL CORPORATION 1996
HIGH SPEED NUMERICS
WITH THE 8018680188
AND 8087
CONTENTS PAGE
10 INTRODUCTION 1
20 OVERVIEW OF THE
8018680188 1
30 NUMERICS OVERVIEW 2
31 The Benefits of Numeric
Coprocessing 2
32 Introduction to the 8087 2
33 Escape Instructions 2
34 Host Response to Escape
Instructions 3
35 Coprocessor Response to Escape
Instructions 3
40 OVERVIEW OF THE 82188
INTEGRATED BUS CONTROLLER 4
41 Introduction 4
42 Bus Control Signals 4
43 Bus Arbitration 4
44 Interface Logic 4
50 DESIGNING THE SYSTEM 4
51 Circuit Schematics of the
801868-821888087 System 4
52 Queue Status Interface 5
53 Control Signals 6
531 ALE 6
532 Read Write 7
533 DEN 7
534 DTR 7
54 Chip Selects 8
541 Introduction 8
542 CSI and CSO of the 82188 8
543 System Design Example 9
55 Wait State Ready Logic 10
551 Internal Wait States with Instruction
Fetches 10
552 Internal Wait States with Data IO
Cycles 10
553 Automatic Wait States at Reset 10
554 External Ready Synchronization 11
56 Bus Arbitration 11
57 Speed Requirements 11
CONTENTS PAGE
60 BENCHMARKS 12
61 Introduction 12
62 Interest Rate Calculations 12
63 Matrix Multiply Benchmark Routine 13
CONTENTS PAGE
64 Whetstone Benchmark Routine 13
65 Benchmark Conclusions 15
70 CONCLUSION 15
AP-258
10 INTRODUCTION
Fiom theii intioduction in 1982, the highIy integiated
16-bit 80186 and its 8-bit exteinaI bus veision, the
80188, have been ideaI piocessoi choices foi high-pei-
foimance, Iow-cost embedded contioI appIications. The
integiated peiipheiaI functions and enhanced 8086
CPU of the 80186 and 80188 aIIow foi an easy upgiade
of oIdei geneiation contioI appIications to achieve
highei peifoimance whiIe Ioweiing the oveiaII system
cost thiough ieduced boaid space, and a simpIified pio-
duction fIow.
Moie and moie contioIIei appIications need even high-
ei peifoimance in numeiics, yet stiII iequiie the Iow-
cost and smaII foim factoi of the 80186 and 80188. The
8087 Numeiics Data Copiocessoi satisfies this need as
an optionaI add-on component.
The 8087 Numeiic Data Copiocessoi is inteifaced to
the 80186 and 80188 thiough the 82188 IBC (Integiat-
ed Bus ContioIIei). The IBC piovides a highIy integiat-
ed inteiface soIution which iepIaces the 8288 used in
80868087 systems. The IBC incoipoiates aII the nec-
essaiy bus contioI foi the 8087 whiIe aIso pioviding the
necessaiy Iogic to suppoit the inteiface between the
80186/8 and the 8087.
This appIication note discusses the design consideia-
tions associated with using the 8087 Numeiic Data Co-
piocessoi with the 80186 and 80188. Sections two,
thiee, and foui contain an oveiview of the integiated
ciicuits invoIved in the numeiics configuiation. Section
five discusses the inteifacing aspects between the
80186/8 and the 8087, incIuding the ioIe of the 82188
Integiated Bus ContioIIei and the opeiation of the inte-
giated peiipheiaIs on the 80186/8 with the 8087. Sec-
tion six compaies the advantages of using an 8087 Nu-
meiic Data Copiocessoi ovei softwaie ioutines wiitten
foi the host piocessoi as weII as the advantage of using
an 80186/8 numeiics system ovei an 8086/8088 nu-
meiics system.
Fxcept wheie noted, aII futuie iefeiences to the 80186
wiII appIy equaIIy to the 80188.
20 OVERVIEW OF THE 80186
The 80186 and 80188 aie highIy integiated miciopioc-
essois which effectiveIy combine up to 20 of the most
common system components onto a singIe chip. The
80186 and 80188 piocessois aie designed to piovide
both highei peifoimance and a moie highIy integated
soIution to the totaI system.
Highei integiation iesuIts fiom integiating system pe-
iipheiaIs onto the miciopiocessoi. The peiipheiaIs con-
sist of a cIock geneiatoi, an inteiiupt contioIIei, a
DMA contioIIei, a countei/timei unit, a piogiamma-
bIe wait state geneiatoi, piogiammabIe chip seIects,
and a bus contioIIei. (See Figuie 1.)
2315901
Figure 1 801868 Block Diagram
1
AP-258
Highei peifoimance iesuIts fiom enhancements to both
geneiaI and specific aieas of the 8086 CPU, incIuding
fastei effective addiess caIcuIation, impiovement in the
execution speed of many instiuctions, and the incIusion
of new instiuctions which aie designed to pioduce opti-
mum 80186 code.
The 80186 and 80188 aie compIeteIy object code com-
patibIe with the 8086 and 8088. They have the same
basic iegistei set, memoiy oiganization, and addiessing
modes. The diffeiences between the 80186 and 80188
aie the same as the diffeiences between the 8086 and
8088: the 80186 has a 16-bit aichitectuie and 16-bit bus
inteiface, the 80188 has a 16-bit inteinaI aichitectuie
and an 8-bit data bus inteiface. The instiuction execu-
tion times of the two piocessois diffei accoidingIy: foi
each non-immediate 16-bit data iead/wiite instiuction,
4 additionaI cIock cycIes aie iequiied by the 80188.
30 NUMERICS OVERVIEW
31 The Benefits of Numeric
Coprocessing
The 8086/8 and 80186/8 aie geneiaI puipose micio-
piocessois, designed foi a veiy wide iange of appIica-
tions. TypicaIIy, these appIications need fast, efficient
data movement and geneiaI puipose contioI instiuc-
tions. Aiithmetic on data vaIues tends to be simpIe in
these appIications. The 8086/8 and 80186/8 fuIfiII these
needs in a Iow cost, effective mannei.
Howevei, some appIications iequiie extiemeIy fast and
compIex math functions which aie not piovided by a
geneiaI puipose piocessoi. Such functions as squaie
ioot, sine, cosine, and Iogaiithms aie not diiectIy avaiI-
abIe in a geneiaI puipose piocessoi. Softwaie ioutines
iequiied to impIement these functions tend to be sIow
and not veiy accuiate. Integei data types and theii
aiithmetic opeiations (i.e., add, subtiact, muItipIy and
divide) which aie diiectIy avaiIabIe on geneiaI puipose
piocessois, stiII may not meet the needs foi accuiacy,
speed and ease of use.
Pioviding fast, accuiate, compIex math can be quite
compIicated, iequiiing Iaige aieas of siIicon on inte-
giated ciicuits. A geneiaI data piocessoi does not pio-
vide these featuies due to the extia cost buiden that Iess
compIex geneiaI appIications must take on. Foi such
featuies, a speciaI numeiic data piocessoi is iequiied -
one which is easy to use and has a high IeveI of suppoit
in haidwaie and softwaie.
32 Introduction to the 8087
The 8087 is a numeiic data copiocessoi which is capa-
bIe of peifoiming compIex mathematicaI functions
whiIe the host piocessoi (i.e. the main CPU) peifoims
moie geneiaI tasks. It suppoits the necessaiy data types
and opeiations and aIIows use of aII the cuiient haid-
waie and softwaie suppoit foi the 8086/8 and 80186/8
miciopiocessois. The fact that the 8087 is a copioces-
soi means it is capabIe of opeiating in paiaIIeI with the
host CPU, which gieatIy impioves the piocessing pow-
ei of the system.
The 8087 can inciease the peifoimance of fIoating-
point caIcuIations by 50 to 100 times, pioviding the
peifoimance and piecision iequiied foi smaII business
and giaphics appIications as weII as scientific data pio-
cessing.
The 8087 numeiic copiocessoi adds 68 fIoating-point
instiuctions and eight 80-bit fIoating-point iegisteis to
the basic 8086 piogiamming aichitectuie. AII the nu-
meiic instiuctions and data types of the 8087 aie used
by the piogiammei in the same mannei as the geneiaI
data types and instiuctions of the host.
The numeiic data foimats and aiithmetic opeiations
piovided by the 8087 suppoit the pioposed IFFF Mi-
ciopiocessoi FIoating Point Standaid. AII of the pio-
posed IFFF fIoating point standaid aIgoiithms, excep-
tion detection, exception handIing, infinity aiithmetic
and iounding contioIs aie impIemented. The IFFF
standaid makes it easiei to use fIoating point and heIps
to avoid common piobIems that aie inheient to fIoating
point.
33 Escape Instructions
The copiocessing capabiIities of the 8087 aie achieved
by monitoiing the IocaI bus of the host piocessoi. Cei-
tain instiuctions within the 8086 assembIy Ianguage
known as FSCAPF instiuctions aie defined to be co-
piocessoi instiuctions and, as such, aie tieated diffei-
entIy.
The copiocessoi monitois piogiam execution of the
host piocessoi to detect the occuiience of an FSCAPF
instiuction. The fetching of instiuctions is monitoied
via the data bus and bus cycIe status S2S0, whiIe the
execution of instiuctions is monitoied via the queue
status Iines QS0 and QS1.
AII FSCAPF instiuctions stait with the high-oidei 5-
bits of the instiuction opcode being 11011. They have
two basic foims, the memoiy iefeience foim and the
non-memoiy iefeience foim. The non-memoiy foim,
shown in Figuie 2A, initiates some activity in the co-
piocessoi using the nine avaiIabIe bits of the FSCAPF
instiuction to indicate which function to peifoim.
Memoiy iefeience foims of the FSCAPF instiuction,
shown in Figuie 2B, aIIow the host to point out a mem-
oiy opeiand to the copiocessoi using any host memoiy
2
AP-258
MOD
1 1 0 1 1 1 1
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
1st byte
l
2nd byte
Figure 2A Non-Memory Reference ESCAPE Instructions
addiessing mode. Six bits aie avaiIabIe in the memoiy
iefeience foim to identify what to do with the memoiy
opeiand.
Memoiy iefeience foims of FSCAPF instiuctions aie
identified by bits 7 and 6 of the byte foIIowing the FS-
CAPF opcode. These two bits aie the MOD fieId of the
8086/8 oi 80186/8 effective addiess caIcuIation byte.
Togethei with the R/M fieId (bits 2 thiough 0), they
deteimine the addiessing mode and how many subse-
quent bytes iemain in the instiuction.
34 Host Response to Escape
Instructions
The host peifoims one of two possibIe actions when
encounteiing an FSCAPF instiuction: do nothing (op-
eiation is inteinaI to 8087) oi caIcuIate an effective ad-
diess and iead a woid vaIue beginning at that addiess
(iequiied foi aII LOADS and STORFS). The host ig-
noies the vaIue of the woid iead and hence the cycIe is
iefeiied to as a Dummy Read CycIe. FSCAPF in-
stiuctions do not change any iegisteis in the host othei
than advancing the IP. If theie is no copiocessoi oi the
copiocessoi ignoies the FSCAPF instiuction, the FS-
CAPF instiuction is effectiveIy a NOP to the host. Oth-
ei than caIcuIating a memoiy addiess and ieading a
woid of memoiy, the host makes no othei assumptions
iegaiding copiocessoi activity.
The memoiy iefeience FSCAPF instiuctions have two
puiposes: to identify a memoiy opeiand and, foi ceitain
instiuctions, to tiansfei a woid fiom memoiy to the
copiocessoi.
35 Coprocessor Response to Escape
Instructions
The 8087 peifoims basicaIIy thiee types of functions
when encounteiing an FSCAPF instiuction: LOAD
(iead fiom memoiy), STORF (wiite to memoiy), and
FXFCUTF (peifoim one of the inteinaI 8087 math
functions).
When the host executes a memoiy iefeience FSCAPF
instiuction intended to cause a iead opeiation by the
8087, the host aIways ieads the Iow-oidei woid of any
8087 memoiy opeiand. The 8087 wiII save the addiess
and data iead. To iead any subsequent woids of the
opeiand, the 8087 must become a IocaI bus mastei.
When the 8087 has the IocaI bus, it inciements the 20-
bit physicaI addiess it saved to addiess the iemaining
woids of the opeiand.
When the FSCAPF instiuction is intended to cause a
wiite opeiation by the 8087, the 8087 wiII save the ad-
diess but ignoie the data iead. FventuaIIy, it wiII get
contioI of the IocaI bus and peifoim successive wiites
inciementing the 20-bit addiess aftei each woid untiI
the entiie numeiic vaiiabIe has been wiitten.
FSCAPF instiuctions intended to cause the execution
of a copiocessoi caIcuIation do not iequiie any bus ac-
tivity. Numeiic caIcuIations woik off of an inteinaI ieg-
istei stack which has been initiaIized using a LOAD
opeiation. The caIcuIation takes pIace using one oi two
of the stack positions specified by the FSCAPF instiuc-
tion. The iesuIt of the opeiation is aIso pIaced in one of
the stack positions specified by the FSCAPF instiuc-
tion. The iesuIt may then be ietuined to memoiy using
a STORF instiuction, thus aIIowing the host piocessoi
to access it.
MOD RM 16-bit direct displacement
1 1 0 1 1 0 0 1 1 0
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
MOD RM 16-bit displacement
1 1 0 1 1 1 0
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
MOD RM 8-bit displacement
1 1 0 1 1 0 1
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
MOD RM
1 1 0 1 1 0 0
I
15
I
14
I
13
I
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
Figure 2B Memory Reference ESCAPE Instruction Forms
3
AP-258
40 OVERVIEW OF THE 82188
INTEGRATED BUS CONTROLLER
41 Introduction
The 82188 Integiated Bus ContioIIei (IBC) is a highIy
integiated veision of the 8288 Bus ContioIIei. The IBC
piovides command and contioI timing signaIs foi bus
contioI and aII of the necessaiy Iogic to inteiface the
80186 to the 8087.
42 Bus Control Signals
The bus command and contioI signaIs consist of RD,
WR, DFN, DT/R, and ALF. The timings and IeveIs
aie diiven foIIowing the Iatching of vaIid signaIs on the
status Iines S0S2. When S0S2 change state fiom pas-
sive to active, the IBC begins cycIing thiough a state
machine which diives the coiiesponding contioI and
command Iines foi the bus cycIe. As with the 8288, an
addiess enabIe input (AFN) is piesent to aIIow tii-stat-
ing when othei bus masteis suppIy theii own bus con-
tioI signaIs.
43 Bus Arbitration
The IBC aIso has the abiIity to conveit bus aibitiation
piotocoIs of RQ/OT to HOLD-HLDA. This aIIows the
82586 LocaI Aiea Netwoik (LAN) Copiocessoi, the
82730 Text Copiocessoi, and othei copiocessois using
the HOLD-HLDA piotocoI to be inteifaced to the
8086/8 as weII as aIIowing the 80186/8 to be inteifaced
to the 8087. In addition to conveiting aibitiation pioto-
coIs, the IBC makes it possibIe to aibitiate between two
bus masteis using HOLD-HLDA with a thiid using
RQ/OT.
44 Interface Logic
In addition to aII the bus contioI and aibitiation fea-
tuies, the IBC piovides Iogic to connect the queue
status to the 8087, a chip-seIect foi the 8087, and the
necessaiy RFADY synchionization iequiied between
the 8087 and the 80186/8.
50 DESIGNING THE SYSTEM
51 Circuit Schematics of the 801868828888087 System
2315902
Figure 3 801868821888087 Circuit Diagram
4
AP-258
52 Queue Status
The 8087 tiacks the instiuction execution of the 80186
by keeping an inteinaI instiuction queue which is iden-
ticaI to the piocessois instiuction queue. Fach time the
piocessoi peifoims an instiuction fetch, the 8087 Iatch-
es the instiuction into its own queue in paiaIIeI with the
piocessoi. Fach time the piocessoi iemoves the fiist
byte of an instiuction fiom the queue, the 8087 iemoves
the byte at the top of the 8087 queue and checks to see
if the byte is an FSCAPF piefix. If it is, the 8087 de-
codes the foIIowing bytes in paiaIIeI with the piocessoi
to deteimine which numeiic instiuction the bytes iepie-
sent. If the fiist byte of the instiuction is not an FS-
CAPF piefix, the 8087 discaids it aIong with the subse-
quent bytes of the non-numeiic instiuction as the 80186
iemoves them fiom the queue foi execution.
The 8087 opeiates its inteinaI instiuction queue by
monitoiing the two queue status Iines fiom the CPU.
This status infoimation is made avaiIabIe by the CPU
by pIacing it into queue status mode. This iequiies
stiapping the RD pin on the 80186 to giound. When
RD is tied to giound, ALF and WR become QS0
(Queue Status 0) and QS1 (Queue Status 1) iespec-
tiveIy.
Table 1 Queue Status Decoding
QS1 QS0 Queue Operation
0 0 No queue operation
0 1 First byte from queue
1 0 Subsequent byte from queue
1 1 Reserved
Fach time the 80186 begins decoding a new instiuction,
the queue status Iines indicate fiist byte of instiuction
taken fiom the queue. This signaIs the 8087 to check
foi an FSCAPF piefix. As the iemaining bytes of the
instiuction aie iemoved, the queue status indicates
subsequent byte iemoved fiom queue. The 8087 uses
this status to eithei continue decoding subsequent
bytes, if the fiist byte was an FSCAPF piefix, oi to
discaid the subsequent bytes if the fiist byte was not an
FSCAPF piefix.
The QS0(ALF) and QS1(WR) pins of the 80186 aie fed
diiectIy to the 82188 wheie they aie Iatched and de-
Iayed by one-haIf-cIock. The deIayed queue status fiom
the 82188 is then piesented diiectIy to the 8087.
The wavefoims of the queue status signaIs aie shown in
Figuie 4. The ciiticaI timings aie the setup time into
the 82188 fiom the 80186 and the setup and hoId time
into the 8087 fiom the 82188. The caIcuIations foi an 8
MHz system aie as foIIows:
.5T
CLCL
- T
CHQSV
(186 max)
.5(125 ns)
b
35
T
CLCL
- T
CLQOV
(82188 max)
(125 ns)
b
50
T
CLQOV
(82188 min)
5
t
T
QIVCL
(82188 min)
t
15 ns
t
T
QVCL
t
10 ns
t
T
CLQX
(8087 min)
t
5 ns
,setup to 82188
,setup to 8087
,hoId to 8087
2315903
Figure 4 Queue Status Timing
5
AP-258
53 Bus Control Signals
When the 80186 is in Queue Status mode, anothei com-
ponent must geneiate the ALF, RD, and WR signaIs.
The 82188 piovides these signaIs by monitoiing the
CPU bus cycIe status (S0S2). AIso piovided aie DFN
and DT/R which may be used foi extia diive capabiIity
on the contioI bus. With the exception of ALF, aII con-
tioI signaIs on the 82188 aie aImost identicaI to theii
coiiesponding 80186 contioI signaIs. This section dis-
cusses the diffeiences between the 80186 and the 82188
contioI signaIs foi the puipose of upgiading an 80186
design to an 801868087 design. Foi oiiginaI 80186
8087 designs, theie is no need to compaie contioI signaI
timings of the 82188 with the 80186.
531 ALE
The ALF (Addiess Latch FnabIe) signaI goes active
one cIock phase eaiIiei on the 80186 than on the 82188.
Timing of the ALF signaI on the 82188 is cIosei to that
of the 8086 and 8288 bus contioIIei because the bus
cycIe status is used to geneiate the ALF puIse. ALF on
the 80186 goes active befoie the bus cycIe status Iines
aie vaIid.
The inactive edge of ALF occuis in the same cIock
phase foi both the 80186 and the 82188. The setup and
hoId times of the 80186 addiess ieIative to the 82188
ALF signaI aie shown in Figuie 5 and aie caIcuIated
foi an 8 MHz system as foIIows:
NOTE
The hoId time caIcuIation is the same foi both the
80186 and 8087.
These timings piovide adequate setup and hoId times
foi a 74LS373 addiess Iatch.
2315904
Figure 5 Address Latch Timings
Setup Time
Foi 80186
e
T
AVCH
(186 min)
a
T
CHLL
(82188 min)
e
10
a
0
e
10 ns.
Foi 8087
e
0.5 (T
CLCL
)
b
T
CLAV
(8087 max)
a
T
CHLL
(82188 min)
e
0.5 (125)
b
55
a
0
e
7.5
HoId Time
e
0.5 (T
CLCL
)
b
T
CHLL
(82188 max)
a
T
CLAZ
(186 min)
e
0.5 (125)
b
30
a
10
e
42.5 ns.
6
AP-258
T
CLRL
e T
CLML
e T
CVCTV
e 10 to 70 ns 2315905
T
CLRH
e T
CLMH
e 10 to 55 ns
T
CVCTX
e 5 to 55 ns
Figure 6 Read and Write Timings
532 Read and Write
The iead and wiite signaIs of the 82188 have identicaI
timings to those of the 80186 with one exception: the
82188 WR inactive edge may not go inactive quite as
eaiIy as the 80186. This spec is, in fact, a tightei spec
than the 80186 WR timing and shouId make designs
easiei. The timings foi RD and WR aie shown in Fig-
uie 6 foi both the 80186 and the 82188.
533 DEN
The DFN signaI on the 82188 is identicaI to the DFN
signaI on the 80186 but with a tightei timing specifica-
tion. This makes designs easiei with the 82188 and
makes upgiades fiom 80186 bus contioI to 82188 bus
contioI moie stiaightfoiwaid. The timings foi DFN on
both the 80186 and 82188 aie shown in Figuie 7.
534 DTR
The opeiation of the DT/R signaI vaiies somewhat be-
tween the 80186 and the 82188. The 80186 DT/R sig-
naI wiII iemain in an active high state foi aII wiite cy-
cIes and wiII defauIt to a high state when the system bus
is idIe (i.e., no bus activity). The 80186 DT/R goes Iow
onIy foi iead cycIes and does so onIy foi the duiation of
the bus cycIe. At the end of the iead cycIe, assuming
the foIIowing cycIe is a non-iead, the DT/R signaI wiII
defauIt back to a high state. Back-to-back iead cycIes
wiII iesuIt in the DT/R signaI iemaining Iow untiI the
end of the Iast iead cycIe.
The DT/R signaI on the 82188 opeiates diffeientIy by
making tiansitions onIy at the stait of a bus cycIe. The
82188 DT/R signaI has no defauIt state and theiefoie
wiII iemain in whichevei state the pievious bus cycIe
iequiied. The 82188 DT/R signaI wiII onIy change
states when the cuiient bus cycIe iequiies a state diffei-
ent fiom the pievious bus cycIe.
2315906
T
CVCTV
e 10 to 70 - clock edge to DEN activeinactive
T
CVDEX
e 10 to 70 - falling edge of T4 to DEN inactive
T
CHDNV
e 10 to 55 - rising edge of clock to DEN active
T
CHDNX
e 10 to 55 - clock edge to DEN inactive
Figure 7 Data Control Timings
7
AP-258
T
CLDTV
e 0 to 55 ns 2315907
Figure 8 Data Transmit Receive Timings
54 Chip Selects
541 INTRODUCTION
Chip-seIect ciicuitiy is typicaIIy accompIished by using
a disciete decodei to decode two oi moie of the uppei
addiess Iines. When a vaIid addiess appeais on the ad-
diess bus, the decodei geneiates a vaIid chip-seIect.
With this method, any bus mastei capabIe of pIacing an
addiess on the system bus is abIe to geneiate a chip-se-
Iect. An exampIe of this is shown in Figuie 9 wheie an
8086/8087 system uses a common decodei on the ad-
diess bus. Note the decodei is abIe to opeiate iegaidIess
of which piocessoi is in contioI of the bus.
2315908
Figure 9 Typical 80868087 System
With high integiation piocessois Iike the 80186 and
80188, the chip-seIect decodei is integiated onto the
piocessoi chip. The integiated chip-seIects on the
80186 enabIe diiect piocessoi connection to the chip-
enabIe pins on many memoiy devices, thus eIiminating
an exteinaI decodei. But because the integiated chip-se-
Iects decode the 80186s inteinaI bus, an exteinaI bus
mastei, such as the 8087, is unabIe to activate them.
The 82188 IBC soIves this piobIem by suppIying a
chip-seIect mechanism which may be activated by both
the host piocessoi and a second piocessoi.
542 CSI AND CSO OF THE 82188
The CSI (chip seIect in) and CSO (chip seIect out) pins
of the 82188 piovide a way foi a second bus mastei to
seIect memoiy whiIe aIso making use of the 80186 inte-
giated chip-seIects. The CSI pin of the 82188 connects
diiectIy to one of the 80186s chip-seIects whiIe CSO
connects to the memoiy device designated foi the chip-
seIects iange. An exampIe of this is shown in Figuie 10.
2315909
Figure 10 Typical 80186821888087 System
8
AP-258
When the 80186 has contioI of the bus, the ciicuit acts
just as a buffei and the memoiy device gets seIected as
if the ciicuit had not been theie. Whenevei CSI goes
active, CSO goes active. When a second bus mastei,
such as the 8087, takes contioI of the bus, CSO goes
active and iemains active untiI the 8087 passes contioI
back to the piocessoi. At this time CSO is deactivated.
A functionaI bIock diagiam of the CSICSO ciicuit is
shown in Figuie 11. A giant puIse on the RQ/OT0 Iine
gives contioI to the 8087 and aIso causes the
8087CONTROL signaI to go active, which in tuin
causes CSO to go active. The 8087CONTROL signaI
goes inactive when eithei a ieIease is ieceived on
RQ/OT0, indicating that the 8087 is ieIinquishing con-
tioI to the main piocessoi, oi a giant is ieceived on the
RQ/OT1 Iine, indicating that the 8087 is ieIinquishing
contioI to a thiid piocessoi. Both actions signify that
the 8087 is ieIinquishing the bus. If CSO goes inactive
because a thiid piocessoi took contioI of the bus, then
CSO wiII go active again foi the 8087 when a ieIease
puIse is tiansmitted on the RQ/OT1 Iine to the 8087.
This ieIease puIse occuis as a iesuIt of SYSHLDA go-
ing inactive fiom the thiid piocessoi.
543 SYSTEM DESIGN EXAMPLE
To piovide the 8087 access to data in Iow memoiy
thiough an integiated chip-seIect, the LCS pin shouId
be disconnected fiom the bank that it is cuiientIy se-
Iecting and fed diiectIy into the 82188 CSI. The CSI
output shouId be connected to the banks which the
LCS foimeiIy seIected. The LCS wiII stiII seIect the
same banks because CSO goes active whenevei CSI
goes active. But now the 8087, when taking contioI of
the bus, may aIso seIect these banks.
Caie must be taken in Iocating the 8087 data aiea be-
cause it must ieside in the aiea in which the chip-seIect
is defined. If the 8087 geneiates an addiess outside of
the LCS iange, the CSO wiII stiII go active, but the
addiess wiII eiioneousIy seIect a pait of the Iowei bank.
Note aIso that this chip-seIect Iimits the size of the 8087
data aiea to the maximum size memoiy which can be
seIected with one chip-seIect. Howevei, this does not
pIace a Iimit on instiuction code size oi non-8087 data
size. AII 80186 and 8087 instiuctions aie fetched by the
piocessoi and theiefoie do not iequiie that the 8087 be
23159010
Figure 11 82188 Chip Select Circuitry
9
AP-258
abIe to addiess them. Likewise, non-8087 data is nevei
accessed by the 8087 and theiefoie does not iequiie an
8087 chip-seIect.
55 Wait State Ready Logic
The 8087 must accuiateIy tiack eveiy instiuction fetch
the 80186 peifoims so that each op-code may be iead
fiom the system bus by the 8087 in paiaIIeI with the
piocessoi. This means that foi instiuction code aieas,
the 80186 cannot use inteinaIIy geneiated wait states.
AII ieady Iogic foi these aieas must be geneiated extei-
naIIy and sent into the 82188. The 82188 then piesents
a synchionous ieady out (SRO) signaI to both the
80186 and the 8087.
551 INTERNAL WAIT STATES WITH
INSTRUCTION FETCHES
If inteinaI wait states aie used by the piocessoi with the
8087 at zeio wait states, then the 8087 wiII Iatch op-
codes using a foui cIock bus cycIe whiIe the piocessoi is
using between five and seven cIocks on each bus cycIe.
If the wait states aie tiuIy necessaiy to Iatch vaIid data
fiom memoiy, then a foui cIock bus cycIe wiII foice the
8087 to Iatch invaIid data. The invaIid data may then be
possibIy inteipieted to be an FSCAPF piefix when, in
ieaIity, it is not. The ieveise may aIso hoId tiue in that
the 8087 may not iecognize an FSCAPF piefix when it
is fetched. These conditions couId cause a system to
hang (i.e., cease to opeiate), oi opeiate with eiioneous
iesuIts.
If the memoiy is fast enough to aIIow Iatching of vaIid
data within a foui cIock bus cycIe, then the 80186 intei-
naI wait states wiII not cause the system to hang. Both
piocessois wiII ieceive vaIid data duiing theii iespec-
tive bus cycIes. The 8087 wiII finish its bus cycIe eaiIiei
than the piocessoi, but this is of no consequence to
system opeiation. The 8087 wiII synchionize with the
piocessoi using the status Iines S0S2 at the stait of the
next instiuction fetch.
552 INTERNAL WAIT STATES WITH DATA
IO CYCLES
With the exception of Dummy Read CycIes and in-
stiuction fetches, aII memoiy and I/O bus cycIes exe-
cuted by the host piocessoi aie ignoied by the 8087.
Copiocessoi synchionization is not iequiied foi un-
tiacked bus cycIes and, theiefoie, inteinaIIy geneiated
wait states do not affect system opeiation. AII of the
I/O space and any pait of memoiy used stiictIy foi
data may use the inteinaI wait state geneiatoi on the
80186.
Memoiy used foi 8087 data is somewhat diffeient.
Heie, as in the case of code segment aieas, the system
must ieIy on an exteinaI ieady signaI oi eIse the memo-
iy must be fast enough to suppoit zeio wait state opeia-
tion. Without an exteinaI ieady signaI, the 8087 wiII
aIways peifoim a foui cIock bus cycIe which, when
used with sIow memoiies, iesuIts in the Iatching of in-
vaIid data.
InteinaI wait states wiII not affect system opeiation foi
data cycIes peifoimed by the 8087. In this case the 8087
has contioI of the bus and the two piocessois opeiate
independentIy.
One type of data cycIe has not yet been consideied.
Fach time a numeiics vaiiabIe is accessed, the host
piocessoi iuns a Dummy Read CycIe in oidei to
caIcuIate the opeiand addiess foi the 8087. The 8087
Iatches the addiess and then takes contioI of the bus to
fetch any subsequent bytes which aie necessaiy. If the
8087 vaiiabIes aie Iocated at even addiesses, then an
inteinaIIy geneiated wait state wiII not piesent any
piobIems to the system. If any numeiic vaiiabIes aie
Iocated at odd addiesses, then the inteiface between the
host and copiocessoi becomes asynchionous causing
eiioneous iesuIts.
The eiioneous iesuIts aie due to the 80186 iunning two
back-to-back bus cycIes with wait states whiIe the 8087
iuns two back-to-back bus cycIes without wait states.
The stait of the second bus cycIe is compIeteIy uncooi-
dinated between the two piocessois and the 8087 is un-
abIe to Iatch the coiiect addiess foi subsequent tians-
feis. Foi this ieason, 8087 vaiiabIes in a 80186 system
must aIways Iie on even boundaiies when using the in-
teinaI wait state geneiatoi to access them.
Numeiic vaiiabIes in an 80188 system must nevei be in
a section of memoiy which uses the inteinaI wait state
geneiatoi. The 80188 wiII aIways peifoim consecutive
bus cycIes which wouId be equivaIent to the 80186 pei-
foiming an odd addiessed Dummy Read CycIe.
553 AUTOMATIC WAIT STATES AT RESET
The 80186 automaticaIIy inseits thiee wait states to the
piedefined uppei memoiy chip seIect iange upon powei
up and ieset. This enabIes designeis to use sIow memo-
iies foi system boot ROM if so desiied. If sIow ROMs
aie chosen, then no fuithei piogiamming is necessaiy.
If fast ROMs aie chosen, then the wait state Iogic may
simpIy be iepiogiammed to the appiopiiate numbei of
wait states.
The automatic wait states have the possibiIity of pie-
senting the same piobIem as desciibed in section 5.5.1 if
10
AP-258
the boot ROM needs one oi moie wait states. Undei
these conditions the 8087 wouId be foiced to Iatch in-
vaIid opcodes and possibIy mistake one foi an FSCAPF
instiuction.
If the boot ROM iequiies wait states, then some soit of
exteinaI ieady Iogic is necessaiy. This aIIows both pioc-
essois to iun with the same numbei of wait states and
insuies that they aIways ieceive vaIid data.
If the boot ROM does not iequiie wait states, then
theie is no need to design exteinaI ieady Iogic foi the
uppei chip seIect iegion. But if 8087 code is piesent in
the uppei memoiy chip seIect iegion, the situation de-
sciibed in section 3.4 iegaiding Dummy Read CycIes
must be consideied.
The 82188 soIves this piobIem by inseiting thiee wait
states on the SRO Iine to the 8087 foi the fiist 256 bus
cycIes. By doing this the 82188 inseits the same numbei
of wait states to both piocessois keeping them synchio-
nized. The initiaIization code foi the 80186 must pio-
giam the uppei memoiy chip seIect to Iook at exteinaI
ieady and to inseit zeio wait states within these fiist
256 bus cycIes. At the end of the 256 bus cycIes, the
82188 stops inseiting wait states and both piocessois
iun at zeio wait states.
554 EXTERNAL READY SYNCHRONIZATION
The 80186 and 8087 sampIe RFADY on diffeient cIock
edges. This impIies that some soit of exteinaI synchio-
nization is iequiied to insuie that both piocessois sam-
pIe the same ieady state. Without the synchionization,
it wouId be possibIe foi the exteinaI signaI to change
state between sampIes. The 80186 may sampIe ieady
high whiIe the 8087 sampIes ieady Iow. This wouId Iead
to the two piocessois iunning diffeient Iength bus cy-
cIes and possibIy cause the system to hang.
The 82188 piovides ieady synchionization thiough the
ARDY and SRDY inputs. Once a vaIid tiansition is
iecoided, the 82188 piesents the iesuIts on the SRO
output and hoIds the output in that state untiI both
piocessois have had a chance to sampIe the signaI.
56 BUS ARBITRATION
In oidei foi the 8087 to iead and wiite numeiic data to
and fiom memoiy, it must have a means of taking con-
tioI of the IocaI bus. With the 8086/88 this is accom-
pIished thiough a iequest-giant exchange piotocoI. The
80186, howevei, makes use of HOLD/HOLD AC-
KNOWLFDOF piotocoI to exchange contioI of the
bus with anothei piocessoi. The 82188 suppIies the
necessaiy conveision to inteiface RQ/OT to HOLD/
HLDA signaIs. The RQ/OT signaI of the 8087 con-
nects diiectIy to the 82188s RQ/OT0 input whiIe the
82188s HOLD and HLDA pins connect to the 80186s
HOLD and HLDA pins.
When the 8087 iequiies contioI of the bus, the 8087
sends a iequest on the RQ/OT0 Iine to the 82188. The
82188 iesponds by sending a HOLD iequest to the
80186. When HLDA is ieceived back fiom the 80186,
the 82188 sends a giant back to the 8087 on the same
RQ/OT0 Iine.
The 82188 aIso has piovisions foi adding a thiid bus-
mastei to the system which uses HOLD/HLDA pio-
tocoI. This is accompIished by using the 82188
SYSHOLD, SYSHLDA, and RQ/OT1 signaIs.
The thiid piocessoi iequests the bus by puIIing the
SYSHOLD Iine high. The 82188 wiII ioute (and tians-
Iate if necessaiy) the iequests to the cuiient bus mastei.
If the 8087 has contioI, the 82188 wiII iequest contioI
via the RQ/OT1 Iine which shouId be connected to the
8087s RQ/OT1 Iine.
The 8087 wiII ieIinquish contioI by getting off the bus
and sending a giant puIse on the RQ/OT1 Iine. The
82188 iesponds by sending a SYSHLDA to the thiid
piocessoi. The thiid piocessoi Ioweis SYSHOLD when
it has finished on the bus. The 82188 ioutes this in the
foim of a ieIease puIse on the RQ/OT1 Iine to the
8087. The 8087 then continues bus activity wheie it Ieft
off. The maximum Iatency fiom SYSHOLD to
SYSHLDA is equaI to the 80186 Iatency
a
8087 Iaten-
cy
a
82188 Iatency.
57 SPEED REQUIREMENTS
One of the most impoitant timing specs associated with
the 80186-8087 inteiface is the speed at which the sys-
tem shouId iun. The 8087 was designed to opeiate with
a 33% duty cycIe cIock wheieas the 80186 and 80188
weie designed to opeiate with a 50% duty cycIe cIock.
In oidei to iun both paits off the same cIock, the 8087
must iun at a sIowei speed than is typicaIIy impIied by
its dash numbei in the 8086/88 famiIy.
11
AP-258
To deteimine the speed at which an 8087 may iun
(with a 50% duty cycIe cIock), the minimum Iow and
high times of the 8087 must be examined. The maxi-
mum of these two minimum specs becomes the haIf-pe-
iiod of the 50% duty cycIe system cIock. Foi exampIe,
the 8087-1 piovides woist case spec compatibiIity with
the 80186 at system cIock-speeds of up to 8 MHz. The
cIock wavefoims aie shown in Figuie 12 using 10 MHz
timings.
The minimum cIock Iow time spec (T
CLCH
) of the 10
MHz 8087 is 53 ns. The cIock Iow time of an 8 MHz
80186 is specified to be:
(T
CLCL
) b 75
SoIving foi T
CLCL
of the 80186 using T
CLCH
of the
8087 yieIds the foIIowing:
(T
CLCL
) b 75 e T
CLCH
(T
CLCL
) e 2(T
CLCH
a 75)
T
CLCL
e 121 ns
The caIcuIation shows minimum cycIe time of the
80186 to be 121 ns. This time tiansIates into a maxi-
mum fiequency of 8.26 MHz.
60 BENCHMARKS
61 Introduction
The foIIowing benchmaiks compaie the oveiaII system
peifoimance of an 8086, 80188, and an 80186 in nu-
meiic appIications. ResuIts aie shown foi aII thiee
piocessois in systems with the 8087 copiocessoi and
in systems using an 8087 softwaie emuIatoi. Thiee
FORTRAN benchmaik piogiams aie used to dem-
onstiate the Iaige inciease in fIoating-point math pei-
foimance piovided by the 8087 and aIso the inciease in
peifoimance due to the enhanced 80186 and 80188 host
piocessois.
The 8086 iesuIts weie measuied on an InteIIec Seiies
III Miciocomputei DeveIopment System with an iSBC
86/12 boaid and an iSBC 337 muItimoduIe. TypicaIIy,
one wait state foi memoiy iead cycIes and two wait
states foi memoiy wiite cycIes aie expeiienced in this
enviionment.
The 80186 and 80188 iesuIts weie measuied on a pioto-
type boaid which aIIowed zeio wait state opeiation at
8 MHz. The benchmaiks measuied using the 8087
showed IittIe sensitivity to wait states. Instiuctions exe-
cuted on the 8087 tend to be Iong in compaiison to the
amount of bus activity iequiied and, theiefoie, aie not
affected much by wait states.
The benchmaiks measuied using the softwaie emuIatoi
aie much moie bus intensive and aveiage fiom 10 to 15
peicent peifoimance degiadation foi one wait state.
AII execution times shown heie iepiesent 8 MHz opei-
ation. The 8086 iesuIts weie measuied at 5 MHz and
extiapoIated to achieve 8 MHz execution times.
62 Interest Rate Calculations
Routines weie wiitten in FORTRAN-86 to caIcuIate
the finaI vaIue of a fund given the annuaI inteiest and
the piesent vaIue. It is assumed that the inteiest wiII be
compounded daiIy, which iequiies the caIcuIation of
the yeaiIy effective iate. This vaIue, which is the equiv-
aIent annuaI inteiest if the inteiest weie compounded
daiIy, is deteimined by the foIIowing foimuIa:
yer e (1 a (irnp))np b 1
23159011
Figure 12 Clock Cycle Timing
12
AP-258
wheie:
yei is the yeaiIy effective iate
ii is the annuaI inteiest iate
np is the numbei of compounding peiiods pei
annum
Once the yei is deteimined, the finaI vaIue of the fund
is deteimined by the foimuIa:
fv e (1 ayer) pv
wheie:
pv is the piesent vaIue
fv is the futuie vaIue
ResuIts aie obtained using singIe-piecision, doubIe-pie-
cision, and tempoiaiy ieaI piecision opeiands when:
ii is set to 10% (0.1)
np is set to 365 (foi daiIy compounding)
pv is set to $2,000,000
THF RFSULTS:
yer Final Value
Single-Precision 10514% $221028750
(32-bit)
Double-Precision 10516% $221031157
(64-bit)
Temporary Real 10516% $221031157
Precision
The diffeience between the finaI singIe-piecision and
doubIe-piecision vaIues is $24.07, the diffeience in the
finaI vaIue between the doubIe-piecision and the tempo-
iaiy ieaI piecision is 0.000062 cents. Since the 8087
peifoims aII inteinaI caIcuIations on 80-bit fIoating
point numbeis (temp ieaI foimat), tempoiaiy ieaI pie-
cision opeiations peifoim fastei than singIe- oi doubIe-
piecision. No data conveisions aie iequiied when Ioad-
ing oi stoiing tempoiaiy ieaI vaIues in the 8087. Thus,
foi business appIications, the doubIe-piecision comput-
ing of the 8087 is essentiaI foi accuiate iesuIts, and the
peifoimance advantage of using the 8087 tuins out to
be as much as 100 times the equivaIent softwaie emuIa-
tion piogiam.
63 Matrix Multiply Benchmark
Routine
A ioutine was wiitten in FORTRAN-86 to compute
the pioduct of two matiices using a simpIe iow/coIumn
innei-pioduct method. Fxecution times weie obtained
foi the muItipIication of 32
c
32 matiices using doubIe
piecision. The iesuIts of the benchmaik aie shown in
Figuie 14.
The iesuIts show the 8087 copiocessoi systems pei-
foiming fiom 23 to 31 times fastei than the equivaIent
softwaie emuIation piogiam. Both the 80188/87 and
the 80186/87 systems outpeifoim the 8086/87 system
by 34 to 75 peicent. This diffeience is mainIy attiibuted
to the fact that the matiix piogiam IaigeIy consists of
effective addiess caIcuIations used in aiiay accessing.
The haidwaie effective addiess caIcuIatoi of the 80186
and 80188 aIIow each aiiay access to impiove by as
much as thiee times the 8086 effective addiess caIcuIa-
tion.
64 Whetstone Benchmark Routine
The Whetstone benchmaik piogiam was deveIoped by
Haiiy Cuinow foi the CentiaI Computei Agency of the
Biitish goveinment. This benchmaik has ieceived high
visibiIity in the scientific community as a measuiement
of main fiame computei peifoimance. It is a synthet-
ic piogiam. That is, it does not soIve a ieaI piobIem,
but iathei contains a mix of FORTRAN statements
which iefIect the fiequency of such statements as mea-
suied in ovei 900 actuaI piogiams. The piogiam com-
putes a peifoimance metiic: thousands of Whetstone
instiuctions pei second (KIPS).
SimpIe vaiiabIe and aiiay addiessing, fixed- and fIoat-
ing- point aiithmetic, subioutine caIIs and paiametei
passing, and standaid mathematicaI functions aie pei-
foimed in eIeven sepaiate moduIes oi Ioops of a pie-
sciibed numbei of iteiations.
Table 2 Interest Rate Benchmark Results
8087 Software Emulator 8087 Coprocessor
80188 8086 80186 80188 8086 80186
Single Precision 703 ms 628 ms 434 ms 70 ms 66 ms 61 ms
Double Precision 721 ms 629 ms 444 ms 71 ms 66 ms 61 ms
Temp Real Precision 726 ms 630 ms 448 ms 69 ms 65 ms 59 ms
Average 717 ms 629 ms 442 ms 70 ms 66 ms 60 ms
13
AP-258
The oiiginaI coding of the Whetstone benchmaik was
wiitten in AIgoI-60 and used singIe-piecision vaIues. It
was iewiitten in FORTRAN with singIe-piecision vaI-
ues to exactIy iefIect the oiiginaI intent. Anothei vei-
sion was cieated using doubIe-piecision vaIues. The ie-
suIts aie shown in TabIe 3.
The iesuIts show the 8087 systems with the 80186 and
80188 outpeifoiming the equivaIent softwaie emuIation
by 60 to 83 times. AdditionaIIy, the 80186 coupIed with
the 8087 outpeifoimed the 8086/87 system by 22 pei-
cent.
23159012
Figure 13 Interest Rate Benchmark Results
23159013
Figure 14 Double Precision Matrix Multiplication
14
AP-258
Table 3 Whetstone Benchmark Results
Units
e
KIPS
8087 Software Emulator 8087 Coprocessor
80188 8086 80186 80188 8086 80186
Single
2 23 33 1658 1780 1976
Precision
Double
2 22 32 1517 1520 1852
Precision
65 Benchmark Conclusions
These benchmaiks show that the 8087 Numeiic Data
Copiocessoi, coupIed with eithei the 80186 oi the
80188, can inciease the peifoimance of a numeiic ap-
pIication by 75 to 100 times the equivaIent softwaie
emuIation piogiam.
AppIications which iequiie aiiay accessing with effec-
tive addiess caIcuIations wiII benefit even moie by us-
ing the 80188 and 80186 as the host piocessoi as com-
paied to the 8086. The iesuIts of the matiix muItipIica-
tion show both the 80188 and 80186 outpeifoiming the
8086 by 34 and 75%, iespectiveIy, in an 8087 system.
In geneiaI, an 80186/8087 system wiII offei a 10% to a
75% impiovement ovei an equivaIent 8086/8087 sys-
tem, depending on the instiuction mix.
70 CONCLUSION
Foi contioIIei appIications which iequiie high peifoim-
ance in numeiics and Iow system cost, the 16-bit 80186
oi 8-bit 80188 coupIed with the 8087 offeis an ideaI
soIution. The integiated featuies of the 80186 and
80188 offei a Iow system cost thiough ieduced boaid
space and a simpIified pioduction fIow whiIe the 8087
fuIfiIIs the peifoimance iequiiements of numeiic appIi-
cations.
The 82188 IBC piovides a stiaightfoiwaid, highIy inte-
giated soIution to inteifacing the 80188 oi 80186 to the
8087. The bus contioI timings of the 82188 aie compat-
ibIe with the 80186 and 80188, aIIowing easy upgiades
fiom existing designs. The 82188 featuies piesent a
highIy integiated soIution to both new and oId designs.
The copiocessing capabiIities of the 8087 biing pei-
foimance impiovements of 75 to 100 times the equiva-
Ient 80186 oi 80188 softwaie emuIation piogiam and
an 80186/8087 system wiII offei a 10% to a 75% im-
piovement ovei an equivaIent 8086/8087 system de-
pending on the instiuction mix.
In addition a giowing base of high-IeveI Ianguage sup-
poit (FORTRAN, PascaI, C, Basic, PL/M, etc.) fiom
InteI and numeious thiid-paity softwaie vendois faciIi-
tates the timeIy and efficient geneiation of appIication
softwaie.
REFERENCES
82188 Data Sheet 231051
80186 Data Sheet 210451
80188 Data Sheet 210706
iAPX 86/88 80186/188 Useis ManuaI
Piogiammeis Refeience 210911
Haidwaie Refeience 210912
AP-113 Oetting Staited with the
Numeiic Data Piocessoi 207865
15
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INTEL CORPORATION (UK) Ltd Swindon United Kingdom Tel (0793) 696 000
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Microprocessors