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Pseudo Random Sequence Generator
Pseudo Random Sequence Generator
Spring 2008
jeg
clk
The code given below for the 7-bit shift register will work as a template for shift registers of other sizes.
ENTITY PRSG7 IS PORT( CLK : IN BIT; Q : BUFFER BIT_VECTOR (7 DOWNTO 1) ); END ENTITY PRSG7; ARCHITECTURE BEHAVIORAL OF PRSG7 IS BEGIN PROCESS(Q,CLK) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q <= Q(6 DOWNTO 1) & (Q(7) XNOR Q(6)); ELSE Q <= Q; END IF; END PROCESS; END ARCHITECTURE BEHAVIORAL;
The PLDT-2 boards come with a 4 MHz clock oscillator as the standard global clock. Table 1 list the time it will take the sequence to repeat for the 4 MHz clock oscillator. It is assumed that one would allow the pseudo random sequence generator to run continuously, and then pick different taps to generate the smaller bit patterns to cause random events to take place in the design.
Spring 2008
jeg
Units us ns ns us us us us us us ms ms ms ms ms ms ms ms ms ms s s s s s s m m m m m
3,2 4,3 5,3 6,5 7,6 8,6,5,4 9,5 10,7 11,9 12,6,4,1 13,4,3,1 14,5,3,1 15,14 16,15,13,4 17,14 18,11 19,6,2,1 20,17 21,19 22,21, 23,18 24,23,22,17 25,22 26,6,2,1 27,5,2,1 28,25 29,27 30,6,4,1 31,28 32,22,2,1