PROCESSOR BOARD (VIDEO CONTROLLER) SCHEMATIC

757-039-11

REV A

PAGE 4 OF 11

U2

A25\

9
R56
2
10K

IA1
IA2
IA3
A4
A5
A6

51
50
49
48
47
46

A0
A1
A2
A3
A4
A5

4
52
3
45
6
5
38

RDN
WRN
CEN
IQRN
IACKN
DACKN
RESET

42

X1/CLK

VCC

R87

10K

INT0\

(1,2)

TP

RESET QUART

(1,9)

QUART CLK

(1,2)

E15

41

TP

INT3\

(1,2)

OUT CLK
RESET\

#2

VSS
VSS

RXDA
TXDA
IO0A
IO1A
IO2A
IO3A

19
20
27
26
25
24

RXDB
TXDB
IO0B
IO1B
IO2B
IO3B

8
7
23
22
21
16

RXDC
TXDC
IO0C
IO1C
IO2C
IO3C

36
37
29
30
31
32

RXDD
TXDD
IO0D
IO1D
IO2D
IO3D

44
43
33
34
35
39

VSS
VSS

RXDA2
TXDA2

J2,4A

SPEAKERA+

J2,3A

(1,11)

J5,21C

MM AUDIO1

28
40
TXDB2
TXDC2
TXDD2

RESET CPU/SEN/AUD

+25VDC
VCC

+13VDC

1
1N914

Q7

2N3904
1

R198

DATA
N/C
GND
GND

U87B
R199

6
5

3
4

R185

CR18

E11

TP

X2

1
14

VSS
VSS

8
7
23
22
21
16

R117

RXDC
TXDC
IO0C
IO1C
IO2C
IO3C

36
37
29
30
31
32

RXDD
TXDD
IO0D
IO1D
IO2D
IO3D

44
43
33
34
35
39

VSS
VSS

28
40

AI
BI
CI
DI
EI
FI

3
5
7
9
11
14

16
8

VOUT
VSS

MODE
VC

13
1

+13VDC

R118
1K

100K
1
2
3
4
4
3

RP24

100K

2.4K
ILD2

3
5
7
9
11
14

AO
BO
CO
DO
EO
FO

AI
BI
CI
DI
EI
FI

MODE
VC
VOUT
VSS

TxDa
RxDa
DTR

13

RP12
10
5

1
2
3
4
6
7
8
9

RXDA1
IO0A1
RXDB1
RXDC1
IO0C1

IO2C1

TP

10K

VDD
U2

U76

U62

U78

U60

U78

U20

U79

C24

C26

C61

C76

C112

C105

C6

C101

C53

0.1uF

C113
0.1uF

C124
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

22uF

C70
+

0.1uF
2

74HC14

2
1

1
A

VSS

R181

R55
1

10K
2

U18D
8

1K

TP

74HC14

22

(1,9)
(1,9)
Max. rate = 115.2kb/s

J1,4B
J1,3B

(1)
(1)

J1,4A

(1)

J1,5B
J1,5A

(1)
(1)
Max. rate = 19.2kb/s

C103
RP19

TxDb
RxDb
RP20

J2,16A
J2,16B

(1)
(1)

MICROTOUCH / SPARE

10K

AI
BI
CI
DI
EI
FI

3
5
7
9
11
14

16
8

VOUT
VSS

MODE
VC

13
1

RP21
8
7
6
5
2
1

100K
1
2
3
4
3
4

Max. rate = 9.6kb/s

RP18

100K

+13VDC

COMM TxDc
COMM RxDc
COMM CTS
COMM RTS

4504
MODE

J2,14A

(1)

J2,14B
J2,15B
J2,15A

(1)
(1)
(1)

RS232 DATA
COLLECTION
INPUT
LEVEL

Max. rate = 19.2kb/s

OUTPUT
LEVEL

1 (VCC)

TTL

CMOS

0 (VSS)

CMOS

CMOS
A

470
ILD2

AO
BO
CO
DO
EO
FO

U30

U77

Q5

R175

1
U18C
1

2
4
6
10
12
15

VCC

1N914

3
4

(1,8.9)
(1,8.9)
(1,8,9)
(1,8.9)

16
8

10K

2
3

VCC
U86B

(1,5)

RS485

4504

POWER SAVE

CR12

DCD
DIR

+13VDC

0.1uF

2N3904

U44

6
5

(1)

PAD

2
4
6
10
12
15

4504

2N3904
1

J2,13B

CHOPPED AC IN
(LOW VOLTAGE)

SCLK256

U80

VCC

J1,3A

+13VDC

U76
TXDA1
IO2A1
IO3A1
TXDB1
TXDC1

R208
220

(1)

(1)

JACKPOT RESET DETECT

RxDd
TxDd

150

+13VDC

Max. rate = 38.4kb/s

J2,7A

ON BOARD F/O
COMMUNICATIONS

74HC125

R78
10K
Q4

(1)
(1)

74HC125

R211

J2,12A
J2,12B

JKPT RST

8
7
6
5
2
1

7
8

TELL TALE

2
1

DCS TxDh
DCS RxDh

DATA COLLECTION
SYSTEM (IGT)

E14

SNOUT

2
2

(1)
(1)
Max. rate = 4800b/s

RP22

SIN IN

11

VCC
U86A

J2,8A
J2,8B

PROGRESSIVE
COMMUNICATIONS

RP23
10K

RP25
8
7
6
5
1
2

VCC

R217

PROG TxDg
PROG RxDg

16
8

12

(1)
(1)
Max. rate = 19.2kb/s

TT-CNTR1
TT-CNTR2
TT-DISABLE\
TT-DET\

13
1
5

VCC

J2,10B
J2,9A

SPARE F/O

U62D

R200
220

TxDf
RxDf

10K

AO
BO
CO
DO
EO
FO

(1)

SENET CYCLE DONE

U62B
2

J2,13A

+13VDC RESET\
TP

C126
0.1uF

2
4
6
10
12
15

(1)

TP

4504

VCC

41

RXDB
TXDB
IO0B
IO1B
IO2B
IO3B

SC26C94

4.7K
1

MODE
VC
VOUT
VSS

R170
1K

VCC

SNIN

VCC

Q8
1

X1/CLK

74HC125

ILD2

220

1N914

42

19
20
27
26
25
24

SILICON
SERIAL
NUMBER

TxDe

10

750
2N3904

1
3
2
4

#1

RXDA
TXDA
IO0A
IO1A
IO2A
IO3A

DS2401Z

2
U62C

NETPLEX TxD

TP

2.2K

NETPLEX RxD

RDN
WRN
CEN
IQRN
IACKN
DACKN
RESET

TP

220

J2,10A

4
52
3
45
6
5
38

RESET QUART

+13VDC

(1)

A0
A1
A2
A3
A4
A5

U61

R212

J2,11B

51
50
49
48
47
46

R197
220

(1)

IA1
IA2
IA3
A4
A5
A6

10K

IO2A1

D0
D1
D2
D3
D4
D5
D6
D7

CR17

2
1

R69

18
17
15
13
12
11
10
9

ILD2

I/O RESET\

U62A
74HC125

U87A
7
8

2
J2,11A

R225
10K

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

J2,9B

757 039 11

R226
220
R196
2.2K

(1)

VCC
2

PAGE 11

+13VDC

J2,1A,1B

IO0B2
RXDB2
RXDC2
RXDD2
IO2C2
IO0B1

(1,8,9)
(1,8,9)
(1,8,9)
(1,8,9)
(1,9)
(1,9)

DWG NO.

+25VDC

J1,18A,18B

R168
1K

U31

(1,5)
(1,5)

LIGHT PEN
SWITCH DETECT

SRESET\
2
4
6
10
12
15

4504

OUT CLK

MM AUDIO1

RESET\ CPU/SEN/AUD

TEST SWITCH
U77
3 AI
AO
5 BI
BO
7 CI
CO
9 DI
DO
11 EI
EO
14 FI
FO

U81

SPEAKER-

(1,6)
(1,8,9)

LPSW

10K

10K
VCC

SPEAKERA+

SPEAKER-

(1,2,5,9,11)

R84

RP15

IO WR

OUT CLK
(1,11)

OPTION

(1,3)

8
7
6
5
1
2

(1,11)

SOUND SEL

VCC

(1,5)

74HC175

PAD

(1,3,11)

IA1

(1,5)

OUT7

TO LEDs (DS5, DS6 & DS7)

CLK
CLR

S1

SOUND SEL\

10K
2

1
2

OUT SEL

E13

VCC
R11
1

(1,3,11)

OUT6

TP

MDOOR OPEN\
DDOOR OPEN\
BVAL OPEN\
CCAGE OPEN\
SRAM BAT LOW\
TT BAT LOW\

13
1
IA1

TP

TO LEDs (DS2 & DS3)

J9

VCC

OUT SEL\

SPARE
(1,5)

IO2B2
IO3B2

_11) Audio
PD[0..7]

PAD

OUT5

VERTOUT
INTERROGATE
SPARE I/O

VCC

9
1

TP

FWR EN\

SC26C94

RESET\ I/O

(1,9)

OPTIONAL

R63
1K

X2

1
14

D4

E1

TP

8
7
6
5

(1,3)

D3

13

2
3
7
6
10
11
15
14

1
2
3
4

QRT2 SEL\

D0
D1
D2
D3
D4
D5
D6
D7

12

PD7

Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4

1
2
3
4
4
3

QRT1 SEL\

(1,3)

18
17
15
13
12
11
10
9

U19C

(1,2,3,5,7,11)

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PD6

IO WR\

VCC

U45

IO RD\

(1,2,3,5,7)

PD[0..7]

(1,2,5,7,11)

D2

74AC32

10
1

(1,2,3,5,6,7,10)
D

VCC

A[1..31]

D1

1
2
3
4
3
4

IA[1..3]

PD5

(1,2)
(1,2,7,11)

PD4

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO

THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA, THIS
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO
BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED
BY OTHERS, IN PART OR IN WHOLE, WITHOUT THE EXPRESS
CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT
COVENANTS IT WILL NOT BE USED IN ANY MANNER
DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE
RETURNED ON DEMAND.
DRAW N

DATE

TDW

01NOV99

ELECTRONIC DIAGRAMS & PARTS: GAME KING 17 UPRIGHT (821-307-01)

CHECKED

DATE

INTERNATIONAL GAME TECHNOLOGY

9295 PROTOTYPE DRIVE RENO, NV 89511
TITLE

SCHEMATIC, GAME KING 2

PROTECT GAME KING CTR/TT
DW G. SIZE

DW G. NO.

REV LTR

757 039 11

APPROVED

DATE

SCALE

NONE

4 OF 11
SHT __
__

OCTOBER 15, 2001