Vic thc hnh thng xuyn s em li cho bn nhiu kinh nghim v k nng thit k.

Sau y, mnh xin trnh by cch thit k mt b truyn b t ng b theo chu n UART cc b n c th th c hin v th nghim trn KIT FPGA. (Ch , y ch l b truyn (transmitter) ch khng c nhn (receiver)) C th, mnh s thit k b truyn ni tip theo chun UART (Universal Asynchronous Receiver Transmitter) c cc c im nh sau: 1. Cu hnh c tc BAUD (tc truyn d liu) theo cng thc fosc/((BRG + 1)x16). Trong BRG l thanh ghi thit lp tc baud c rng 8 bit. 2. Khung d liu gm: 1 start bit, 8 bit d liu, 1 stop bit 3. 8 bit d liu cn truyn c gi tr t H00 n HFF s c chuyn i dng m ASCII trc khi truyn i. V d: D liu cn truyn l: H85 s c i thnh H38(l m ASCII ca s 8) v 35(l m ASCII ca s 5). Sau hai gi tr 38 v 35 s c truyn i qua ng truyn ni tip. Chng ta s bt u thc hin tng bc c c thit k mong mun nh sau: u tin, phn tch tng quan mc s kh i: V s tn hiu giao tip:

V s khi tng qut: Thit k c 4 khi c bn nh sau

Bc tip theo, mnh th c hin phn tch mc s cu to chi tit mc cng logic:

V khung truyn d liu: Khung truyn gm 1 bit START, 8 bit data, 1 bit STOP.

V cu to cc khi:

Da trn s chi tit ny bn c th thc hin vit RTL code cho thit k. Sau y l mch chi tit tng khi cc bn d quan st hn:

FSM (my trng thi ca khi TX_SERIAL_DATA)