This document provides a preliminary agenda for an upcoming event including the main sponsor and several lecturers who will speak on topics related to programmable SOC's, DDR3 interfacing design challenges, HEVC video codec, Java embedded on ARM architectures, video compression, power design for worst case scenarios, and more. Attendees can register for the event by contacting Liran Grushka for more information.
This document provides a preliminary agenda for an upcoming event including the main sponsor and several lecturers who will speak on topics related to programmable SOC's, DDR3 interfacing design challenges, HEVC video codec, Java embedded on ARM architectures, video compression, power design for worst case scenarios, and more. Attendees can register for the event by contacting Liran Grushka for more information.
This document provides a preliminary agenda for an upcoming event including the main sponsor and several lecturers who will speak on topics related to programmable SOC's, DDR3 interfacing design challenges, HEVC video codec, Java embedded on ARM architectures, video compression, power design for worst case scenarios, and more. Attendees can register for the event by contacting Liran Grushka for more information.
Subject Leading the way towards All Programmable SOCs
Xilinx, USA
Dr. Jrgen Wolde
CEO
IBW, Germany
DDR3 Interfacing Design Challenges and Solutions
Advanced modem-PHY implementation based on state-of-the-art FPGA and AFE components Will High Efficiency Video Codec (HEVC) kill SW video compression? Java Embedded on ARM What are the benefits?
Dr. Jaime Hasson
Senior Director Manager
Elbit systems
Mr. Ori Modai
CTO, Video Business Unit
Radvision
Mr. Benjamin Pashkoff
Principle Technology Consultant
Oracle
Mr. David Neter
General manager
Does SSN means worst case scenario in power design?
T.M.I
For more information and for submitting your registration form: Liran Grushka, 03-9247780 #107, Lirang@logtel.com