MOSFET Small-Signal Model

Concept: nd an equivalent circuit which interrelates the incremental changes in iD, vGS, vDS, etc. Since the changes are small, the small-signal equivalent circuit has linear elements only (e.g., capacitors, resistors, controlled sources) Derivation: consider for example the relationship of the increment in drain current due to an increment in gate-source voltage when the MOSFET is saturated-- with all other voltages held constant. vGS = VGS + vgs , iD = ID + id -- we want to find id = (?) vgs

We have the functional dependence of the total drain current in saturation: iD = n Cox (W/2L) (vGS - VTn )2 (1 + nvDS) = iD(vGS, vDS, vBS) Do a Taylor expansion around the DC operating point (also called the quiescent point or Q point) defined by the DC voltages Q(VGS, VDS, VBS): 1 iD ( v gs ) + -iD = I D + v GS 2 v2 Q GS i D
2

( v gs ) +
Q

If the small-signal voltage is really small, then we can neglect all everything past the linear term -i D iD = I D + ( v gs ) = I D + g m v gs v GS
Q

where the partial derivative is dened as the transconductance, gm.

EE 105 Spring 1997 Lecture 12

Transconductance
The small-signal drain current due to vgs is therefore given by id = gm vgs.

D G
+

iD = ID + id
+

vgs

B S

VDS = 4 V

_ +

VGS = 3 V_

600 500 iD 400 id Q gm = id / vgs vGS = VGS + vgs vGS = VGS = 3 V

(A) 300 200 100 1 2

6 VDS (V)

EE 105 Spring 1997 Lecture 12

Another View of gm
* Plot the drain current as a function of the gate-source voltage, so that the slope can be identied with the transconductance:

D G
+

iD = ID + id
+

vgs

B S

VDS = 4 V

_ +

VGS = 3 V_

600 500 iD 400 id Q

iD(vGS, VDS = 4 V)

gm = id / vgs

(A) 300 200 100 3 2 1 vGS = VGS = 3 V 6 vGS (V) 4 5 vGS = VGS + vgs

EE 105 Spring 1997 Lecture 12

Transconductance (cont.)
s

Evaluating the partial derivative: W - ( V V Tn ) ( 1 + n V DS ) g m = n C ox --- L GS

Note that the transconductance is a function of the operating point, through its dependence on VGS and VDS -- and also the dependence of the threshold voltage on the backgate bias VBS.
s

In order to nd a simple expression that highlights the dependence of gm on the DC drain current, we neglect the (usually) small error in writing:

gm =

2ID W - I D = ------------------------2 n C ox --- L V GS V Tn

For typical values (W/L) = 10, ID = 100 A, and nCox = 50 AV-2 we nd that gm = 320 AV-1 = 0.32 mS
s

How do we make a circuit which expresses id = gm vgs ? Since the current is not across the controlling voltage, we need a voltage-controlled current source:

gate + vgs _ source _ gmvgs

id
drain

EE 105 Spring 1997 Lecture 12

Output Conductance
s

We can also nd the change in drain current due to an increment in the drainsource voltage: i D 2 W ------ ( V GS V Tn ) n n I D g o = ----------- = n C ox 2 L v
DS Q

The output resistance is the inverse of the output conductance 1 1 r o = ----- = -----------go n I D

The small-signal circuit model with ro added looks like:

id = gm vgs + (1/ro)vds gate + vgs _ source gmvgs ro drain id + vds _

EE 105 Spring 1997 Lecture 12

Backgate Transconductance
s

We can nd the small-signal drain current due to a change in the backgate bias by the same technique. The chain rule comes in handy to make use of our previous result for gm: i D g mb = ----------v BS V Tn g mb = ( g m ) -----------v BS i D = -----------V Tn V Tn -----------v BS

n n gm = ( g m ) ------------------------------------ = ------------------------------------ . 2 2 p V BS 2 2 p V BS

The ratio of the front-gate transconductance gm to the backgate transconductance gmb is: 2 q s N q s N a C b(y =0) g mb 1 a - ------------------------------------ = ------------------- = ---------------- = --------------------------------------------C ox 2 ( 2 p V BS ) gm C ox 2 C ox 2 p V BS where Cb(y=0) is the depletion capacitance at the source end of the channel -gate source Cb(0) bulk depletion region channel

EE 105 Spring 1997 Lecture 12

MOSFET Capacitances in Saturation

fringe electric field lines source gate drain

n+ Csb

 

,,
qN (vGS) overlap LD overlap LD

,,, ,

In saturation, the gate-source capacitance contains two terms, one due to the channel charges dependence on vGS [(2/3)WLCox] and one due to the overlap of gate and source (WCov, where Cov is the overlap capacitance in fF per m of gate width) 2 - WLC ox + W C ov C gs = -3 In addition, there are depletion capacitances between the drain and bulk (Cdb) and between source and bulk (Csb). Finally, the extension of the gate over the eld oxide leads to a small gate-bulk capacitance Cgb.

,, ,,,

n+

Cdb

depletion region

EE 105 Spring 1997 Lecture 12

Complete Small-Signal Model

s

The capacitances are patched onto the small-signal circuit schematic containing gm, gmb, and ro

gate + vgs _ source _ vbs + bulk Cgs

Cgd

id drain

Cgb

gmvgs

gmbvbs

ro

Csb Cdb

p-channel MOSFET small-signal model the source is the highest potential and is located at the top of the schematic
source

vsg vsb _ gate

Cgs Cgd

gmvsg

gmbvsb

ro id drain

Cgb _ bulk

Csb Cdb

EE 105 Spring 1997 Lecture 12

Circuit Simulation
s

Objectives: fabricating an IC costs $1000 ... $100,000 per run ---> nice to get it right the rst time check results from hand-analysis (e.g. validity of assumptions) evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips

Simulators: SPICE: invented at UC Berkeley circa 1970-1975 commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley SPICE, but add functionality, improved user interface, ...) EE 105: student version of PSPICE on PC, limited to 10 transistors other simulators for higher speed, special needs (e.g. SPLICE, RSIM)

Limitations: simulation results provide no insight (e.g. how to increase speed of circuit) results sometimes wrong (errors in input, effect not modeled in SPICE) ===> always do hand-analysis rst and COMPARE RESULTS

EE 105 Spring 1997 Lecture 12

MOSFET Geometry in SPICE

s

Statement for MOSFET ... D,G,S,B are node numbers for drain, gate, source, and bulk terminals Mname D G S B MODname L= _ W=_ AD= _ AS=_ PD=_ PS=_

MODname species the model name for the MOSFET

NRS = N (source) PS = 2 Ldiff (source) = W

Ldiff (source)

AS = W Ldiff (source)

 ,
 ,
  ,
   
L
W

NRD = N (drain) PD = 2 Ldiff (drain) = W

Ldiff (drain)

AD = W Ldiff (drain)

EE 105 Spring 1997 Lecture 12

MOSFET Model Statement

.MODEL MODname NMOS/PMOS VTO=_ KP=_ GAMMA=_ PHI=_ LAMBDA=_ RD=_ RS=_ RSH=_ CBD=_ CBS=_CJ=_ MJ=_ CJSW=_ MJSW=_ PB=_ IS= _ CGDO=_ CGSO=_ CGBO=_ TOX=_ LD=_
Parameter name (SPICE / this text) channel length polysilicon gate length lateral diffusion/ gate-source overlap transconductance parameter threshold voltage / zero-bias threshold channel-length modulation parameter bulk threshold / backgate effect parameter surface potential / depletion drop in inversion SPICE symbol Eqs. (4.93), (4.94) Leff L LD KP VTO LAMBDA GAMMA PHI Analytical symbol Eqs. (4.59), (4.60) L Lgate LD nCox VTnO n n - p Units m m m A/V2 V V-1 V1/2 V

DC Drain Current Equations:

I DS = 0 KP - ( W L eff ) V DS [ 2 ( V GS V TH ) V DS ] ( 1 + LAMBDA V DS ) I DS = ------2

2 KP - ( W L eff ) ( V GS V TH ) ( 1 + LAMBDA V DS ) I DS = ------2

( V GS V TH ) ( 0 V DS V GS V TH )

( 0 V GS V TH V DS )

V TH = V TO + GAMMA ( 2 PHI V BS 2 PHI )

EE 105 Spring 1997 Lecture 12

Capacitances
SPICE includes the sidewall capacitance due to the perimeter of the source and drain junctions -n+ drain

(area)

(perimeter)

CJ AD CJSW PD C BD(V BD) = ------------------------------------------- + --------------------------------------------------MJ MJSW ( 1 V BD PB ) ( 1 V BD PB ) Gate-source and gate-bulk overlap capacitance are specied by CGDO and CGSO (units: F/m). Level 1 MOSFET model:
.MODEL MODN NMOS LEVEL=1 VTO=1 KP=50U LAMBDA=.033 GAMMA=.6 + PHI=0.8 TOX=1.5E-10 CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 + MJ=0.5 PB=0.95

The Level 1 model is adequate for channel lengths longer than about 1.5 m For sub-m MOSFETs, BSIM = Berkeley Short-Channel IGFET Model is the industry-standard SPICE model.

EE 105 Spring 1997 Lecture 12