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Lich On Nhan Nho Lau
Lich On Nhan Nho Lau
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TK VMS: -Tm in p logic ca ng vo, ng ra cng NOT -c tuyn V-I ca MOSFET - Cch suy ra CMOS ng t CMOS tnh
Anten: - Chng 1: Anten thng: E,H, vecto Poyting, Cng sut, in tr bc x. -Chng 2: Cng sut anten, hiu sut,E,H, Vecto mt cng sut, cng sut, Gc khi, U, nh hng D, li G - Cch xt s phn cc ca trng -Tm Gc na cng sut. -Tn gc khi ca anten
TH NGY
CH NHT 15
TH 2 16
TK VMS: -Tm in p logic ca ng vo, ng ra cng NOT -c tuyn V-I ca MOSFET - Cch suy ra CMOS ng t CMOS tnh
Anten: - Chng 1: Anten thng: E,H, vecto Poyting, Cng sut, in tr bc x. -Chng 2: Cng sut anten, hiu sut,E,H, Vecto mt cng sut, cng sut, Gc khi, U, nh hng D, li G - Cch xt s phn cc ca trng -Tm Gc na cng sut. -Tn gc khi ca anten
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 9/2013
implement perform TH 3 3 TH 4 4 TH 5 5
LT Nhn: -Cu trc Havard v Von-Newmann -3 vng nh 8051 v t kha khai bo: code data idata xdata -CTrnh tnh checksum vng nh dng con tr Th hin ti n, -Kiu lit k enum hin ti tip din, - Khai bo thanh ghi v bit: sfr ht hon thnh, v sbit ht hon thnh tip din (trong - vng nh nh a ch bit file word tm tt 12 th) 8051: bdata - Vng lp v tn while(1), u v nhc im ca n: n gin nhng tn nng lng v gy tr
HTVT: -Bi tp cng c - Cng thc suy hao trong truyn v tuyn v bi tp p dng - T hm phn b sc xut tnh kz vng v phng sai. - Tm xc sut phn b Gauss bng hm Q(k) -Nhiu nhit v 3 tch cht, mt ph cng sut ca nhiu nhit, tnh cng sut nhiu nhit
HTVT: -iu kin h thng khng mo dng -Mo tuyn tnh v khng tuyn tnh -Mo a ng - Suy Hao knh truyn v dB
X l{ nh: enhancement and restoration Min khng gian: xl{ im: m nh, ko gin tng phn, histogram; xl{ mt n: ly trung bnh nh; c th thc hin xl{ theo hm T
600 t TOIEC: Lesson 4 Anten: mt cng sut, gc khi, cng bc x, Cng sut bc x, nh hng, li anten
TH 3 10
TH 4 11
TH 5 12 HTVT: -Bi tp cng c - Cng thc suy hao trong truyn v tuyn v bi tp p dng - T hm phn b sc xut tnh kz vng v phng sai. - Tm xc sut phn b Gauss bng hm Q(k) -Nhiu nhit v 3 tch cht, mt ph cng sut ca nhiu nhit, tnh cng sut nhiu nhit
LT Nhn: -Cu trc Havard v Von-Newmann -3 vng nh 8051 v t kha khai bo: code data idata xdata -CTrnh tnh checksum vng Th hin ti n, nh dng con tr hin ti tip din, -Kiu lit k enum ht hon thnh, - Khai bo thanh ghi v bit: sfr ht hon thnh tip din (trong v sbit file word tm tt 12 th) - vng nh nh a ch bit 8051: bdata - Vng lp v tn while(1), u v nhc im ca n: n gin nhng tn nng lng v gy tr
HTVT: -iu kin h thng khng mo dng -Mo tuyn tnh v khng tuyn tnh -Mo a ng - Suy Hao knh truyn v dB
X l{ nh: enhancement and restoration Min khng gian: xl{ im: m HTVT: nh, ko gin tng phn, - Bi tp ci thin khi chim histogram; xl{ mt n: ly vo b khuch i. trung bnh nh; c th thc hin xl{ theo hm T
X l{ nh: -Median v b lc Median loi nhiu mui tiu. -Lm sc nt nh bng Laplacian: mt n, mt n cng dn. Tng mc sai bit bin. - Tch bin bin bng mt n Gradian -Phng php ci thin nh bng kt hp cc b lc. -Min tn s: Lm sc nt+ lm mn nh,
Anten: Bi tp v phn cc trong slide TTT2: Cch xc nh 1 khi chc nng trn mch HTVT: -Cch tm cng sut ca u ra 1 h thng. T tm cs nhiu nhit -Cng sut pht, SNR u vo my thu v SNR u ra my thu. -Bi tp V d. -Cu hi v ct ghp ng cp
TH 3 17
TH 4 18
TH 5 19
X l{ nh: -Median v b lc Median loi nhiu mui tiu. -Lm sc nt nh bng Laplacian: mt n, mt n cng HTVT: dn. Tng mc sai bit bin. - Bi tp ci thin khi chim - Tch bin bin bng mt n vo b khuch i. Gradian -Phng php ci thin nh bng kt hp cc b lc. -Min tn s: Lm sc nt+ lm mn nh,
HTVT: -Cch tm cng sut ca u ra 1 h thng. T tm cs nhiu nhit -Cng sut pht, SNR u vo my thu v SNR u ra my thu. -Bi tp V d. -Cu hi v ct ghp ng cp
Lp trnh nhng: Cc vit file h v c lnh tin x l{ #ifndefine TTT2: Cch xc nh 1 khi Cu trc Delay: Vng lp, timer chc a tc v: nng trn mch v o p vo -superloop vi delay tng khi, trn linh kin t v - Sandwich delay in tr. -Foreground/ Background schedling -Round-Robin sheduler dng ngt
HTVT: -Ti sao phi iu ch? - iu kin chun ha cho tn hiu kho st. X l{ nh: Khi phc nh -Ph tn ca bng di xung - Ph PDF ca 6 loi nhiu. quanh Fc -5 b lc nh. -Hs phm cht ca b lc -Cch xc nh loi nhiu trong cng hng. thc t bng vng trn. - iu ch AM v v d: + cng thc. + Cc v dng sng nhn vs Cos
TH 3 24
TH 4 25
TH 5 26
Lp trnh nhng: Cc vit file h v c lnh tin x l{ #ifndefine TTT2: Cch xc nh 1 khi Cu trc Delay: Vng lp, timer chc a tc v: nng trn mch v o p vo -superloop vi delay tng khi, trn linh kin t v - Sandwich delay in tr. -Foreground/ Background schedling -Round-Robin sheduler dng ngt HTVT: -Ti sao phi iu ch? - iu kin chun ha cho tn hiu kho st. X l{ nh: Khi phc nh -Ph tn ca bng di xung - Ph PDF ca 6 loi nhiu. quanh Fc -5 b lc nh. -Hs phm cht ca b lc -Cch xc nh loi nhiu trong cng hng. thc t bng vng trn. - iu ch AM v v d: + cng thc. + Cc v dng sng nhn vs Cos
TH 3 1
TH 4 2
TH 5 3
verification TH 6 6 TH 7 7
TK HTN: - Mt s a im mua linh kin v t mch -PIC16F84A: +3 cch cp clock. +B nh: Ch { EEPROM + cc thng s chnh cn bit ca 1 con VK: s lnh, tc x l{, b nh program, RAM, EEPROM, +Architecture ca 16F84 +B cu hi tm hiu kh nng 1 con VK +Bi tp nt nhn v led
K{ thut Xung: -Thng thng, ng vo hm m -Mch b chnh v iu kin b chnh - Mch giao hon RL: Ch { dng s kin ko chy qua L -Mch giao hon RLC: Vo/V trong 3 trng hp -bi tp 1.4 v 1.6 trong BT chng I Anh vn: lesson 2
TH 6 13 TK HTN: - Mt s a im mua linh kin v t mch -PIC16F84A: +3 cch cp clock. +B nh: Ch { EEPROM + cc thng s chnh cn bit ca 1 con VK: s lnh, tc x l{, b nh program, RAM, EEPROM, +Architecture ca 16F84 +B cu hi tm hiu kh nng 1 con VK +Bi tp nt nhn v led
TH 7 14
K{ thut Xung: -Thng thng, ng vo hm m -Mch b chnh v iu kin b chnh - Mch giao hon RL: Ch { dng s kin ko chy qua L -Mch giao hon RLC: Vo/V trong 3 trng hp -bi tp 1.4 v 1.6 trong BT chng I
600 t Lesson 5,6 TKHTN: -Lm bi tp Led7 on - Cc bc c data sheep KTX: -BT Chng 1. - Dng Thevenin lm ton - p ng Vo ca RC vs cc dng tn hiu - Cch suy ra t Mch thng thng RC-> h thng RC v thng h thng RL
TH 6 20
TH 7 21
KTX: -BT Chng 1. - Dng Thevenin lm ton - p ng Vo ca RC vs cc dng tn hiu - Cch suy ra t Mch thng thng RC-> h thng RC v thng h thng RL
TH 6 27
TH 7 28
TH 6 4
TH 7 5
N NHN NH LU THNG
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TK VMS: -Tm in p logic ca ng vo, ng ra cng NOT -c tuyn V-I ca MOSFET - Cch suy ra CMOS ng t CMOS tnh
Anten: - Chng 1: Anten thng: E,H, vecto Poyting, Cng sut, in tr bc x. -Chng 2: Cng sut anten, hiu sut,E,H, Vecto mt cng sut, cng sut, Gc khi, U, nh hng D, li G - Cch xt s phn cc ca trng -Tm Gc na cng sut. -Tn gc khi ca anten
TH
CH NHT
TH 2
NGY
15
16
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 10/2013
TH 3 3 TH 4 4 TH 5 5
LT Nhn: -Cu trc Havard v Von-Newmann -3 vng nh 8051 v t kha khai bo: code data idata xdata Th hin ti n, -CTrnh tnh checksum vng hin ti tip din, nh dng con tr ht hon thnh, -Kiu lit k enum ht hon thnh tip din - Khai bo thanh ghi v bit: (trong file word tm tt 12 sfr v sbit th) - vng nh nh a ch bit 8051: bdata - Vng lp v tn while(1), u v nhc im ca n: n gin nhng tn nng lng v gy tr
HTVT: -Bi tp cng c - Cng thc suy hao trong truyn v tuyn v bi tp p dng - T hm phn b sc xut tnh kz vng v phng sai. - Tm xc sut phn b Gauss bng hm Q(k) -Nhiu nhit v 3 tch cht, mt ph cng sut ca nhiu nhit, tnh cng sut nhiu nhit
X l{ nh: HTVT: enhancement and -iu kin h thng restoration khng mo dng Min khng gian: xl{ im: -Mo tuyn tnh v khng m nh, ko gin tng tuyn tnh phn, histogram; xl{ mt -Mo a ng n: ly trung bnh nh; c - Suy Hao knh truyn v th thc hin xl{ theo hm dB T
TH 3 10
TH 4 11
TH 5 12
X l{ nh: -Median v b lc Median loi nhiu mui tiu. -Lm sc nt nh bng Laplacian: mt n, mt n cng dn. Tng mc sai HTVT: bit bin. - Bi tp ci thin khi - Tch bin bin bng mt chim vo b khuch i. n Gradian -Phng php ci thin nh bng kt hp cc b lc. -Min tn s: Lm sc nt+ lm mn nh,
HTVT: -Cch tm cng sut ca u ra 1 h thng. T tm cs nhiu nhit -Cng sut pht, SNR u Anten: Bi tp v phn cc trong slide 600 t Lesson 5,6 vo my thu v SNR u ra my thu. -Bi tp V d. -Cu hi v ct ghp ng cp
TH 3
TH 4
TH 5
17
18
19
TTT2: Cch xc nh 1 khi chc nng trn mch v o p vo tng khi, trn linh kin t v in tr.
Lp trnh nhng: Cc vit file h v c lnh tin x l{ #ifndefine Cu trc Delay: Vng lp, timer Anten: a tc v: -Bi tp v d 6.10: Tm Pc. -superloop vi delay -Tuyn Anten: BT v d 6.11 - Sandwich delay -Foreground/ Background schedling -Round-Robin sheduler dng ngt
HTVT: -Ti sao phi iu ch? - iu kin chun ha cho tn hiu kho st. X l{ nh: Khi phc nh -Ph tn ca bng di xung - Ph PDF ca 6 loi nhiu. quanh Fc -5 b lc nh. -Hs phm cht ca b lc -Cch xc nh loi nhiu cng hng. trong thc t bng vng - iu ch AM v v d: trn. + cng thc. + Cc v dng sng nhn vs Cos
TH 3 24
TH 4 25
TH 5 26
TH 3 1
TH 4 2
TH 5 3
TH 6 6
TH 7 7
TK HTN: - Mt s a im mua linh kin v t mch -PIC16F84A: +3 cch cp clock. +B nh: Ch { EEPROM + cc thng s chnh cn bit ca 1 con VK: s lnh, tc x l{, b nh program, RAM, EEPROM, +Architecture ca 16F84 +B cu hi tm hiu kh nng 1 con VK +Bi tp nt nhn v led
K{ thut Xung: -Thng thng, ng vo hm m -Mch b chnh v iu kin b chnh - Mch giao hon RL: Ch { dng s kin ko chy qua L -Mch giao hon RLC: Vo/V trong 3 trng hp -bi tp 1.4 v 1.6 trong BT chng I Anh vn: lesson 2
TH 6 13
TH 7 14
KTX: -BT Chng 1. - Dng Thevenin lm ton - p ng Vo ca RC vs cc dng tn hiu - Cch suy ra t Mch thng thng RC-> h thng RC v thng h thng RL
TH 6
TH 7
20
21
TH 6 27
TH 7 28
TH 6 4
TH 7 5
N NHN NH LU THNG 1
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TH NGY
CH NHT 15
TH 2 16
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 11/2013
TH 3 3 TH 4 4 TH 5 5 TH 6 6
TH 3 10
TH 4 11
TH 5 12
TH 6 13
TH 3 17
TH 4 18
TH 5 19
TH 6 20
TH 3 24
TH 4 25
TH 5 26
TH 6 27
TH 3 1
TH 4 2
TH 5 3
TH 6 4
TH 7 7
TH 7 14
TH 7 21
TH 7 28
TH 7 5
N NHN NH LU THNG 1
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TK VMS: -Tm in p logic ca ng vo, ng ra cng NOT -c tuyn V-I ca MOSFET - Cch suy ra CMOS ng t CMOS tnh
Anten: - Chng 1: Anten thng: E,H, vecto Poyting, Cng sut, in tr bc x. -Chng 2: Cng sut anten, hiu sut,E,H, Vecto mt cng sut, cng sut, Gc khi, U, nh hng D, li G - Cch xt s phn cc ca trng -Tm Gc na cng sut. -Tn gc khi ca anten
TH
CH NHT
TH 2
NGY
15
16
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 12/2013
TH 3 3 TH 4 4 TH 5 5 TH 6 6
LT Nhn: -Cu trc Havard v Von-Newmann -3 vng nh 8051 v t kha khai bo: code data idata xdata Th hin ti n, -CTrnh tnh checksum hin ti tip din, vng nh dng con tr ht hon thnh, -Kiu lit k enum ht hon thnh tip din - Khai bo thanh ghi v bit: (trong file word tm tt 12 sfr v sbit th) - vng nh nh a ch bit 8051: bdata - Vng lp v tn while(1), u v nhc im ca n: n gin nhng tn nng lng v gy tr
HTVT: -Bi tp cng c - Cng thc suy hao trong truyn v tuyn v bi tp p dng - T hm phn b sc xut tnh kz vng v phng sai. - Tm xc sut phn b Gauss bng hm Q(k) -Nhiu nhit v 3 tch cht, mt ph cng sut ca nhiu nhit, tnh cng sut nhiu nhit
TK HTN: - Mt s a im mua linh kin v t mch -PIC16F84A: +3 cch cp clock. +B nh: Ch { EEPROM + cc thng s chnh cn bit ca 1 con VK: s lnh, tc x l{, b nh program, RAM, EEPROM, +Architecture ca 16F84 +B cu hi tm hiu kh nng 1 con VK +Bi tp nt nhn v led
X l{ nh: HTVT: enhancement and -iu kin h thng restoration khng mo dng Min khng gian: xl{ im: -Mo tuyn tnh v khng m nh, ko gin tng tuyn tnh phn, histogram; xl{ mt -Mo a ng n: ly trung bnh nh; c - Suy Hao knh truyn v th thc hin xl{ theo hm dB T
K{ thut Xung: -Thng thng, ng vo hm m -Mch b chnh v iu kin b chnh - Mch giao hon RL: Ch { dng s kin ko chy qua L -Mch giao hon RLC: Vo/V trong 3 trng hp -bi tp 1.4 v 1.6 trong BT chng I Anh vn: lesson 2
TH 3 10
TH 4 11
TH 5 12
TH 6 13
X l{ nh: -Median v b lc Median loi nhiu mui tiu. -Lm sc nt nh bng Laplacian: mt n, mt n cng dn. Tng mc sai HTVT: TKHTN: bit bin. - Bi tp ci thin khi -Lm bi tp Led7 on - Tch bin bin bng mt chim vo b khuch i. - Cc bc c data sheep n Gradian -Phng php ci thin nh bng kt hp cc b lc. -Min tn s: Lm sc nt+ lm mn nh,
HTVT: -Cch tm cng sut ca u ra 1 h thng. T tm cs nhiu nhit -Cng sut pht, SNR u Anten: Bi tp v phn cc trong slide600 t Lesson 5,6 vo my thu v SNR u ra my thu. -Bi tp V d. -Cu hi v ct ghp ng cp
KTX: -BT Chng 1. - Dng Thevenin lm ton - p ng Vo ca RC vs cc dng tn hiu - Cch suy ra t Mch thng thng RC-> h thng RC v thng h thng RL
TH 3
TH 4
TH 5
TH 6
17
18
19
20
Lp trnh nhng: Cc vit file h v c lnh tin x l{ #ifndefine Cu trc Delay: Vng lp, TTT2: Cch xc nh 1 timer Anten: khi chc a tc v: -Bi tp v d 6.10: Tm Pc. nng trn mch v o p -superloop vi delay -Tuyn Anten: BT v d vo tng khi, trn linh - Sandwich delay 6.11 kin t v in tr. -Foreground/ Background schedling -Round-Robin sheduler dng ngt HTVT: -Ti sao phi iu ch? - iu kin chun ha cho tn hiu kho st. -Ph tn ca bng di xung quanh Fc -Hs phm cht ca b lc cng hng. - iu ch AM v v d: + cng thc. + Cc v dng sng nhn vs Cos
X l{ nh: Khi phc nh - Ph PDF ca 6 loi nhiu. -5 b lc nh. -Cch xc nh loi nhiu trong thc t bng vng trn.
TH 3 24
TH 4 25
TH 5 26
TH 6 27
TH 3 1
TH 4 2
TH 5 3
TH 6 4
TH 7 7
TH 7 14
TH 7
21
TH 7 28
TH 7 5
N NHN NH LU THNG
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TH NGY
CH NHT 15
TH 2 16
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 1/2014
TH 3 3 TH 4 4 TH 5 5 TH 6 6
TH 3 10
TH 4 11
TH 5 12
TH 6 13
TH 3 17
TH 4 18
TH 5 19
TH 6 20
TH 3 24
TH 4 25
TH 5 26
TH 6 27
TH 3 1
TH 4 2
TH 5 3
TH 6 4
TH 7 7
TH 7 14
TH 7 21
TH 7 28
TH 7 5
N NHN NH LU THNG
TH NGY CH NHT 1 TH 2 2
TH NGY
CH NHT 8
TH 2 9
TK VMS: -Tm in p logic ca ng vo, ng ra cng NOT -c tuyn V-I ca MOSFET - Cch suy ra CMOS ng t CMOS tnh
Anten: - Chng 1: Anten thng: E,H, vecto Poyting, Cng sut, in tr bc x. -Chng 2: Cng sut anten, hiu sut,E,H, Vecto mt cng sut, cng sut, Gc khi, U, nh hng D, li G - Cch xt s phn cc ca trng -Tm Gc na cng sut. -Tn gc khi ca anten
TH
CH NHT
TH 2
NGY
15
16
TH NGY
CH NHT 22
TH 2 23
TH NGY
CH NHT 29
TH 2 30
N NH LU THNG 2/2014
TH 3 3 TH 4 4 TH 5 5 TH 6 6
LT Nhn: -Cu trc Havard v Von-Newmann -3 vng nh 8051 v t kha khai bo: code data idata xdata Th hin ti n, -CTrnh tnh checksum hin ti tip din, vng nh dng con tr ht hon thnh, -Kiu lit k enum ht hon thnh tip din - Khai bo thanh ghi v bit: (trong file word tm tt 12 sfr v sbit th) - vng nh nh a ch bit 8051: bdata - Vng lp v tn while(1), u v nhc im ca n: n gin nhng tn nng lng v gy tr
HTVT: -Bi tp cng c - Cng thc suy hao trong truyn v tuyn v bi tp p dng - T hm phn b sc xut tnh kz vng v phng sai. - Tm xc sut phn b Gauss bng hm Q(k) -Nhiu nhit v 3 tch cht, mt ph cng sut ca nhiu nhit, tnh cng sut nhiu nhit
TK HTN: - Mt s a im mua linh kin v t mch -PIC16F84A: +3 cch cp clock. +B nh: Ch { EEPROM + cc thng s chnh cn bit ca 1 con VK: s lnh, tc x l{, b nh program, RAM, EEPROM, +Architecture ca 16F84 +B cu hi tm hiu kh nng 1 con VK +Bi tp nt nhn v led
X l{ nh: HTVT: enhancement and -iu kin h thng restoration khng mo dng Min khng gian: xl{ im: -Mo tuyn tnh v khng m nh, ko gin tng tuyn tnh phn, histogram; xl{ mt -Mo a ng n: ly trung bnh nh; c - Suy Hao knh truyn v th thc hin xl{ theo hm dB T
K{ thut Xung: -Thng thng, ng vo hm m -Mch b chnh v iu kin b chnh - Mch giao hon RL: Ch { dng s kin ko chy qua L -Mch giao hon RLC: Vo/V trong 3 trng hp -bi tp 1.4 v 1.6 trong BT chng I Anh vn: lesson 2
TH 3 10
TH 4 11
TH 5 12
TH 6 13
X l{ nh: -Median v b lc Median loi nhiu mui tiu. -Lm sc nt nh bng Laplacian: mt n, mt n cng dn. Tng mc sai HTVT: TKHTN: bit bin. - Bi tp ci thin khi -Lm bi tp Led7 on - Tch bin bin bng mt chim vo b khuch i. - Cc bc c data sheep n Gradian -Phng php ci thin nh bng kt hp cc b lc. -Min tn s: Lm sc nt+ lm mn nh,
HTVT: -Cch tm cng sut ca u ra 1 h thng. T tm cs nhiu nhit -Cng sut pht, SNR u Anten: Bi tp v phn cc trong slide600 t Lesson 5,6 vo my thu v SNR u ra my thu. -Bi tp V d. -Cu hi v ct ghp ng cp
KTX: -BT Chng 1. - Dng Thevenin lm ton - p ng Vo ca RC vs cc dng tn hiu - Cch suy ra t Mch thng thng RC-> h thng RC v thng h thng RL
TH 3
TH 4
TH 5
TH 6
17
18
19
20
Lp trnh nhng: Cc vit file h v c lnh tin x l{ #ifndefine Cu trc Delay: Vng lp, TTT2: Cch xc nh 1 timer Anten: khi chc a tc v: -Bi tp v d 6.10: Tm Pc. nng trn mch v o p -superloop vi delay -Tuyn Anten: BT v d vo tng khi, trn linh - Sandwich delay 6.11 kin t v in tr. -Foreground/ Background schedling -Round-Robin sheduler dng ngt HTVT: -Ti sao phi iu ch? - iu kin chun ha cho tn hiu kho st. -Ph tn ca bng di xung quanh Fc -Hs phm cht ca b lc cng hng. - iu ch AM v v d: + cng thc. + Cc v dng sng nhn vs Cos
X l{ nh: Khi phc nh - Ph PDF ca 6 loi nhiu. -5 b lc nh. -Cch xc nh loi nhiu trong thc t bng vng trn.
TH 3 24
TH 4 25
TH 5 26
TH 6 27
TH 3 1
TH 4 2
TH 5 3
TH 6 4
TH 7 7
TH 7 14
TH 7
21
TH 7 28
TH 7 5