EL5067 Sistem VLSI Untuk Komunikasi Digital

Lecture 03 FSM and HLSM in VHDL

Finite-State Machine (FSM)

Finite-State Machine (FSM)

Inputs: b; Outputs: x x=0 Off b x=1 On1
FSM inputs

x=1 x=1 On3

FSM outputs

On2

b Combinational logic
Currstate

clk

State register
Nextstate

Finite-State Machine (FSM)

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE Beh OF LaserTimer IS TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); SIGNAL Currstate, Nextstate: Statetype; BEGIN StateReg: PROCESS (Clk) BEGIN IF (Clk = '1' AND Clk'EVENT) THEN IF (Rst = '1') THEN Currstate <= S_Off; ELSE Currstate <= Nextstate; END IF; END IF; END PROCESS; CombLogic: PROCESS (Currstate, b) BEGIN CASE Currstate IS WHEN S_Off => x <= '0'; IF (b = '0') THEN Nextstate <= S_Off; ELSE Nextstate <= S_On1; END IF; WHEN S_On1 => x <= '1'; Nextstate <= S_On2; WHEN S_On2 => x <= '1'; Nextstate <= S_On3; WHEN S_On3 => x <= '1'; Nextstate <= S_Off; END CASE; END PROCESS; END Beh;

Finite-State Machine (FSM)

Architecture defines two processes
One process for combinational logic One process for state register
FSM outputs FSM inputs
ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE Beh OF LaserTimer IS TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) BEGIN ... END PROCESS CombLogic; StateReg: PROCESS (Clk) BEGIN ... END PROCESS StateReg; END Beh;

Combinational logic
Currstate

clk

State register
Nextstate

Finite-State Machine (FSM)

Inputs: b; Outputs: x x=0 Off b x=1 x=1 x=1

On3

ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE Beh OF LaserTimer IS TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) BEGIN ... END PROCESS CombLogic;

On1

On2

TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); Note: Enumeration lists all possible values for type

StateReg: PROCESS (Clk) BEGIN ... END PROCESS StateReg; END Beh;

Possible values for defined type Name of new type Type declaration

Finite-State Machine (FSM)

Architecture defines two Statetype signals
Currstate, Nextstate
ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE Beh OF LaserTimer IS TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) BEGIN ...
FSM outputs FSM inputs b Combinational logic Currstate clk State register Nextstate x

CombLogic Process
Sensitive to Currstate and input b

StateReg Process
Sensitive to Clk input

END PROCESS CombLogic; StateReg: PROCESS (Clk) BEGIN ... END PROCESS StateReg; END Beh;

Finite-State Machine (FSM)

Process may use CASE statement
x=0
Off b
... SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) BEGIN CASE Currstate IS WHEN S_Off => x <= '0'; IF (b = '0') THEN Nextstate <= S_Off; ELSE Nextstate <= S_On1; END IF; WHEN S_On1 => x <= '1'; Nextstate <= S_On2; WHEN S_On2 => x <= '1'; Nextstate <= S_On3; WHEN S_On3 => x <= '1'; Nextstate <= S_Off; END CASE; END PROCESS CombLogic; ...

x=1 x=1 On3

b
x=1 On1 On2

b Combinational logic
Currstate

clk

State register
Nextstate

FSM outputs

FSM inputs

Finite-State Machine (FSM)

FSMs CombLogic process
Case statement describes states CASE Currstate IS
... SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) Executes corresponding statements BEGIN based on current state Suppose Currstate CASE Currstate IS A state's statements consist of WHEN S_Off => is S_On1 Actions of the state x <= '0'; IF (b = '0') THEN Setting of next state (transitions) Nextstate <= S_Off; Currstate is S_On1 ELSE Nextstate <= S_On1; Executes statements for state On1, END IF; jumps to END CASE WHEN S_On1 => x <= '1'; Inputs: x; Outputs: b Nextstate <= S_On2; WHEN S_On2 => x=0 x <= '1'; Nextstate <= S_On3; Off b WHEN S_On3 => x <= '1'; b Nextstate <= S_Off; x=1 x=1 x=1 END CASE; END PROCESS CombLogic; On1 On2 On3 ...

Ex:

Finite-State Machine (FSM)

FSM StateReg Process
Similar to 4-bit register Register for Currstate signal of type Statetype Note: Registers size is implicitly defined by Statetype Process has synchronous reset Resets Currstate to FSMs initial state, S_Off
FSM inputs b Combinational logic
Currstate
... StateReg: PROCESS (Clk) BEGIN IF (Clk = '1' AND Clk'EVENT) THEN IF (Rst = '1') THEN Currstate <= S_Off; ELSE Currstate <= Nextstate; END IF; END IF; END PROCESS StateReg; ...

clk

State register
Nextstate

FSM outputs

High-Level State Machine

High-Level State Machine

Register-transfer level (RTL) design captures desired system behavior using high-level state machine
Earlier example 3 cycles high, used FSM What if 512 cycles high? 512-state FSM? Better solution High-level state machine that uses counter to count cycles
Declare explicit counter cnt Initialize cnt to 2 (2, 1, 0 3 counts) "On" state Sets x=1 Configures cnt for decrement on next cycle Transitions to Off when cnt is 0 Note that transition conditions use current value of cnt, not next (decremented) value For 512 cycles high, just initialize cnt to 511
Inputs: b; Outputs: x x=0 Off b x=1 On1 x=1 On2 3 cycles with x=1 x=1 On3 b

Inputs: b; Outputs: x; Register: cnt(2)

x=0 cnt=2

Off
b

cnt=0

x=1 cnt=cnt-1 On (cnt=0)'

3 cycles with x=1

High-Level State Machine

Entity declaration same as FSM Same two-process approach as FSM
One process for combinational logic, one for registers Registers now include explicit registers (Cnt)
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE HLSM OF LaserTimer IS TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); BEGIN CombLogic: PROCESS (Currstate, Cnt, b) BEGIN ... END PROCESS CombLogic; Regs: PROCESS (Clk) BEGIN ... END PROCESS Regs; END HLSM;

FSM outputs

HLSM FSM inputs inputs

b Combinational logic Currstate clk State register

Cnt Cnt register CntNext

Nextstate Nextstate

13

HLSM outputs

High-Level State Machine

CombLogic process
Describes actions and transitions Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2 Off b
... ARCHITECTURE HLSM OF LaserTimer IS TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); BEGIN CombLogic: PROCESS (Currstate, Cnt, b) BEGIN CASE Currstate IS WHEN S_Off => x <= '0'; CntNext <= "10"; IF (b = '0') THEN Nextstate <= S_Off; ELSE Nextstate <= S_On; END IF; WHEN S_On => x <= '1'; CntNext <= Cnt - "01"; IF (Cnt = "00") THEN Nextstate <= S_Off; ELSE Nextstate <= S_On; END IF; END CASE; END PROCESS CombLogic; ...

cnt=0

x=1 cnt=cnt-1 On (cnt=0)'

x HLSM outputs

HLSM inputs

b
Combinational logic Currstate Cnt

clk

State register Nextstate

Cnt register
CntNext

High-Level State Machine

Regs process
Updates registers on rising clock
... ARCHITECTURE HLSM OF LaserTimer IS TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); BEGIN CombLogic: PROCESS (Currstate, Cnt, b) ... END PROCESS CombLogic; Regs: PROCESS (Clk) BEGIN IF (Clk = '1' AND Clk'EVENT) THEN IF (Rst = '1') THEN Currstate <= S_Off; Cnt <= "00"; ELSE Currstate <= Nextstate; Cnt <= CntNext; END IF; END IF; END PROCESS Regs; END HLSM;

Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2

Off b b cnt=0

x=1 cnt=cnt-1
On (cnt=0)'
x HLSM outputs

HLSM inputs

b Combinational logic Currstate clk State register Nextstate Cnt Cnt register CntNext

Top-Down Design: HLSM to Controller and Datapath

Top-Down Design
Top-down design
Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first.
Capture behavior
k_s p_s s_s w_s k_s p_s s_s w_s

Simulate

Capture structure

Should be the same

Simulate

Top-Down Design
Top-down design
Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first.
Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2 Off b

b
cnt=0

x=1 cnt=cnt-1 On (cnt=0)'

At RTL level
Capture behavior HLSM Capture structure: Controller and datapath
Controller

Datapath

HLSM to Controller and Datapath

Deriving a datapath from the HLSM
Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2

Off
b

b cnt=0
Cnt_s Cnt_eq0

Datapath "10" ="00"

s 1 2x1 0

x=1 cnt=cnt-1 On (cnt=0)'

-1

Cnt_ld Clk

ld

Cnt

HLSM to Controller and Datapath

Deriving a controller
Replace HLSM by FSM that uses the datapath
Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2 Off b

b
cnt=0

x=1 cnt=cnt-1

On

(cnt=0)' Datapath
"10"
Cnt_s

Inputs: b, Cnt_eq0; Outputs: x, Cnt_s, Cnt_ld; x=0 Cnt_s=1, Cnt_ld=1

Off b

b
Cnt_eq0

Cnt_eq0

="00"

s 1 2x1 0

-1

x=1 Cnt_s=0, Cnt_ld=1

Cnt_ld Clk

ld

Cnt

On

(Cnt_eq0)'

Controller

HLSM to Controller and Datapath

Describe controller and datapath in VHDL
One option: structural datapath, behavioral (FSM) controller Let's instead describe both behaviorally

Inputs: b, Cnt_eq0; Outputs: x, Cnt_s, Cnt_ld; x=0 Cnt_s=1, Cnt_ld=1

Datapath
"10"

Cnt_s

Off b

b
Cnt_eq0

Cnt_eq0

="00"

s 1 2x1 0

-1

x=1 Cnt_s=0, Cnt_ld=1

Cnt_ld Clk

ld

Cnt

On

(Cnt_eq0)'

Controller

Describing a Datapath Behaviorally

ARCHITECTURE CtrlDpBeh OF LaserTimer IS -- Shared signals SIGNAL Cnt_eq0, Cnt_s, Cnt_ld: std_logic; -- Datapath signals Combinational part and SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); register part BEGIN ------ Datapath processes ----- Current and next signals DPCombLogic: PROCESS (Cnt_s, Cnt) shared between the two parts BEGIN IF (Cnt_s = '1') THEN Just like for FSM behavior CntNext <= "10"; ELSE CntNext <= Cnt - "01"; END IF; IF (Cnt = "00") THEN Datapath Cnt_eq0 <= '1'; ELSE DpCombLogic Cnt_eq0 <= '0'; "10" Cnt_s END IF; END PROCESS DPCombLogic; s 1 2x1 0 ="00" -1 Cnt_eq0 DpRegs: PROCESS (Clk) BEGIN CntNext Cnt IF (Clk = '1' AND Clk'EVENT) THEN Cnt_ld IF (Rst = '1') THEN ld Cnt Cnt <= "00"; Clk ELSIF (Cnt_ld = '1') THEN DpRegs Cnt <= CntNext; END IF; END IF; END PROCESS DpRegs;

Two processes

Describing the Controller Behaviorally

ARCHITECTURE CtrlDpBeh OF LaserTimer IS ... -- Controller state signals TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; BEGIN ... ------ Controller processes -----CtrlCombLogic: PROCESS (Currstate, Cnt_eq0, b) BEGIN CASE Currstate IS WHEN S_Off => x <= '0'; Cnt_s <= '1'; Cnt_ld <= '1'; IF (b = '0') THEN Nextstate <= S_Off; ELSE Nextstate <= S_On; END IF; WHEN S_On => x <= '1'; Cnt_s <= '0'; Cnt_ld <= '1'; IF (Cnt_eq0 = '1') THEN Nextstate <= S_Off; ELSE Nextstate <= S_On; END IF; END CASE; END PROCESS CtrlCombLogic; CtrlRegs: PROCESS (Clk) BEGIN IF (Clk = '1' AND Clk'EVENT) THEN IF (Rst = '1') THEN Currstate <= S_Off; ELSE Currstate <= Nextstate; END IF; END IF; END PROCESS CtrlRegs;

Inputs: b, Cnt_eq0; Outputs: x, Cnt_s, Cnt_ld; x=0 Cnt_s=1, Cnt_ld=1

Off
b

Cnt_eq0
x=1 Cnt_s=0, Cnt_ld=1

On

(Cnt_eq0)'

Controller

Standard approach for describing FSM - Two processes

Controller and Datapath Behavior

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer;
Datapat Inputs: b; Outputs: x; Register: cnt(2) Inputs: b, Cnt_eq0; Outputs: x, Cnt_s, Cnt_ld; h x=0 x=0 cnt=2
Cnt_s=1, Cnt_ld=1 Cnt_s

ARCHITECTURE CtrlDpBeh OF LaserTimer IS -- Shared signals SIGNAL Cnt_eq0, Cnt_s, Cnt_ld: std_logic; -- Datapath signals SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); -- Controller state signals TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; BEGIN ------ Datapath processes -----DPCombLogic: PROCESS (Cnt_s, Cnt) ... END PROCESS DPCombLogic; DpRegs: PROCESS (Clk) ... END PROCESS DpRegs; ------ Controller processes -----CtrlCombLogic: PROCESS (Currstate, Cnt_eq0, b) ... END PROCESS CtrlCombLogic; CtrlRegs: PROCESS (Clk) ... END PROCESS CtrlRegs; END CtrlDpBeh;

"10"
="00"
s12x1 0

Off Off
b b

x=1 x=1 cnt=cnt-1 On On

cnt=0 Cnt_eq0

Cnt_eq0

-1

Cnt_s=0, Cnt_ld=1

Cnt_ld
ld

Cnt

Clk (cnt=0)' (Cnt_eq0)' Controller

Result is one architecture with four processes

Top-Down Design : Converting Algorithmic-Level Behavior to RTL

Algorithmic-Level Behavior for SAD

A

SAD

256-byte array integer

B sad_out

256-byte array
go

Wait until go equals '1' Sum := 0; FOR I IN 0 TO 255 LOOP Sum := Sum + |A(I) - B(I)|; END LOOP; SAD_out <= Sum;

Note: Above algorithm written in pseudo-code, and not in a particular language

Convert Algorithm to HLSM

Local registers: sum, sad_reg (32 bits); i (9 bits)

S0 go
S1
(i<256)

!go sum = 0 i=0

S2 i<256 sum=sum+abs(A[i]-B[i]) S3 i=i+1 S4 sad_reg = sum

Describe HLSM in VHDL

... TYPE Statetype IS (S0,S1,S2,S3,S4); SIGNAL State_reg: Statetype; SIGNAL Sum_reg, SAD_reg: integer; SIGNAL I_reg: integer; BEGIN ... PROCESS(Clk) WHEN S2 => BEGIN IF (NOT(I_reg = 255)) THEN IF (Clk='1' AND Clk'EVENT) THEN State_reg <= S3; IF (Rst='1') THEN ELSE State_reg <= S0; State_reg <= S4; Sum_reg <= 0; END IF; SAD_reg <= 0; WHEN S3 => I_reg <= 0; Sum_reg <= Sum_reg + ELSE Conv_Integer(ABS(A(I_reg)-B(I_reg))); CASE (State_reg) IS I_reg <= I_reg + 1; WHEN S0 => State_reg <= S2; IF (Go='1') THEN WHEN S4 => State_reg <= S1; SAD_reg <= Sum_reg; ELSE State_reg <= S0; State_reg <= S0; WHEN OTHERS => END IF; State_reg <= S0; WHEN S1 => END CASE; Sum_reg <= 0; END IF; I_reg <= 0; END IF; State_reg <= S2; END PROCESS; ... SAD_out <= SAD_reg; ...