Cpe358/Cs381 Switching Theory and Logical Design Class 5

CpE358/CS381 Switching Theory and Logical Design Class 5
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
Copyright 2004 Stevens Institute of Technology All rights reserved
1-152
Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Hazards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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1-153
Standard Combinational Circuits in TTL

All part number prefixed by 74, 74S, 74LS, etc.
00, 01, 03, 10, 12, 13, 18, 20, 22, 26, 30, 37, 38, 39, 40 02, 23, 24, 25, 27, 28, 33 04, 05, 06, 14, 16 07, 17 08, 09, 11, 15, 21 32 41, 42, 43, 44 45 46, 47, 48, 49 35, 50, 51, 53, 54, 55, 56 52 60, 61 62 NAND 70-79 80, 82, 83, NOR NOT Buffer AND OR 4-line to 10-line decoder BCD-to-decimal BCD-to-7-segment AND-OR-Invert AND-OR AND expander AND-OR expander 81, 84, 89 85 86 87 88 90-116 160-179, 190-199 138, 139, 148-159, 251-258, 348-359 Flip-Flops Adders RAM Magnitude comparator XOR True/complement ROM Counters, S/R, Latches
Decoder, MUX, Encoders, Selectors, DeMUX
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Generalized Combinational Circuits

In general, F( ) will represent some high-level function needed for a system
I
n inputs
Combinational Circuit
O
m outputs
O = (o0 , o1, o2 ,..., om 1 ) = F (I ) = F (i 0 , i1, i 2 ,..., i n 1 )

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Generalized Combinational Circuits

E.g., ASCII to 7-segment decoder needed for a display system
b0 ASCII ASCII to 7 segment decoder b7
b a a g f g e d c
O = (a, b, c, d , e, f , g ) = F (B ) = F (b0 , b1, b2 ,..., b7 )

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Analysis vs. Design

Analysis procedure: Given a logic diagram, find F( )
y
F(x,y,z)
F ( x, y , z ) = x i y + x 'iz
Design procedure: Given F( ), design a logic circuit that implements F( ) with minimum number of gates
F ( x, y , z ) = xy + xz '+ xy '+ w = (w ' x ' y '+ xyz )'

wx\yz 00 00 01 11 10 0 1 X 1 01 0 1 X 1 11 1 0 X X 10 1 1 X X
w x y F(x,y,z)
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Analysis
Consider this logic diagram what function does it perform?: a b F(a,b,c,d,e,f) c d
e f
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Analysis
Consider this logic diagram what function does it perform?: a b c d T1 T2 F(a,b,c,d,e,f) T3 T4 1. e f Label first level gate outputs
e f
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Analysis
Consider this logic diagram what function does it perform?: a b c d T1 T2 F(a,b,c,d,e,f) T3 T4 1. 2. T1=efa T2=efb T3=efc T4=efd Label first level gate outputs Determine Boolean functions
e f
e f
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Analysis
Consider this logic diagram what function does it perform?: a b c d T1 T2 F(a,b,c,d,e,f) T3 T4 T1=efa T2=efb T3=efc T4=efd 1. Label first level gate outputs 2. Determine Boolean functions 3. Iterate until reaching output F(a,b,c,d,e,f) = T1 + T2 + T3 + T4 F(a,b,c,d,e,f) = efa + efb + efc + efd
e f
e f
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1-161
Analysis
Consider this logic diagram what function does it perform?: a b c d T1 T2 F(a,b,c,d,e,f) T3 T4 T1=efa T2=efb T3=efc T4=efd 1. Label first level gate outputs 2. Determine Boolean functions 3. Iterate until reaching output F(a,b,c,d,e,f) = T1 + T2 + T3 + T4 F(a,b,c,d,e,f) = efa + efb + efc + efd F( ) F( ) is a 4 input MUX
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Copyright 2004 Stevens Institute of Technology All rights reserved 1-162
e f
e f a b c d
00 01 10 11
ef
Design
Design a 2-line to 4-line decoder with enable 1. Create a high-level function definition
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Design
Design a 2-line to 4-line decoder with enable A1 A0 E B3 B2 B1 B0 1. Create a high-level function definition, determine I/O requirements
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Design
Design a 2-line to 4-line decoder with enable A1 A0 E
E 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 B0 0 1 0 0 0 B1 0 0 1 0 0 B2 0 0 0 1 0 B3 0 0 0 0 1
1. 2.
B3 B2 B1 B0
Create a high-level function definition, determine I/O requirements Define truth table
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Design
E 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 B0 0 1 0 0 0 B1 0 0 1 0 0 B2 0 0 0 1 0 B3 0 0 0 0 1
1. 2. 3.
B3 B2 B1 B0
Create a high-level function definition, determine I/O requirements Define truth table Derive Boolean functions for each output
B0 = EA1A0 B1 = EA1A0 B2 = EA1A0 B3 = EA1A0
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Design
E 0 1 1 1 1 A1 X 0 0 1 1 A0 X 0 1 0 1 B0 0 1 0 0 0 B1 0 0 1 0 0 B2 0 0 0 1 0 B3 0 0 0 0 1
1. 2. 3. 4.
B3 B2 B1 B0
Create a high-level function definition, determine I/O requirements Define truth table Derive Boolean functions for each output Draw the logic diagram and verify correctness B0 = EA1A0 B1 = EA1A0 B2 = EA1A0 B3 = EA1A0 B3 B2 B1 B0
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E A1 A0
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Binary Addition Review

1-bit addition:
+ 0 1 0 0 1 1 1 0*
* carry
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1-bit addition:
+ 0 1 0 0 1 1 1 0*
* carry As two Boolean functions:

+ 0 1 0 0 1 1 1 0 + 0 1 0 0 0 1 0 1
sum
carry
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1-bit addition:
+ 0 1 0 0 1 1 1 0*
* carry As two Boolean functions:

+ 0 1 0 0 1 1 1 0 + 0 1 0 0 0 1 0 1
sum
carry
sum(a, b ) = a ' b + ab ' = a b
carry (a, b ) = ab
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Half Adder
sum(a, b ) = a ' b + ab ' = a b
carry (a, b ) = ab
a b
sum(a,b)
carry(a,b)
a b HA sum
carry
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
1-171
Full Adder
ai bi c_ini FA
sumi
c_outi
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Full Adder
ai bi c_ini
a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 cout 0 0 0 1 0 1 1 1
FA
sumi
c_outi
sum 0 1 1 0 1 0 0 1 www.UandiStar
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Full Adder
ai bi c_ini
a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 cout 0 0 0 1 0 1 1 1
ab FA sumi c 0 c_outi
sum 0 1 1 0 1 0 0 1
a 00 01 11 10
0 1 1 0 0 1 1 0
sum
b ab c 0 c 1 a 00 01 11 10
0 0 0 1 1 1 0 1
carry
b
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-174
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Full Adder
ai bi c_ini
a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 cout 0 0 0 1 0 1 1 1
ab FA sumi c 0 c_outi
sum 0 1 1 0 1 0 0 1
a 00 01 11 10
0 1 1 0 0 1 1 0
sum
b ab c 0 c 1
sum(a, b, ci ) = a b ci
a
00 01 11 10
0 0 0 1 1 1 0 1
carry
b c (a, b, c ) = ac + bc + ab o i i i
1-175
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Full Adder Implementation

a b a b HA s c a b HA s c cout cin FA s
a b ci FA s co
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Binary Adder
Multiple Full Adders can be cascaded to create an arbitrary precision adder
An-1 Bn-1
A2 B2
A1 B1
A0 B0
Cn
a s
co FA ci
Cn-1
C3
a s
co FA ci
C2
a s
co FA ci
C1
a s
co FA ci
C0
Sn-1
S2
S1
S0
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Binary Adder
Multiple Full Adders can be cascaded to create an arbitrary precision adder But there is an accumulation of delay through the carry stages AN-1 BN-1 A2 B2 A1 B1 A0 B0
CN
a s
co FA ci
CN-1
C3
a s
co FA ci
C2
a s
co FA ci
C1
a s
co FA ci
C0
Sn-1 (1 AND + 1 OR Delays) x (N-1) stages
2 XOR delays
1 AND + 1 OR delays S2 S1 S0
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Binary Adder Carry Propagation Delay

A/Bin Calculationk Calculationk+1
Sum
Calculationk
Calculationk+1
Carryi
Carryi+1
Calculationk
Calculationk+1
Carryi+2
Calculationk
Calculationk+1
Carryi+3
Calculationk
Calculationk+1 1 XOR delay ~3 gate delays 1 AND delay ~2 gate delays 1 OR delay ~2 gate delays
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Carries in Adders
Consider the 8-bit sum: 01111111 +00000001 10000000 There is a carry at each stage If the necessary carries could be scanned once in advance of the addition, incremental delays could be avoided
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Carries in Adders
C4
a HA b c s
C4 S3
P3 G3
C3
a HA b
s c
P2 G2
C2
a HA b
s c
Carry Look-ahead Generator P

1
S2
C1
S1
G1
a HA b
s c
P0 G0 S0 C0
C0 www.UandiStar
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Review of Binary Subtraction

Define: B
01001001 -00110101
x=rx
B +1
01001001 +11001011 100010100 73 -53 20
11001010+1
Is there an easy way to do the 2s complement in one step?
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1-182
Review of Binary Subtraction

Define: B
01001001 -00110101
x=rx
B +1
01001001 +11001011 100010100 73 -53 20
11001010+1
Is there an easy way to do the 2s complement in one step? A3 A2 A1 A0 M (0-plus/1-minus)

B3 B2 B = 1s complement A B1 B0 C0
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Copyright 2004 Stevens Institute of Technology All rights reserved 1-183
B+C0 = 2s complement A
Adder/Subtractor
An-1 A2 A1 A0 M Bn-1 B2 B1 B0
C V
Cn
a s
co FA ci
Cn-1
C3
a s
co FA ci
C2
a s
co FA ci
C1
a s
co FA ci
C0
Sn-1 (sign bit) If V asserted, overflow has occurred
S2
S1
S0
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Review of Multiplication
Decimal
123 x 45 615 492 5535
carries
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Review of Multiplication
Decimal Binary 123 x 45 615 492 5535 101101 x 11001 101101 no carries 000000 (replicate 000000 and 101101 shift) 101101 10001100101
carries
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2-bit By 2-bit Binary Multiplication

B1 x A1B1 C3 C2 A1 A0B1 A1B0 C1 C0 A1 B0 A0 A0B0 A0 B1 B0
a c HA s
a c HA s
C3
C2
C1
C0
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4-Bit By 3-Bit Binary Multiplier

B3 A0 B3 A1 0 B3 A2 B2 B1 B0 A3 Co A2 S3 A1 S2 A0 B3 4-bit adder S1 B2 B1 B0 S0 B2 B1 B0 B2 B1 B0
A3
A2
A1
A0 B3 4-bit adder Co S3
B2 S2
B1 S1
B0 S0
C6
C5
C4
C3
C2
C1
C0
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Uses for Decoders

Memory address expansion A0:N+2 A0:N-1 Bank 0
E
TS
Data_out
Bank 1
E AN AN+1 B0 A0 A1
TS
2-bit to 4-line
E
B1 B2 B3
Bank 2
E
TS
Bank 3
AN+2 E E
TS
2-bit to 4-line
Banks 4-7
Four 2N location Memories
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2-Line to 4-Line Decoder
E 0 1 1 1 1
A1 X 0 0 1 1
A0 X 0 1 0 1
B0 0 1 0 0 0
B1 0 0 1 0 0
B2 0 0 0 1 0
B3 0 0 0 0 1
E A1 A0
B3 B2 B1 B0
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3-Line to 8-Line Decoder

A 2N to 22N Decoder can be created from two N to 2N Decoders A2
E A1 A0
B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
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A1 A0
E A1 A0
B3 B2 B1 B0
1-191
Encoder
Encoder performs inverse operation of Decoder
1 A1 A0
B3 B2 B1 B0
B3 B2 B1 B0 A0 A1 F(A0,A1) = (A0,A1)
2-Bit to 4-Line Decoder F(A0,A1)
4-Line to 2-Bit Decoder
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Encoder Truth Table

Inputs D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1 x 0 0 0 0 1 1 1 1 Outputs y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1
x = D4 + D5 + D6+ D7 y = D2 + D3 + D6+ D7 z = D1 + D3 + D5+ D7 What should output be for input (00000000)? What about (00100100)?
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Priority Encoder
Inputs D0 0 1 X X X X X X X D1 0 0 1 X X X X X X D2 0 0 0 1 X X X X X D3 0 0 0 0 1 X X X X D4 0 0 0 0 0 1 X X X D5 0 0 0 0 0 0 1 X X D6 0 0 0 0 0 0 0 1 X D7 0 0 0 0 0 0 0 0 1 x X 0 0 0 0 1 1 1 1 Outputs y X 0 0 1 1 0 0 1 1 z X 0 1 0 1 0 1 0 1 V 0 1 1 1 1 1 1 1 1
Output encodes the largest (highest index) input that is 1. V indicates if there are any 1s in the input
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Multiplexer
I0 I1 I2 I3 S1 S0 S1 S0
I0 I1 I2 I3 S1S0 www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved
I0 I1 Y I2 I3 Y
B0 A0 A1
2-bit to 4-line
E
B1 B2 B3
00 01 10 11
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Uses for MUXes

Combining multiple information sources onto one channel
I0 I1 I2 I3 S1S0 00 01 10 11
I0 I1 I2 I3 S1 S0 Y
Time A Time A Time A Time A
B B B B
C C C C
D D D D
E E E E
F F F F
I0A I1A I2A I3A I0B I1B I2B I3B I0C I1C I2C I3C I0D I1D I2D I3D I0E I1E I2E I3E I0F I1F
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Function Implementation with MUX

With static values I[0:15], this multiplexer implements the truth table shown
S3 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 S3S2S1S0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 1
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DEMUX
I
00 01 10 11 S1S0 Y0 Y1 Y2 Y3
Y0 Y1 Y2 Y3
B0
S1 S0 DEMUX performs inverse function of MUX
A0 A1
2-bit to 4-line
E
B1 B2 B3
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Multiplexing and Demultiplexing Data Steams
Multiple input sources

S1S0
I0 I1 I2 I3
00 01 10 11
Single communications channel

I 00 01 10 11 Y0 Y1 Y2 Y3
Sequenced select lines

S1S0
Reconstituted output signals
Sequenced and synchronized select lines
Most speech signals in the telephone plant is carried on T1 transmission facility: 24 voice channels, each sampled at 8 kHz with 8 bits/channel + synchronization = 1.544 Mb/s Multiple T1s are combined to form a T3 line at ~45 Mb/s
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Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Hazards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
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Homework 5 due in Class 7

As always, show all work Problems 4-1, 4-5 (x=4, y=2, z=1), (A=4, B=2, C=1), 4-6, 4-7
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Cpe358/Cs381 Switching Theory and Logical Design Class 5

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Cpe358/Cs381 Switching Theory and Logical Design Class 5

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CpE358/CS381 Switching Theory and Logical Design Class 5

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Standard Combinational Circuits in TTL

Decoder, MUX, Encoders, Selectors, DeMUX

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Generalized Combinational Circuits

O = (o0 , o1, o2 ,..., om 1 ) = F (I ) = F (i 0 , i1, i 2 ,..., i n 1 )

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Generalized Combinational Circuits

b0 ASCII ASCII to 7 segment decoder b7

O = (a, b, c, d , e, f , g ) = F (B ) = F (b0 , b1, b2 ,..., b7 )

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Analysis vs. Design

F ( x, y , z ) = xy + xz '+ xy '+ w = (w ' x ' y '+ xyz )'

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

B0 = EA1A0 B1 = EA1A0 B2 = EA1A0 B3 = EA1A0

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Binary Addition Review

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Binary Addition Review

* carry As two Boolean functions:

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Binary Addition Review

* carry As two Boolean functions:

sum(a, b ) = a ' b + ab ' = a b

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

sum(a, b ) = a ' b + ab ' = a b

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Full Adder Implementation

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved