1 Akai LCD TV

SERVICE MANUAL
Model: LCT2716
Safety Instructions Features & Specifications Block Diagram Circuit Diagram Disassembly Schematic & Component Diagrams Bill of Material Pin Descriptions LCD Panel specification Exploded View Diagram
This manual is the latest at the time of printing, and does not include the modification which may be made after the printing, by the constant improvement of product.
I. Safety Instructions
The l ig h tn i ng fla sh w i th arro wh e ad symb ol , within an equilatera l triangle, is intended to alert the user to the presence of uninsulated dangerous voltage within the prod uct s enclosure that may be of sufficie nt mag nitud e to consti tute a risk of electric shock to persons. The excla mati on po i nt wi thi n a n e q ui l ate ra l tri a n gl e is i nte n de d to a le rt th e u se r to th e presence of important operating and maintenance (s e rv i ci n g ) i n str u ct i o n s i n th e l i te r a tu re accompanying the appliance.
CAUTION
RISK O F ELECT RIC SHO CK DO NO T O PEN
CAUTION: TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOT REMOVE COVER (OR BACK). NO USER-SERVICEABLE PARTSINSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL ONLY.
PRECAUTIONS DURING SERVICING

1. In a ddition to safe ty, othe r parts and assemblies are speci fied for conformance with such regulatio ns as those applyi ng to sp urious radiation . These must also be replace d only with specifie d replacements. Exampl es: RF converters, tun er units, a ntenna selection switches, RF cables, noise-blo cking capacitors, noise-bl ocking filters, etc. 2. Use sp ecified inte rnal Wiring . Note especially: 1) Wires covered with PVC tubing 2) Do uble insulated w ires 3) Hig h voltage leads 3. Use specified i nsulating material s for haza rdous live pa rts. Note espe cially: 1) In sulating Tape 2) PVC tubing 3) Spa cers (insu lating barriers) 4) Insula ting sheets for transistors 5) Plastic screws for fixing micro switches 4. When replacing AC primary side compo nents (tran sformers, power cords, n oise blo cking capacitors, e tc.), wra p ends o f wires securely about the te rminals be fore solde ring.
WARNING:
Before servicing this TV receiver, read the X-RAY RADIATION PRECAUTION, SAFETY INSTRUCTION and PRODUCT SAFETY NOTICE.
X-RAY RADIATION PRECAUTION

1. Excessively high can prod uce potentially hazardous X-RAY RADIATION. To avoid such hazards, the high volta ge must no t exceed the speci fied limit. The normal va lue of the high voltage of this TV receiver is 2 7 KV at zero b ean current (mi nimum b rightne ss). The high voltage must no t exceed 30 KV u nder any circu mstances. Each time when a re ceiver req uires servici ng, the high voltage sho uld be checked. The readi ng of the high voltage is re commended to be reco rded as a part o f the service record, It is important to u se an accurate and reliable high voltage meter. 2. The only source of X-RAY RADIATION in this TV receiver is the picture tube. For con tinued X-RAY RADIATION protectio n, the repla cement tube must be exactly the sa me type as specified in th e parts list. 3. Some parts in this TV receiver have special safety related characteristics fo r X-RADIATION protection. For continued safety, the parts rep lacement should be under taken only afte r referring the PRODUCT SAFETY NOTICE.
5. Make sure that w ires do no t contact heat generating parts (he at sin ks, oxide me tal fi lm resistors, fusi ble resistors, etc.) 6. Check if replace d wires do not conta ct sharply edged or po inted pa rts. 7. Make sure that foreign objects (screws, solder drop lets, etc.) do not remain insi de the set.
SAFETY INSTRUCTION
The se rvice shoul d not be attempted by anyone unfamiliar with the ne cessary i nstructio ns on th is TV receiver. The fo llowing are the necessary instru ctions to be ob served before se rvicing. 1. An isolation transformer shoul d be con nected i n the power li ne between the receiver and the AC line when a service is performed o n the primary of the conve rter tra nsformer of the set. 2. Comply wi th all caution an d safety related provided on th e back of the cabi net, inside the cabinet, o n the chassis or p icture tube. 3. To avo id a shock hazard, alw ays discharge the pictu re tube's anode to the chassis g round be fore removi ng the anod e cap.
MAKE YOUR CONTRIBUTION TO PROTECT THE ENVIRONMENT

Used batte ries wi th the ISO symbol for recycling a s well as small accumu lators (re chargeable batteries), mini-batteries (cell s) and starter b atteries should not be thrown into the garbage can. Please leave the m at an ap propriate depot.
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4. Completely discharge the high pote ntial voltage of the picture tube before handli ng. The pi cture tube is a vacuum and if bro ken, the gl ass will explode. 5. When rep lacing a MAIN PC B in the cabinet, always be certai n that all protective are installed properly such as co ntrol knobs, adjustment co vers o r shie lds, barri ers, iso lation resistor networks etc. 6. When se rvicing is re quired, observe the origin al lead dressing. Extra precau tion sho uld be gi ven to a ssure correct lead dressing in the high voltage area. 7. Keep wires away from high voltage or high te mpera ture compone nts. 8. Befo re returning the set to the customer, al ways perform an AC leaka ge current check on the exposed meta llic parts of th e cabine t, such as anten nas, termin als, screw heads, meta l overlay, control shafts, etc., to be sure the set i s safe to operate without danger of electrica l shock. Plu g the AC lin e cord directly to the AC outlet (do not use a line iso lation transformer d uring th is check). Use an AC voltmeter havin g 5K ohms volt sen sitivity or more i n the following manner. Conne ct a 1.5 K ohm 10 watt resistor pa ralleled by a 0.15F AC type capacito r, between a go od earth ground (water pipe, conductor etc.,) and the exposed metallic parts, one a t a ti me. Measure the AC vol tage across the combination of the 1 .5K ohm resistor and 0.15 uF capacitor. Re verse the AC p lug at the AC o utlet and repea t the AC volta ge measurements fo r each exposed metallic part. The me asured voltage must not exceed 0.3 V RMS. This correspo nds to 0.5mA AC. Any val ue exceeding this limit co nstitute s a poten tial sho ck hazard and must be corrected immedia tely. The resista nce me asureme nt shou ld be done betwe en accessi ble exposed metal parts and power cord plug prong s with th e power switch "ON". The resi stance should be mo re tha n 6M o hms.
AC VOLTMETER
PRODUCT SAFETY NOTICE

Many e lectrical an d mechanica l parts in this TV receiver have special safety-related characteristics. These characteri stics are offer passed unnoticed by visual spection and the protecti on afforded by them cannot necessari ly be obta ined by using replacement compon ents rates for a hig her voltag e, wattage , etc. The replacemen t parts w hich have these sp ecial safety characteristics are identifie d by marks on the schematic diag ram and on the parts l ist. Before replacin g any of these compo nents, rea d the parts list in thi s manua l care fully. The use of substitute re placemen t parts which do not have the same safety chara cteristics as speci fied in the p arts list may cre ate shock, fire, X-RAY RADIATION or other h azards.
Goo d ea rth grou nd su ch as th e wat er p ip e , c o n du c t or , etc.
Pl ace this pro be on eac h e x p os ed me t al li c part
AC Leak age Curr ent Check
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1. FEATURES
- POWER SUPPLY - MULTI TV SYSTEM - MULTISTANDARD SOUND PROCESSORS - MULTI VEDEO SYSTEM VERSATILE INPUT SOURCE : AC 90~264V 50/60Hz : NTSC M : BTSC+SAP : PAL/NTSC/SECAM : TV, AV1, AV2, S- VIDEO, YCbCr, YPbPr, DVI, PC(ANALOG) - FULL FUNCTION REMOTE CONTROLLER EXCELLENT SOUND EFFECT WITH VOLUME, TRABLE, BASS, BALANCE, AVC ADJUSTABLE AUDIO MODE, SPACIAL EFFECT, EQUALIZER - SMART SOUND SET PICTURE MODE SET - VTR FOR WEAK AND DISTORETED - SIGNAL FROM VIDEO TAPE RECORDER - AUTOMATICALLY TURN OFF THE SET WHEN - SIGNAL ABSENT LONGER THAN 10 MINUTES - 216 CHANNELS - BLUE SCREEN DISPLAY - / V-CHIP - FREEZE PICTURE - PROGRAM LABEL - SLEEP - SCREEN SIZE CHANGE - STANDBY - CHANNEL SWAP - VOG PIP (AT PC 1280X768/60Hz, TV WIDE FORMAT) : PERSONAL,CINEMA, SPEECH, MUSIC, : STANDARD,PERSONAL, MILD ,BRIGHT,
- ADAPTIVE 2/4 LINE COMB FILTER FOR PAL/NTSC
GENERAL SPECIFICATIONS ITEM DESCRIPTION

-POWER CONSUMPTION -TV RECEIVE SYSTEM -VIDEO SYSTEM -VISION INTERMEDIATE FREQUENCY -INTER-CARRIER FREQUENCY 180Watt MAX. 3Watt(STBY) NTSC M PAL/ SECAM/ NTSC 45.75MHz
4.5MHz (BTSC) CHROMA IF FREQUENCY 42.17MHz USA 216 Channel CHANNELS RECEIVED (AIR 2-83 Channel) CAT V (STD IRC HRC) 1-134 Channel TUNING MODE PLL SYSTEM 1 A V 1 in, 1 A V 2 in, 1 S-Video in AV IN / OUT Y Cb Cr in ,Y Pb Pr in 1 AV out AV IN/OUT SPECIFICATION Y/C in -Y1.0 0.2 VP-P C: 0.7 VP-P Video in ----1.0 0.2 VP-P Audio in ----Approx, 500mV Video out----1.0 0.2 VP-P Audio out ----Approx, 400mV RGB IN : ANTENNA INPUT IMPEDANCE OSD LANGUAGE AUDIO OUTPUT POWER LED INDICATORS HAND SET POWER SUPLY 75 OHM ENGLISH / SPAINISH / GERMAN / FRENCH / PORTUGUES 6Wx2 (1KHz, 0.5Vrms, 10%THD) Continue shine Power on Flash standby Battery 1.5V AAAx 2 0.7 VP-P 75 75 75 75
PART 2: PC RESOLUTION
ANALOG RGB IN RESOLUTION 640X480 800X600 1024X768 1280X720 V. Feq. (Hz) 59.940 60.317 60.004 59.870 0.7 VP-P h. Feq. (Hz) 31.469 37.879 48.363 47.776 GRAPHIC MODE VGA VGA VGA VGA
PART 3: PANEL
Brand & Model Resolution Displayable Colour Surface Viewing Angle (H/V) Display Response Time Contrast Ratio Brightness Aspect Lamp Life Bad Pixel Quality (Bright/Dark/Total) CHIMEI/V270W1-L03 1280X720 16.7MHz Hard Coating + Anti-Radiation 170 (Hor) / 170 (Ver) 25ms 1:600 550nit 16;9 50,000Hrs 2 /6 / 8
Block Diagram
1 2 3 4 5 6 7 8
U6
U8 TELETEXT
U7 CCD/VCHIP
U9
EEPRAM D
SDRAM U18
U2
U4
UC
UB BUFFER
FLASH MEMERY
BUFFER
TUNER AV IN S_VIDEO IN YCrCb U24 VIDEO SCART SWITCH U21 U19 SWITCH VIDEO DECODER DEINTERLACER UE U17 AMP
C U3 SYNC U10 PC SWITCH YPrPb ADC BUFFER U11 U14
CPU/SCALER
LVDS
LCD PANEL
UD U5 U1 EEPRAM RESET
DVI
DAC
I2C
TV AUDIO AV AUDIO AUDIO SCART AUDIO DECODER POWER AMP
HDTV AUDIO
POWER A 24VDC 11----20VDC 5VDC 5VDC_SB 3VDC_SB STAND BY A
Wiring Diagram
CN14 1 2 3 4 5 CON6 CN12 6 5 4 3 2 1 CON6 RCA1 1 2 3 TVVIN TV-VIN GND BLANKING BLANKING GND TV-AUDIO
R28 AV2_L SD R41 AV2_R SL SD SR
0 0
CON5 is for LCD control (J24's) supplement, D MUTE D
CN5 1 2 CON2 VDD PWCS0# PWD0 PWD1 PWD2 PWD3 PWD4 PWD5 PWD6 PWD7 11 3 4 7 8 13 14 17 18 CLK 1D 2D 3D 4D 5D 6D 7D 8D VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE GND 20 7 2 5 6 9 12 15 16 19 1 10 LCDON BKLON PD LVDSON 11 11 4,9 12 LED1 7 680R GREEN 74HC374 R39 R40 680R LED2 DIGSEL DIODE DIGSEL 7 BUF-VS BUF-VS HSYNC BUF-HS BUF-HS R34 22R C25 22P R36 2.2K U3 1 2 3 4 5 6 7 74hc14a R38 14 13 12 11 10 9 8 VFF
U2
MUTE
VSYNC
9,10
MEM_BUS
R35 22R C26 R37 2.2K C
22P
RCA1 2 1 1,7,9 7 7,1 7,1 GREEN 7,1

SAGND
R14 0
AV2-IN
VCC
R184 10K AV2-IN VIN4 VCC BUF-HS VCC VCC BUF-VS VCC YSOG AV2-IN VIN4 YSOG
U21 1 2 3 4 5 6 7 8 0Y 2Y YOUT 3Y 1Y INH VEE VSS VDD 2X 1X XOUT 0X 3X A B CD4052 VCC 16 15 14 13 12 11 10 9
C234 0.1 DEN DDEN DVI-DE A B1 A B1
DDCD
DDCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D1 K
R29 10K
D2
R30 10K
D3
D4
D5
BLUE
RED
D6
R44 2K
D7
R45 2K
3 B A BAV99L 1 BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L R223 10K VIN R225 10K YSOG R224 10K B
VAA VAA R64 R62 D 47 5.6K C62 4 VOUT VOUT 4.7 Q3 9014 C63 0.1 R63 22K R60 470 C64 0.1 C38 is the bypass cap for Q1 VAA R65 GND R61 470 SDO
VINHS VINVS SDA SCL
VAA
VAA
C65 0.1 R192 470 D C72 0.22 C69 33pF C73 0.22 C70 33pF C74 0.22 C71 GREEN BLUE BOX SMS CSYNC ASEL VSSA Z86229 LPF 2 3 17 8 9 R75 6.8K C67 0.1 C78 68nF 6.8nF GND GND VDD V33VT GND R69 470 33pF V-BLU V-BLU V-GRN V-GRN V-RED
R59
100
V-RED U26 bypass cap
GND 0_NS
CCVIN
R67 GND
470
U7 7 VIDEO VDD 12 16 18
VAA
R193 470 R68 470
5 13 14 15 4
GND
HS_IN VS_IN SDA SCL SEN PREF
RED
R194 470
GND VINHS VINVS SDA SCL RST1# C VAA R203 R202 47 5.6K C246 VOUT 4.7 Q2 9014 RST1# 0 R66 VAA
GND R73 10K 10 6 1 11 GND GND
D13 R74 IN4148 R76
75 75
V-BOX C75 33pF
V-BOX
C77
L8 FB
C80 V33VT 100uF/16V
C22 0.1
R204 100
39
31
44
R207 470 +12 R205 22K R206 470
D14 IN4148 VDS RED GREEN BLUE 35 34 33 32 1 30 8 7 6 5 4 3 2 21 20 19 18 17 16 52 51 48 47 46 45 29 27 15 14 DA CL V33VT 5264 C54 0.1 5 6 7 8 R210 10K R196 470
CVBS0 VDDA VDDC VDDP
L41 FB B 3 IC9 7805 IN GND OUT 1 L42 FB
GND
GND SCL SDA SCL SDA VINVS VINHS CVBS0 C21 0.1 49 50 37 36 23 24 25 26 SCL SDA VSYNC HSYNC CVBS0 CVBS1 FILT IREF
PWM PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 COR FRAME SDA_NV SCL_NV GNDA GNDC GNDP
R198 470 B
VAA
4,6,8,9
VID_BUS
R200 470
C249 100uF/16V
C208 100uF/16V
U8
GND C244 0.1 C20 0.1 24K C60 20pF R80 X2 12.000M C61 20pF 28 V33VT R209 1K Q1 9015 R232 10K 9 10 11 12 42 41 40 43 XO XI XGND RESET TEST
V33VT
R31 10K
R32 10K
A R208 5.6K RST1#
ADC0 ADC1 ADC2 ADC3
U6
SDA SCL TEST VCC GND A2 A1 A0 4 3 2 1 A
22
13
38
24C16
5 5,6,9,10,11
VOUT VOUT RST1# RST1#
C32 1nF VDD SDA SCL 13 14 70 12 15 10 9 C36 0.22 29 36 45 52 69 2 PLVDD YVDD CVDD VDD VDDCAP GNDCAP AFVDD ISVDD RST# SCL SDA VOUT TV-VIN R71 1.2K R49 AV-IN TGND R50 S-CIN R51 75 C29 0.68 R58 VIN4 G R245 R52 0_NS B R246 0_NS R R247 R54 0_NS GND GRN BLU RRED V-BOX1 C58 20pF C255 0.22 75 L11 3.3uH R55 75 C57 330pF 2 1 3 C256 0.22 79 62 X1 63 GND 20.25M 60 58 24 7 64 11 25 26 30 35 46 51 65 68 77 80 67 C254 0.22 Y1/G1 U1/B1 V1/R1 FBIN1 XTALI ASGND ASGND APGND APVDD AFGND PLGND YGND CGND I2CSEL SPGND VGAV OE# CLK5 FPDAT CLK20 ISGND ISGND ISGND GND GND R53 75 L10 3.3uH R57 75 C56 330pF C39 0.22 6 V2/R2 LLC2 LLC AVO HCLP HS VS INTLC TEST GND 75 L9 3.3uH R56 75 C55 330pF C38 0.22 4 U2/B2 VIN4 GND YSOG 75 C30 0.68 C37 0.22 75 5 VIN4 Y2/G2 72 VIN1 75 C31 1nF 71 CIN 2K C28 0.68 73 VIN2 FFIE FFWE FFRST FFRE FFOE Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 74 VSTBY SPVDD C27 0.68 76 59 VDD +5
VCC is 5V power supply from the power socket VDD is 3.3V digital power supply, +5 is 5V analog power supply for U1 VPC3230D; VTT is 5V power supply for U2 FI1256MK2 (TV Tuner)
SDA SCL SCL D 2 CN3 2 1 CON2

AV-IN SAGND
D +5 (VSTBY)
TV-VIN
VIN3
VREF VRT
78 66
VREF
19 20 21 22 23 31 47 32 33 34 37 47 38 39 40 41 42 43 44 47 48 49 50 27 28 54 55 56 57 53 16
C42 47nF GND GND
C45 10uF
C43 47nF
C46 10uF
C48 0.1
C47 10uF
GND
GND
VIDEO BUS
GND
GND VID_BUS 5,6,8,9
S-VIDEO1 S-CIN S-YIN SAGND SAGND SAGND SAGND SAGND SAGND SAGND C S-YIN 1 2 3 4 5 6 7 8 9 CON9
RP7
RP8
U4 VPC3230D
VINY7 VINY6 VINY5 VINY4 VINY3 VINY2 VINY1 VINY0
VDD
C49 0.1
C50 0.1
C51 0.1
C52 0.1
L38
L39 VINCK 11R/100MHZ 11R/100MHZ VHREF VINHS VINVS VIODD +5
17 18 C40 0.22 U22 YCr2 YCr YCb2 B YCb BY VDD BX B CY A C AY CX AX INH A VEE B VSS C CD4053 Q9 S/Y R186 1K 9014 C76 0.1 R G YY2 YY +12 GND B C34 1nF C41 0.22 C35 1nF
HD-Pb1 HD-Pb B
GND X Y 1 YCb GND 2 YY 1 YCr R212 10K YCb R214 10K YCr R216 10K YCb2 R218 10K YY2 R220 10K YCr2 R222 10K GND Y
HD-Y1 HD-Y
YY
C59 20pF
XTALO
C44 47nF C33 1nF GND
HD-Pr1 HD-Pr X 2
R248 0_NS R249 R250 0_NS 0_NS VSS 16
R185 10K
GND
V-BLU S-B V-GRN S-G
S1A S2A S1B S2B
VCC
2 3 5 6 11 10 V-BOX 14 13 1 15
DA DB
4 7 9 12
BLU GRN RRED V-BOX1
210EF
U5
SDA
U24 PI5V330
V-RED S-R GND A2 A1 A0 4 3 2 1 V-BOX RGB/V R251 6.8K
S1C S2C S1D S2D IN EN
DC DD
5 6 VDD C53 0.1 7 8
SDA SCL TEST VCC
SCL
04-CODER.SCH 4

GND
A.1
24C16
GND
30TV
7 8
2003.06.12
8 23 22 21 20 18 17 16 15 38 37 36 35 33 32 31 30 25 26 28 27 4,5,8,9 VID_BUS
VINY7 VINY6 VINY5 VINY4 VINY3 VINY2 VINY1 VINY0 VINCK VINHS VINVS
UCA PW1230
VG7 VG6 VG5 VG4 VG3 VG2 VG1 VG0 VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0 PVCLK CREF PVHS PVVS VB7 VB6 VB5 VB4 VB3 VB2 VB1 VB0 SVCLK SVHS SVVS
UCC PW1230
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DG7 DG6 DG5 DG4 DG3 DG2 DG1 DG0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DCLK DHS DVS DENR DENG DENB DEN VREFI VREFO 142 141 139 138 136 135 133 132 130 129 128 127 125 124 122 121 119 118 117 116 114 113 111 110 102 104 103 108 106 107 145 161 162 R86 R87 R88 R89 47 47 47 47
GPR7 GPR6 GPR5 GPR4 GPR3 GPR2 GPR1 GPR0 GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0
DE-INTERLACED
DISPLAY BUS (G-PORT)
G-PORT
7,8,9
RP9 47 RP10 47
UCD PW1230
MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MRAS# MCAS# MWE# MCLK MCLKFB 218 221 220 215 217 214 211 209 206 203 204 207 210 213 254 250 247 244 241 238 234 231 232 236 239 242 245 248 252 255 225 226 227 229 223
NVA13 NVA12 NVA11 NVA10 NVA9 NVA8 NVA7 NVA6 NVA5 NVA4 NVA3 NVA2 NVA1 NVA0 NVD15 NVD14 NVD13 NVD12 NVD11 NVD10 NVD9 NVD8 NVD7 NVD6 NVD5 NVD4 NVD3 NVD2 NVD1 NVD0 NVRAS# NVCAS# NVWE# NVCLK NVCLK NVA13 NVA11
PW1230 MEMORY BUS
VDD R82 0 1 3 9 14 27 43 49 0 21 20 35 22 34 33 32 31 30 29 26 25 24 23 38 18 17 16 39 15 D
R81
RP11 47 RP12 47
NVA12
BSL1 BSL0 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VCC VCC VCC VCC VCC VCC VCC
RP13 47 RP14 47
R86 470
9 8 7 6 4 3 2 1 13 11 12
PW1230C L43 FB
DDCK
NVCLK
DDHS DDVS DEN
NVRAS# NVCAS# NVWE#
RAS# CAS# WE# CKEN UDQM LDQM VSS VSS VSS VSS VSS VSS VSS CS#
U9
CLK
K4S641632C
NVA10 NVA9 NVA8 NVA7 NVA6 NVA5 NVA4 NVA3 NVA2 NVA1 NVA0
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
53 51 50 48 47 45 44 42 13 11 10 8 7 5 4 2
NVD15 NVD14 NVD13 NVD12 NVD11 NVD10 NVD9 NVD8 NVD7 NVD6 NVD5 NVD4 NVD3 NVD2 NVD1 NVD0
VDD 37 19 C
DEN
PW1230E
9 PW1230E 7,8,9
+3.3 C81 0.1 BGND COMP 160 153 150 C82 0.1 156 159 R92 316 BGND VDD VYY VZZ VXX C110 0.1
VDD R90 3.3K R91 3.3K C112 X3 10MHz 20pF 146 201 40 R93 2.2M
6 12 28 41 46 52 54
UCE PW1230
CGMS MVE XTALI MCUA7 MCUA6 MCUA5 MCUA4 MCUA3 MCUA2 MCUA1 MCUA0 MCUD7 MCUD6 MCUD5 MCUD4 MCUD3 MCUD2 MCUD1 MCUD0 MCUCS# MCUWR# MCUCMD MCURDY 177 176 174 173 172 170 169 168 186 185 184 183 182 181 179 178 B 190 191 192 188
1,7,8
GRAPHIC
GRAPHIC
UCB PW1230
GR7 GR6 GR5 GR4 GR3 GR2 GR1 GR0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 GCLK GFBK GVS
Y/GA U/BA
100 99 98 97 95 94 92 91 89 88 87 86 84 83 82 81 79 78 76 75 73 72 71 70 68 66 67
GR7 GR6 GR5 GR4 GR3 GR2 GR1 GR0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0 GCLK GHS GVS
C83 0.1
C84 0.1
C85 0.1
V/RA RSET
41 47 45 55
XTALO SDA SCL RST# CSA2 CSA1 TEST TSTCLK TRST# TCK TDI TDO TMS
VXX
+2.5
+3.3
SDA SCL RST1#
SDA SCL RST1#
C113 20pF
14 29 42 54 64 69 80 90 101 109 120 131 143 165 180 200 208 216 224 230 237 243 249 256
197 199
149 163 166
5 34 93 123 140 175 205 235
151 154 157
R191 58 60 10K VYY VZZ
44 43 56 144 53 50 51 48 52
VDD VDD VDD VDD VDD VDD VDD VDD
PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD PVDD
DPAVDD DPDVDD
MPDVDD MPAVDD
ADDVDD ADAVDD ADGVDD
AVD33B AVD33G AVD33R
UCF PW1230
MPDVSS MPAVSS ADDVSS ADAVSS ADGVSS DPAVSS DPDVSS AVS33B AVS33G AVS33R PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS PVSS VSS VSS VSS VSS VSS VSS VSS VSS
C86 0.1
C87 0.1
C88 0.1
C89 0.1
BGND
19 49 77 112 134 187 219 251
10 24 39 46 57 65 74 85 96 105 115 126 137 147 171 189 193 202 212 222 228 233 240 246 253
196 198
59 61
148 164 167 BGND
BGND BGND VDD A C90 0.1 C91 0.1 C92 0.1 C93 0.1 C94 0.1 C95 0.1 C96 0.1 C97 0.1 C98 0.1 C99 0.1 C100 0.1 C101 0.1 C102 0.1 C103 0.1 C104 0.1 +2.5 +3.3
152 155 158 BGND VDD A C106 0.1
C105 0.1
C107 0.1
C108 0.1
C109 0.1
BGND
VEE SDA SCL HD-Y HD-Y D 2 HD-Pb GND HD-Pb X Y 2

SDA SCL
VFF
VDD1
VEE
GRAPHIC
GRAPHIC
1,6,8
26 27 39 42 45 46 51 52 59 62
C132 3.9nF
AVD AVD AVD AVD AVD AVD AVD AVD AVD AVD
VDD VDD VDD VDD VDD VDD
R106 3.3K
R94 75 GND L13 HfFB R95 75 GND L14 HfFB R96 75 VDD R97 10K 10
R104 3.3K R105 3.3K
Bypass cap for U9

VGAHS
PVD PVD
L12 HfFB
HD-Y
VDD
VSS
C136 39nF
11 22 23 69 78 79
34 35
VFF 70 71 72 73 74 75 76 77 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 67 66 65 64 R112 R113 R114 R115 47 47 47 47

GR7 GR6 GR5 GR4 GR3 GR2 GR1 GR0 GG7 GG6 GG5 GG4 GG3 GG2 GG1 GG0 GB7 GB6 GB5 GB4 GB3 GB2 GB1 GB0
C114 0.1 VSS
33 57 56 55 RED S1A S2A S1B S2B U10 PI5V330 S1C S2C S1D S2D IN EN VCC DA DB DC DD GND 4 7 9 12
RED
FILT SDA SCL A0
HD-Pb
VGAVS
16
GND
HD-Pr VGA-R HD-Y VGA-G
GND HD-Pr HD-Pr X Y 2
HD-Pr
2 3 5 6 11 10 14 13
1,3 1,3
C133 47nF C134 47nF C137 1nF C135 47nF
RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 GRN7 GRN6 GRN5 GRN4 GRN3 GRN2 GRN1 GRN0 BLU7 BLU6 BLU5 BLU4 BLU3 BLU2 BLU1 BLU0 DATCK HSOUT SOGOUT VSOUT
RP15 47 C115 0.1 RP16 47 GND RP17 47 RP18 47 C122 0.1 RP19 47 RP20 47 FB
GCLK GFBK GHSSOG GVS
C116 0.1
C117 0.1
C118 0.1
C119 0.1
54 48 49 43 30 31 29
RAIN GAIN SOGIN BAIN HSYNC VSYNC COAST REFBYP MIDSCV CLAMP
GREEN
GREEN
VDD1
GND GND VGA
L16 HfFB R98 GND L17 HfFB R99 75 GND L15 HfFB R100 75 75
VGA-B
HD-Pb VGA-B
BLUE
BLUE
1,3
9 5 PIN9 4 3
VGABI VGAGI VGARI
U11 AD9883A
C126 0.1
C127 0.1
15 9 14 8 13 7 12 C 6 11
VGA-G
1 15
HSYNC VSYNC
2 1
VEE
VDD C C123 0.1 C125 0.1 C128 0.1
VGA-R
GND
BUF-HS 1,3
58 37 38
L44
VGAHS VGAVS DDCC
BUF-VS
1,3
GND GND C120 0.1 C121 0.1
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
DDCD
DB15
GND
GND
1 UAA 74LV126 3
GND 1 10 20 21 24 25 28 32 36 40 41 44 47 50 53 60 61 63 68 80
9 9
VGASEL GCOAST PW1230E PW1230C
VGASEL GCOAST
Bypass caps for U10 and U11 GND
6,8,9 6
PW1230E PW1230 CLK & SYNCs
PW1230E
G-PORT
G-PORT 6,8,9
10 9 UBC 74LV126 8
DDCK
GPCLK
9 B
FLASHEN
FLASHEN
13
R107 3.3K 6
U12 MAX232A
4 1 5 UAB 74LV126
TXD
VCC
DDHS
12
UBD 74LV126 11
GPSOG
C1P C1M TIN1 TIN2 ROUT1 ROUT2 C2P C2M
VCC GND TOUT1 TOUT2 RIN1 RIN2 VP VM
16 15 14 7 13 8 2 6 C141 0.1 PCRXD PCTXD U23 24LC21A 6 5 SCL SDA VCLK VCC GND NC NC NC 4 A 3 2 1 C140 0.1
DDVS 9 RXD 9 TXD CN9 DDHS
3 11 10 12 9 4
1 2 UBA 74LV126 3
C138 0.1 R116 200 R117 200
GPFBK
4 5 UBB 74LV126 6
R108 3.3K 12
13
VDD
DDCC
DDCC
11 UAD 74LV126 10
DDCEN
RXD
GPVS
R118 8.2K
VDD
R119 1K
C139 0.1 VDD
UAC 74LV126 8 U13 24LC21A 1,9 A 1,3,9

GSCL GSCL GSCL GSDA( DDCD )
Q4
R111 3.3K
R3 9014 VDD GND NC NC NC 4 3 2 1 DVC1 D16 D9 VCC DIODE 2 VCC 3 4 DIODE C129 0.1 C130 0.1 C131 0.1 D10 DIODE VCC R4 3.3K R5 0
1 2 3 CON3
6 5 7 8 R33 10k
SCL SDA VCLK VCC
DDCD
3.3K GSCLV DDCDV R6 R7 0 10K
VDD
R109 3.3K R110 3.3K
7 8
PIN9
D8 DIODE
A.1
VDD1
7 18 31 42
1,6,7
GRAPHIC
GRAPHIC
VDD1 47 46 44 43 1 1A1 1A2 1A3 1A4 1OE 2A1 2A2 2A3 2A4 2OE
BUFFERED GRAPHIC BUS (G-PORT)
G-PORT
6,7,9
1Y1 1Y2 1Y3 1Y4
2 3 5 6 VXX L21 FB L22 FB L23 FB VYY VYY VZZ +2.5
VCC VCC VCC VCC
VDD1
GVS GHSSOG GFBK GCLK
41 40 38 37 48
2Y1 2Y2 2Y3 2Y4
8 9 11 12
GPVS GPSOG GPFBK GPCLK
VZZ
C165 47uF/16V
C166 47uF/16V
C167 47uF/16V
C142 0.1
C143 0.1
GR7 GR6 GR5 GR4
U14
36 35 33 32 25
LVC16244
3A1 3A2 3A3 3A4 3OE 4A1 4A2 4A3 4A4 4OE
3Y1 3Y2 3Y3 3Y4
13 14 16 17
GPR7 GPR6 GPR5 GPR4
+2.5 BGND BGND BGND
Bypass caps for U27

GR3 GR2 GR1 GR0
VYY is 2.5V display PLL power supply of U7, VZZ is 2.5V memory PLL power supply of U7, 19 20 22 23
GPR3 GPR2 GPR1 GPR0
30 29 27 26 24
4 10 15 21 28 34 39 45
GND GND GND GND GND GND GND GND
4Y1 4Y2 4Y3 4Y4
VCC VDD1 3 7 18 31 42
IC2 LT1117
VIN ADJ VOUT 2
VXX L24 FB
VXX
GG7 GG6 GG5 GG4
47 46 44 43 1
1A1 1A2 1A3 1A4 1OE 2A1 2A2 2A3 2A4 2OE
1Y1 1Y2 1Y3 1Y4
2 3 5 6
GPG7 GPG6 GPG5 GPG4
R129 300
VCC VCC VCC VCC
C168 100uF
R128 300
1
VADJ125
VDD1
GG3 GG2 GG1 GG0
41 40 38 37 48
2Y1 2Y2 2Y3 2Y4
8 9 11 12
GPG3 GPG2 GPG1 GPG0
VXX is 2.5V core power supply of U7 (PW1230)
C155 0.1 B
C156 0.1
GB7 GB6 GB5 GB4
Bypass caps for U28

GB3 GB2 GB1 GB0
25 30 29 27 26 24
3OE 4A1 4A2 4A3 4A4 4OE 4Y1 4Y2 4Y3 4Y4 19 20 22 23
GPB3 GPB2 GPB1 GPB0
6,7,9
PW1230E
PW1230E
4 10 15 21 28 34 39 45
GND GND GND GND GND GND GND GND
U15
36 35 33 32
LVC16244
3A1 3A2 3A3 3A4
3Y1 3Y2 3Y3 3Y4
13 14 16 17
GPB7 GPB6 GPB5 GPB4
A.1
4,5,6,8 6,7,8
VID_BUS G-PORT
VIDEO BUS G-PORT ROMOE# ROMWE# PWA19 PWA18 PWA17 PWA16 PWA15 PWA14 PWA13 PWA12 PWA11 PWA10 PWA9 PWA8 PWA7 PWA6 PWA5 PWA4 PWA3 PWA2 PWA1 PWD15 PWD14 PWD13 PWD12 PWD11 PWD10 PWD9 PWD8 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0 PWNMI
MEMORY BUS DISPLAY PORT
MEM BUS MEM_BUS
3,10 11,12
D-PORT
VLL
VDD1
VPP
194 195 196 197
164 173 174 175 176 177 178 179 180 181 182 183 184 187 188 189 190 191 192
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
PWCS0#
PWNMI
10
16 37 65 84 137 185
29 52 72 86 104 123 140 171 208
165 167
199 198
193
VLL D
D VDDP VDDP
PWXO
VDD1 VDD1 VDD1 VDD1 VDD1 VDD1
VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3
WR RD ROMOE ROMWE
PWXI
NMI
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CS1 CS0
X4 14.318 R130 2.2M 56 55 54 51 50 49 48 47 71 75 74 70 69
C169 0.1 129 130 131 132 133 134 135 136 119 120 121 122 125 126 127 128 111 112 113 114 115 116 117 118 96 97 98 99 100 101 102 103 88 89 90 91 92 93 94 95 76 77 78 79 80 81 82 83 107 106 109 108 110
DRO7 DRO6 DRO5 DRO4 DRO3 DRO2 DRO1 DRO0 DGO7 DGO6 DGO5 DGO4 DGO3 DGO2 DGO1 DGO0 DBO7 DBO6 DBO5 DBO4 DBO3 DBO2 DBO1 DBO0 DRE7 DRE6 DRE5 DRE4 DRE3 DRE2 DRE1 DRE0 DGE7 DGE6 DGE5 DGE4 DGE3 DGE2 DGE1 DGE0 DBE7 DBE6 DBE5 DBE4 DBE3 DBE2 DBE1 DBE0 GND DCLK D-HS D-VS D-EN
C171 0.1
C173 0.1
C186 20pF Clock generation circuit
C187 20pF
VYUV7 VYUV6 VYUV5 VYUV4 VYUV3 VYUV2 VYUV1 VYUV0 VCLK VHS VVS VPEN VFIELD
DRO7 DRO6 DRO5 DRO4 DRO3 DRO2 DRO1 DRO0 DGO7 DGO6 DGO5 DGO4 DGO3 DGO2 DGO1 DGO0 DBO7 DBO6 DBO5 DBO4 DBO3 DBO2 DBO1 DBO0
RP27 47 VLL RP28 47 C170 0.1 RP29 47 RP30 47 C172 0.1 C174 0.1
VHREF VIODD IRIN
VDD1
R134 1K C R131 6.8K R132 470 VCC1 CN6 1 2 3 CON3

GPR7 GPR6 GPR5 GPR4 GPR3 GPR2 GPR1 GPR0 GPG7 GPG6 GPG5 GPG4 GPG3 GPG2 GPG1 GPG0 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 GPCLK GPSOG GPVS DDEN GPFBK
RP31 47 RP32 47
C175 0.1
C177 0.1
C179 0.1 C
27 26 25 24 23 22 21 20 19 18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 31 33 32 34 35 36
GRE7 GRE6 GRE5 GRE4 GRE3 GRE2 GRE1 GRE0 GGE7 GGE6 GGE5 GGE4 GGE3 GGE2 GGE1 GGE0 GBE7 GBE6 GBE5 GBE4 GBE3 GBE2 GBE1 GBE0 GCLK GHSSOG GVS GPEN GFBK GCOAST
VDD1 RP33 47 C176 0.1 RP34 47 C178 0.1 C180 0.1 D-VS VDD1 R142 0 R143 0 D-HS
U17 PW113
IR input circuit R56 may not be stuffed
DRE7 DRE6 DRE5 DRE4 DRE3 DRE2 DRE1 DRE0 DGE7 DGE6 DGE5 DGE4 DGE3 DGE2 DGE1 DGE0 DBE7 DBE6 DBE5 DBE4 DBE3 DBE2 DBE1 DBE0 DCLKn DCLK DHS DVS DEN
RP35 47 RP36 47
GCOAST
GCOAST
C181 0.1
C183 0.1
C185 0.1
VDD1
VDD1
RP37 47 RP38 47
VPP CN10 C182 0.1 C184 0.1 SDA SCL RST1# 1 2 3 4 CON4 AGND KEY6 KEY7 D17 DIODE D18 DIODE KEY1 B
B R135 3.3K R136 3.3K DDEN

SCL SDA
GCOAST
R133 R138 R139 R140 R141 CN13 CON2 1 2
470 47 47_NS 47_NS 47
XT_OUT
TEST EXTRST
PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0
PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
TRST TCK TMS TDI TDO
VSSP VSSP
VSS1 VSS1 VSS1 VSS1 VSS1 VSS1
VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3 VSS3
VLL is 1.8V core power for U15
VDD1 17 38 66 85 138 186 1 30 53 73 87 105 124 141 172 142 28 64 63 62 61 60 59 58 57 46 45 44 43 42 41 40 39 166 168 139 169 170 147 146 145 144 143 200 201 202 203 204 ) 205 206 207 67 68 TXD 7 RXD 7 TXD RXD SCART SW FLASHEN VGASEL PW1230E A BLANKING
PWMOUT
RST#
PWXI
PWXO
IRIN GSCL DDCD SCL SDA
KEY7 KEY6 KEY5 KEY4 KEY3 KEY2
R137 3.3K RST# RST1#

RST#
Q16 9015 A 11 1,7 1,3,7 PWMOUT GSCL DDCD SCL SDA

PWMOUT
RST1#
RST1#
GSDA(
R227 3.3K
AGND R234 3.3K
1 SCART 2 SW FLASHEN 7 7 VGASEL PW1230E 6,7,8 3 A BLANKING R183 1K R228 1K
S/Y B1
RXD TXD
I2C pull-up resistors
PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0
RESET
XT_IN
R226 1K
GSCL GSDA( SCL SDA
VDD1
DDCD )
KEY1
KEYBOARD BUS
KBD_BUS
11
A.1
3,9 D
MEM_BUS
MEMORY BUS
JP1 JMP VDD1

FVPP FWP#
VDD1 3 1 0 R144 3.3K R145 3.3K VDD1 SW1 NMI

RNMI
4 2 R233
Short JP1 3-4 when writing flash Short JP1 1-2 for write protect. For AMD single power flash, this jumper is not used. UDA 74ACT32 3 2 R146 3.3K C188 0.1 R153 200 R147 3.3K
PWNMI
37
13 14
VDD1 VCC VPP WP#

PWA19 PWA18 PWA17 PWA16 PWA15 PWA14 PWA13 PWA12 PWA11 PWA10 PWA9 PWA8 PWA7 PWA6 PWA5 PWA4 PWA3 PWA2 PWA1
16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 28 11 12 26
A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE# WE# RST# CE#
BYTE# A-DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A20/NC A19/NC RY/BY# VSS VSS
47 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 10 9 15
PWD15 PWD14 PWD13 PWD12 PWD11 PWD10 PWD9 PWD8 PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0
PWNMI
U17 bypass cap
RNMI
VDD1
VDD1 UDB 74ACT32 6 5 VDD1 1 3 HD2 C D12 DIODE SW3 NMI C232 0.1 C233 47uF 0 R179
29LV800D
C189 0.1
C190 0.1
HD1 2 4
RST#
ROMOE# ROMWE# RST#
U18
RST#
U16 bypass cap
R178 0_NS
FCE#
27 46
R148 3.3K JMP1 JMP

FCE#
VDD1 2 4 Short JP2 when using PROMJET or ICE ROM Emualtor, open it when using flash normally.
1 3
PROMJET
PWA2 PWA4 PWA6
PWA9 PWA11 PWA12 PWA14 PWA17 PWA19
ROMOE# PWD15 PWD14 PWD5 PWD4 PWD3 PWD2 PWD9 PWD8
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
ICE#
VDD1 PROMJET1
VDD1
PWA1 PWA3 PWA5 PWA7 PWA8 PWA10 IRP# ICE# PWA13 PWA15 PWA16 PWA18 IA20 IA21 ROMWE# PWD7 PWD6 PWD13 PWD12 PWD11 PWD10 PWD1 PWD0
R149 3.3K IRP# R150 3.3K R151 3.3K R152 3.3K
VDD1
VDD1
IA20 IA21
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
KBD BUS
KBD_BUS
D VDD1 1 3 5 7 9 KBD1 KBD 2 4 6 8 10
R158 10K
R159 10K
R160 10K
R161 10K
R162 10K
R163 10K
R164 10K
R165 10K
KEY0 KEY2 KEY4 KEY6
+12
KEY7 KEY5 KEY3 KEY1
+12 8
C193 0.1
R166 10K
3 2
UEA LM358 1 BKLIGHT1 R188 2K R190 300R U18 bypass cap BKLIGHT
PWMOUT
C192 0.1 4 R167 10K R168 10K
C VCC C250 +12 is 12V power supply
VDD1 R46 2K C196 47uF/16V R47 UDC 74ACT32 8 10 D11 R169 1N4148 10K R170 2K 2K Q5 9014
R154 510
100uF/16v
Q7 T3904 CN2 R48 2K R171 3K R155 0 1 2 3 CON3
9 3 3
PWMOUT BKLON LCDON
PWMOUT BKLON
LCDON
B MOSFET1 MOSFET P 1 2 3 1 2 3 +12 M5V C194 0.1 R173 3.3K Q8 J279 LCDVCC C197
R172 3.3K
C195 0.1
Q6 9014
1000uF/16v
9,12 LVDSON
DISPLAY PORT
DISPLAY PORT
9,11 D
D-PORT
VDD
LVDSON
LVDS BUS
+5V
DRO1 DRO3 DRO5 DRO7 DGO1 DGO3 DGO5 DGO7 DBO1 DBO3 DBO5 DBO7 D-HS DCLK
TTL1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
DRO0 DRO2 DRO4 DRO6 DGO0 DGO2 DGO4 DGO6 DBO0 DBO2 DBO4 DBO6 D-EN D-VS
1 9 26
32
CON1 47 48 45 46 41 42 37 38 39 40
TXE0P TXE0M TXE1P TXE1M TXE2P TXE2M TXE3P TXE3M TXECP TXECM
DRE0 DRE1 DRE2 DRE3 DRE4 DRE5 DRE6 DRE7 DGE0 DGE1 DGE2 DGE3 DGE4 DGE5 DGE6 DGE7 DBE0 DBE1 DBE2 DBE3 DBE4 DBE5 DBE6 DBE7 D-HS D-VS D-EN
51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31
R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HSYNC VSYNC ENABLE CNTRL CLOCK R/F
OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 CLKOUT CLKOUT
TXE3P TXE3M TXECP TXECM TXE2P TXE2M
VDD
VOO
VNN
C198 0.1
C199 0.1
C200 0.1
C201 0.1
C202 0.1
U19 DS90C383A
LVDSVC LVDSGD LVDSGD LVDSGD
VOO 44 36 43 49 AGND VNN PLLVCC 34 33 35 LCDVCC AGND TXE3P TXE3M TXECP TXECM TXE2P TXE2M TXE1P TXE1M TXE0P TXE0M TXO3P TXO3M TXOCP TXOCM OUT0 OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 CLKOUT CLKOUT 47 48 45 46 41 42 37 38 39 40
TXO0P TXO0M TXO1P TXO1M TXO2P TXO2M TXO3P TXO3M TXOCP TXOCM
TXE1P TXE1M TXE0P TXE0M
AGND C Bypass caps for U20
AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CON2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VCC VCC VCC
PWDN
HEADER 18X2_NS
TTL2
DRE1 DRE3 DRE5 DRE7 DGE1 DGE3 DGE5 DGE7 DBE1 DBE3 DBE5 DBE7
CON30
VDD
VOO
VNN
DCLK
PLLGND PLLGND
C203 0.1
C204 0.1
C205 0.1
C206 0.1
C207 0.1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
DRE0 DRE2 DRE4 DRE6 DGE0 DGE2 DGE4 DGE6 DBE0 DBE2 DBE4 DBE6
17
5 13 21 29 53
GND GND GND GND GND
LCDVCC
AGND
AGND VDD LVDSON
HEADER 18X2_NS
Bypass caps for U21
R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 HSYNC VSYNC ENABLE CNTRL CLOCK R/F
PWDN
VCC VCC VCC
1 9 26
32
DRO0 DRO1 DRO2 DRO3 DRO4 DRO5 DRO6 DRO7 DGO0 DGO1 DGO2 DGO3 DGO4 DGO5 DGO6 DGO7
51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31
TXO2P TXO2M TXO1P TXO1M TXO0P TXO0M
CON30_NS
VOO is 3.3V LVDS power for U20 and U21,

DBO0 DBO1 DBO2 DBO3 DBO4 DBO5 DBO6 DBO7
U20 DS90C383A
LVDSVC LVDSGD LVDSGD LVDSGD
VOO 44 36 43 49 AGND VNN PLLVCC 34 33 35 AGND A
D-HS D-VS D-EN
GND GND GND GND GND
DCLK
PLLGND PLLGND
17 1 2 3
5 13 21 29 53
VCC D
VSS
+5
VCC
VCC
+12
+12 VCC1
C209 47uF/16V VSS GND
C210 47uF/16V
C217 100uF
C221 470uF
C218 100uF
C222 470uF
IC5 LT1117
3 VIN ADJ VOUT 2
VLL L29 FB L30 FB
VPP
L26 FB
GND R174 300
R175 680
1
V125ADJ
L27 FB
+5
VLL is 1.8V core power of U15,
VCC1 3 VCC1 POWER1 8 7 6 5 4 3 2 1 CON8 VCC1 3 VCC1 VCC M5V +12 C219 470uF C225 100uF C226 100uF C124 470uF VDD1 CN11 1 2 3 CON3 VCC1 VDD1
IC7 LT1117
VIN ADJ VOUT 2
VEE L31 FB
VEE
C211 47uF/16V
GND
VEE is 3.3V PLL power for U10
IC8 LT1117
VIN ADJ VOUT 2
VFF L35 FB
VFF
C216 47uF/16V
J28' and J28" are supplementary power sockets
GND
VFF is 3.3V analog power for U10 B VDD 1 L32 FB V33VT 2 C223 470uF VCC 3 VDD L33 FB L34 FB L37 FB VNN VNN VOO +3.3 VLL VPP V33VT B
IC4 LT1085CM
VIN GND VOUT 2
VDD L36 FB VDD VDD
VOO
C212 47uF/16V
C213 47uF/16V
C214 47uF/16V
C231 100uF/16V
C215 47uF/16V
CK3 is the decoupling cap for VLL,
+3.3 GND GND GND GND
C220 100uF
C224 470uF
1
D2
2
L5
3
T2
4
D10
100uF450v
5
L12 5UH/5A
6
CN5,CN8 HDR1X10
100UF/450V
3300UF/35V
C19
103/1KV
L4
MUR480E
D3 MUR860T
150pf1kv
C7
C23
R20 68K/5W 2
3 4
500
MBR20200
C37
10
2200PF200V
400UH2A
Q1 FQP18N50
0.1UF400V
R14 1M
C9
500
L4
L7
500
C4
D4
R3
1N4148
C5 105/400V
L3
500
R15 1M
47
15V 1/2W C64

104/50V
MUR180E
10
47k
12
R26 47K
D12
R55 47R2W
C62 221/1KV
L14
ZD2
3300UF35V
0R FR107 C28 100UF25V
C61,47
3300UF35V
C50
0.1UF50V
R31
D13
C49
5UH
OUT 24V/5A
C60
11
RS606 D1
C12
C28
100uf25v
C10 0.01
0.1
8 5
D91N4148
C21
Q2
150p1kv
R36 4.7K
C44,C45 2200UF25V
C58 0.1
CN6 HDR1X8 GND GND

+5 +5 +5 +5 +11~16V +11~16V
C6
U1
0.22
RT1
U3 NCP1377DR2
1 4
10
R16 47K
STW12NK80Z
R19
L15 10UH3A
8OH5A
MC33260D
L1 20mH3A
R25 300
C25
CA1
C29 2200P
PH3
PC817B
R35 1K
R38
2200uF25V
R33
ZD1
C31
C59,C60
C8 1000PF
C3 2200P
C1 2200P
R9 0.51 5W
100P 100P
47UF/25V
12K
10K
0.24/5W
C22
10
C17
TL431ACLP
R2
R27
Q12 MTP50P03HD
104
51K
R34 R37 6.2K 100K
R24
R54 10K
Q13
U5
100P
11,12
MBR20100
5UH
C54
C20
9,10
C16
R17 68K5W 2
R53 1K/1W
C33 C36 25V/2200uF
2N5551 R56 10K
+5V Q9 MTP50P03HD
L16
0.1
R1 1K
15V 1/2W D18
T1
L9
25V/2200uF C43
R41 5.1k
C44 10UH1A 1000UF10V
C55
HDR1X2 CN4
+5
G
D17
68UF450V
0.22UF275V
25V/2200uF
D5 1N4007 U2
103 1KV
L8 5UH
L17
25V/2200uF
7,8
L2 20mH3A
8
7
D8 MUR180E
1
2
NCP1203P60
FQP7N80
10 R21 5
.
4
5
C30 333_NS
R30 100_NSR42
5.1K
2N5401
1K
Q4
D11 MBR1100 R10 10
R44 1.5K
1000UF10V
3 6
MBR20100
C40
L11 5UH
CN7 GND HDR1X5
R46
Q11
C32,C35
R48
5UH
5UH8A L13
C53
+11~16V +11~16V GND GND +5

C56 1000UF10V
C4 0.68UF/275V R60
6
5
R8
D7 1N5819
3
4
10
PH1
Q3 MTP50P03HDL
R23 10
1K R22
1K
C27 0.1
C24 0R
RV1 2.2M 1/4W 5W 2 10D471
R43 2K
1000UF10V
C51 GND
B
U6
CN3 HDR1X3
3.15A/250V
1K
150P1KV
FU1
R12
C15
PC817B
R29 1K
U4 TL431ACLP
R28 4.7K
LM1085IT-3.3
R18 2K
PC817B
PH2
1000UF10V
C46
1000UF10V
R39 5.1K
C41
C45 0.1
+5 +3.3 GND
C42
C11
MBR1100
C13 101
R11 47K
R13 0.51/5W
C18
10UF50V
D6
R7 100R
Q14 2N5551
Q4 2N5551
0.1
R49 1K
SB
100UF25V
SW1
C26 2200P
CN2
+5V
R61 10K
R65 2K
47UF/16V
Q15 2N5401
CN1 5A500V
R62 5.1K
IN:AC 100V-240V
R63 1K
C56
R64 10K
Q17 2N5551
Q16 2N5551
1 L2 FB 1 2 3 4 CON4
CN1
VCC1 CN2 3 2 1 CON3 IF AGND TV_AUDIO CN6 2 1 CON2 AV-IN AGND4 CN7 2 1 CON2 TV_VIN AGND3
CN10 6 5 4 3 2 1 CON6 SL AGND SR SCART_L AGND SCART_R CN3 2 1 CON2 MUTE AGND
CN5 4 3 2 1 CON4 AGND RST1# SCL SDA VHH 3
IC1 LT1117
VIN ADJ VOUT 2
VBB L3 FB 5
C1 470uF/16V C3 0.1
VHH R10 560R C43

V125ADJ
VHH
VHH
VHH
VHH VCC1
R9 3K L4 FB VCC
C56 1000uF
C57 1000uF
C58 1000uF
1000uF VHH
VCC 11 12 13
IF
VCC1 65 66
VBB 39
C41 470uF
C36 0.1
C40 0.1
C2 100pF
R1 1K C13 56pF
U1 56pF C15 67 68 69 60 0.33 57 56 54 53 51 50 48 47 73 74 77 VCC 78 80 79 4 5 7 17 6 8 9 10 3 2 21 C28 0.1 ANA_IN1+ ANA_INANA_IN2+ MONO_IN CAPL_M SC1_IR SC1_IL CAPL_A SC2_IR SC2_IL XT_OUT SC3_IR SC3_IL XT_IN SC4_IR SC4_IL TP AUD-CL_OUT D_I/O1 D_I/O0 STANDBYQ A-SEL 12S_CL 12S_WS 12S_I1 12S_I2 12S_DO ADR_DA ADR_WS ADR_CL SDA SCL DVSS DVSS DVSS AVSS AVSS RESET SC1_OR SC1_OL SC2_OR SC2_OL DACM_R DACM_L DACM_S DACA_R DACA_L VREF-T AHVSS AHVSS VREF1 VREF2 AGNDC TEST ASG ASG ASG AHVSUP DVSUP DVSUP DVSUP AVSUP AVSUP C14 VCC VCC1 VBB
TV_AUDIO
R22 C4 R23 AV-AR 10K AV-AL SR C7 SL
R2 0.33 C5 0.33 C6
1K
56pF C12
VBB 40 38 72 X1 18.432 71 36 37 33 34 27 DACM-R 28 DACM-L 30 24 25 58 45 70 C21 10uF C34 0.1 C47 4.7 C35 0.1 AGND1 AGND1AGND1 AGND1 VOL-R VOL-L R18 47K R19 47K R20 47K C16 10uF C17 10uF C22 20pF C23 20pF AGND1
DACM-R
C18 10uF
C31 0.1
C37 470pF
C52 1.5nF
C19 10uF
C32 0.1
C38 470pF
C53 1.5nF
C20 10uF
C33 0.1
C39 470pF
C54 1.5nF
10K
C26 1nF AGND1 C27 1nF The bypass caps for U5. DVSUP, AVSUP and AHVSUP pin each has 3 caps.
HD-AR HD-AL
0.33 0.33
PC-AR PC-AL
DACM-L
PHO 3 2 1 CON3 AGND PL PR PR PL SCART_R SCART_L C8 0.33 C9 0.33 C10 0.33 C11 0.33 VBB
VHH 16 VCC2 3 U2 C29

AMPIN-L
8 6 9 12 VHH 5 R7 10K 10 13 11 C48 R8 10K 22uF C42 220uF
VCC1
C30
0.1uF/16V
AMPIN-R
IN1+ IN2+
OUT1+ OUT2-
1 4 17 14
CN8
1 2
CON2
0.1uF/16V R21 47K
IN3+ OUT4+ IN4+ MODE2 MODE1 CIV SGND SVR GND2 GND1 OUT3-
CN9
1 2
C49 100uF/16V
CON2
AGND1
SDA SCL
15 2 CON6
R35 1K
R36 1K
R37 R38 1K 1K
RST1#
VHH D1 C51 IN4148 470u/16V Q4 R29 10K 9015
C61 220uF R34 100R R13 3K
B 7
3450 14 15 16 61 62 43 44 35 26 49 52 55
VCC R3 10K R26 10K R30 3K VCC Q7 9014 Q8 9014 R33 1K
Q1 9014
Q3 9014
R6 3.3K
MUTE
TV_AUDIO
R24 10K R25 10K
Q5 9014 C55 L-R TV_VIN R27 10K 100uF/16V 100uF/16V C59
R31 5.1K R28 1K Q6 9014 R4 10K C60 TV_VIN1 100uF/16V R12 220R RST1# R32 2K
A.1
CN1 M5 TUNER 1 +5V 6 SCL GND 2 GND 7 SDA 3 8 IF GND 4 TV-VIN 9 5 TV-AUDIO DB9
10
11
12
13 13 +5V
10
11
12
C1 100u/16V
C2 0.1
C4 100u/16V
C3 0.1
SCL SDA SCL SDA
VTT
GND
14
14
+5V
L1 10uH
VTT
TV-AUDIO
AGND
AGND
TV-VIN IF
TV-VIN
Disassembly
In case of trouble, etc., Necessitating disassemble, please disassemble in the order shown in the illustrations. Reassemble in the reverse order. 1. Removal of the Back Cover
2. Removal of the MAIN PCB a. Remove the screws. b . Slide out the LCD chassis slightly; pull up the connector of AC cord from PCB; pull up the LCD PCB from LCD. c . Remove the Anode cap from Thepicture tube. To avaid a shock hazard, be sure to discharge d . Take out the LCD chassis.
MAIN PCB
AUDIO PCB
POWER PCB
TUNER PCB
Bill of Material
TURNER.PCB
1.000 PCB
413210450RZ00
CAP 50V-104-Z CAP-EL4*7 CD110-10V-33uF-M SOCKET DB9 INDOUCTOR EC0410-100K 10uH 500mA WIRE 5mm
2.000 C2,C3
414133R10RM00
2.000 C1,C4
420ET15010920
1.000 CN1
429EC041010R0
1.000 L1
4320006000500
2.000 J4,J5
4320006000750
WIRE 7.5mm
1.000 J3
4320006001000
WIRE 10mm
1.000 J1
4320006001250
WIRE 12.5mm
1.000 J2
442JS6B312110
TUNER JS-6B3121/F2
1.000 TUNER
7506T2601001F 4110PQ323A000
MTV-2601B POWER PART TRANSFORMER PQ32/30-40305A TRANSFORMER KBEC42-40525B CARBON RES 1/8W-100-J CARBON RES 1W-1K-J CARBON RES1/4W-1K
1.000 1.000 T1
411EC42405250
1.000 T2
4121010118J40
1.000 R7
4121010201J40
1.000 R53
4121010214J40
1.000 R49
4121010314J40
CARBON RES1/4W-10K
1.000 R54
4121010514J40
CARBON RES1/4W-1M
1.000 R14
4121010R14J40
CARBON RES1/4W-10
2.000 R23 R33
4121020214J40
CARBON RES 1/4W-2K-J
2.000 R18 R43
4121024114J40
CARBON RES RT14-1/4W-240-J CARBON RES1/4W-5.1K
1.000 R42
4121051214J40
1.000 R39
4121051314J40
CARBON RES1/4W-51K
1.000 R38
4123068305J20
METAL OXIDE RES 5W-68K-J METAL OXIDE RES RY-5W-0.33-J METAL OXIDE RES 5W-0.51R-J HEAT VARIABLE RES 5A 8R DIP PIEZORESISTANCE ZOV-07D471K HEL DIP WIREWOUND RES 5W-0.51-J
2.000 R17 R20
41230R3305J20
1.000 R40
41230R5105J20
1.000 R13
4129008R05A00
1.000 RT1
412A07D471K00
1.000 RV1
412A0R5105J00
1.000 R9
4130103102M03
HIGH VOLTAGE CERAMIC CAPACITOR 1KV-103-M
3.000 C14 C23 C20
4130151102M00
HIGH VOLTAGE CERAMIC CAPACITOR 1000V-151-M X CAP AC275V-104-MK Y CAP221 400V
3.000 C9 C21,
4136104271M02
1.000 C4
4136221401M00
3.000 C1,C3,C26
4136222251M00
Y CAP AC250V-222-MK X CAP AC275V-684-MK METAL MYLAR CAP 400V-105-K CAP- EL DL:18*35(105) CD11G-450V-100u-M CAP-EL 105high frequency LOW IMPEDANCER CD11HL 25V-100uF-M CAP-EL 47uF/10V 6
2.000 C29,C37
4136684271M03
1.000 C54
4138105401K00
1.000 C5
4140101451M00
2.000 C7 C19
414110125RM01
4.000 C11 C17 C18 C28
1.000 C64
414110210RM02
CAP-EL 105high frequency LOW IMPEDANCER
7.000 C41 C44 C46 C51 C53 C56 C57
10V-1000uF-M CAP-EL 105high frequency LOW IMPEDANCER 16V-1000uF-M CAP-EL 105high frequency LOW IMPEDANCER 25V-2200uF-M CAP-EL 105high frequency LOW IMPEDANCER 35V-3300uF-M 16*31 CAP-EL 105 450V-47uF-M CHIP ZENER 1206 15V 0.5W DIODE FR107
414110216RM01
1.000 C48
414122225RM01
8.000 C33 C36 C43 C52 C59 C32 C35 C39
414133235RM00
4.000 C47 C49 C50 C61
414147R451M00
1.000 C16
4151000015070
1.000
415300FR10740
1.000 D13OR 1N4935
415301N400720
DIODED015 1N4007 DIODE UF4007 DIODE MBR20100CT TO-220
1.000 D5
41530UF400740
2.000 D6 D11
4153MBR20100C
1.000 D17
4153MBR20200C
DIODE MBR20200 TO-220
3.000 D10 D10 D18
4153MUR180E00
DIODE MUR180E DO-15 DIODE MUR480E DO-35 DIODE MUR860T TO-220 BRIDGE RECTIFIER (DIP) 800V KBU6JRS606 MOSFET MTP50P03HDL TO-220 TRANSISTOR 2N5401
2.000 D8 D12
4153MUR480E00
1.000 D2
4153MUR860T00
1.000 D3
41540KBU6J000
1.000 D1
416000050P030
3.000 Q3 Q9 Q12
416002N540100
2.000 Q11
Q4
416002N555100
TRANSISTOR 2N5551
2.000 Q13 Q14
41602SK265100
MOSFET 2SK2651
1.000 Q5
416FQP18N5000
MOSFET FQP18N50 TO-220 MOSFET STW12NK80Z TO-3P IC P621[SFH615A-3][PC817]
1.000 Q1
416STW12NK800
1.000 Q2
41700000P6210
3.000 PH1 PH2 PH3
4170000TL4310
IC TL431 DIP TO-92
2.000 U4 U5
41700DF108410
IC(DIP) DF1084-3.3V TO-220 FUSE T3.15A 250V VDE/UL INDUCTOR 500 100MHz INDUCTOR PQ32/30-40117B INDUCTOR EE25-40216 INDUCTOR T37-52-100K3A INDUCTOR
1.000 U6
4222500315210 4290250100040
1.000 FU1 4.000 L3 L5 L6 L7
42903040117B0
1.000 L4
4290304021600
2.000 L1 L2
42903100K5210
2.000 L16 L15
429035R0K5200
1.000 L13
T37-52-5R0K 42903B60974A0 INDUCTOR DQG-B6-0974A INDUCTOR DQG-B6-1042A INDUCTOR DQG-B6-1043A INDUCTOR LCL-T16-0564 magnetic loop RHM-004002003 WIRE 8mm 0.7 1.000 L12
42903B61042A0
1.000 L9
42903B61043A0
3.000 L8 L10 L11
42903T1605640
1.000 L14
42907RHM40203
3.000 D3*2Q1(S)1
4320007000800
2.000 J7 J23
4320007001000
WIRE10mm 0.7
10.000 J4 J5 J8 J10 J11 J13 J14 J17 J18 R31
4320007001500
WIRE15mm 0.7
4.000 J22 J21 J20 J24
4320007001700
WIRE17mm 0.7
1.000 J19
4320007002000
WIRE20mm 0.7
2.000 J12 J9
4320007003000
WIRE30mm 0.7
1.000 J1
437T300100260 405T2701050A0
LEAD WIRE 70mm 26"POWER300.PCB 2004.8.11 CHIP RES 1/4W-0 1206 J
1.000 J2 1.000
412700R014J70
2.000 R57 R58
412700R01AJ60
CHIP RES 1/10W-0 0805
1.000 C27
412701021AJ60
CHIP RES 1/10W-1K 0805 J
5.000 R12 R22 R35 R48 R63
412701031AJ60
6.000 R1,R27 R32 R56 R61 R64
412701041AJ60
CHIP RES 1/10W-100K 0805 J
1.000 R37
4127010514J70
CHIP RES 1206 1/4W-1M-J CHIP RES 0805
1.000 R15
2.000 R3 R24
1/4W-1M-J 4127010R1AJ60 CHIP RES 1/10W-10 0805 J 4.000 R10 R4 R19,R8
4127012314J70
CHIP RES 1206 1/4W-12K-J CHIP RES 1206 1/4W-1K5-J CHIP RES 1/10W-2K 0805 J
1.000 R2
4127015214J70
1.000 R44
412702021AJ60
2.000 R29 R65
412703011AJ60
CHIP RES 1/10W-300 0805 J
1.000 R25
412704721AJ60
CHIP RES 1/10W-4.7K
0805 J
1.000 R28
4127047314J70
CHIP RES 1206 1/4W-47K-J CHIP RES 1/10W-47K 0805 J
1.000 R3
412704731AJ60
2.000 R11 R16
412704731AJ70
CHIP RES 1206 1/4W-47K-J
1.000 R26
412705121AJ60
CHIP RES 1/10W-5.1K 0805 J
4.000 R46,R36,R41 R62
412706221AJ60
CHIP RES 1/10W-6.2K 0805 J
1.000 R34
4127075R1AJ70
CHIP RES 1/8W-75 1206 J
1.000 R21
413510150RJ40
CHIP CAP 50V-100P
0805 J NPO
4.000 C13 B1 A1 25
413510150RJ50
CHIP CAP 1206 50V-100P-J CHIP CAP 0805 50V-102-K CHIP CAP 0805 50V-10nF-K CHIP CAP 50V-104 0805 Z
1.000 C22
413510250RK40
1.000 C8
413510350RK40
1.000 C10
413510450RZ40
10.000 C12 24 31 42 45 55 58 60 62 63
413522450RZ40
CHIP CAP 50V-224 0805 Z
1.000 C6
4151000015070
CHIP ZENER 1206 15V 0.5W
2.000 ZD1 ZD2
415201N414870
CHIP DIODE 1N4148 1206
3.000 D4 D9 D7
41700001377B0
IC NCP1377B SO8 IC MC33260D SO8 IC NCP1203D60R2 SOP 8 TRANSISTOR 2N5551 SOT23 TRANSISTOR 2N5401 SOT23
1.000 U3
4170000332600
1.000 U1
41701203P6010
1.000 U2
2.000 Q16 Q17 1.000 Q18 1.000
7516T2601000M
LCDTV-2627 KEY PCB PART
40300T1701000
KEY 6*6*5mm SOCKET 4PIN/2.0
7.000 P+,P-,V-,V+,MENU,SOURCE,POWER
4041920004010
1.000 CN1
4041920008010
SOCKET 8PIN/2.0
1.000 CN2
TVM2627KEY100.PCB
1.000
2004.10.6 4105010300010 LED 3mm GREEN 1.000 LED
4300000000080 7516T2701002F
IR MTV-2601TUNER SWITCH PCB
1.000 REMOUT 1.000
4041920002010
SOCKET 2PIN/2.0
2.000 CN4,6
4041920003010
SOCKET 3PIN/2.0
3.000 CN1,2,3
4041920005010
SOCKET 5PIN/2.0
1.000 CN5
2627-TURNER300.PCB 2004.10.18 414147116RM00 CAP-EL 8*12 CD110-16V-470uF-M SOCKET DB-9A SOCKET DB9
1.000
1.000 C1
420ET15010910
1.000 DB2
420ET15010920
1.000 DB1
4320005001000
WIRE 10mm MTV-2701mainboard
2.000 J1J2 0.000 3.000 CN5,CN3,CN13 3.000 CN9,CN11,CN2 1.000 CN6 1.000 CN14 1.000 CN12 1.000 CN10 1.000 POWER1 1.000 KBD1
4041920002010 4041920003010 4041920004010 4041920005010 4041920006010 4041920007010 4041920008010 4041920010010
SOCKET 2PIN/2.0 SOCKET 3PIN/2.0 SOCKET 4PIN/2.0 SOCKET 5PIN/2.0 SOCKET 6PIN/2.0 SOCKET 7PIN/2.0 SOCKET 8PIN/2.0 SOCKET 10PIN/2.0
414110116RM00 414110210RM00 414110R16RM00 41412R216RM00
CAP-EL 16V-100uF M 6*7 CAP-EL 10V-1000uF-M CAP-EL 16V-10uF-M CAP-EL
13.000 C168,C217, C220,C225,C226,C231,C246,C250,C10,23,C62, C208,C249 2.000 C197,C227 3.000 C45-C47 1.000 C233
414147116RM00 414147125RM00 414147R16RM00 417000078L050 4202T27012010 4202T30011210 420AD10006110 420DT15011510 424000006101A
16V-2.2uF-M CAP-EL CD110-16V-470uF-M CAP-EL 25V-470uF M8*15 CAP-EL 16V-47uF M5*7 IC 78L05 AV SOCKET AV3-8.4-20 RCA SOCKET AV8-8.4-7 S-SOCKET DSW-06P SOCKET DB-15 OSCILLATOR49S-10---80 10M(+-20PPM,20PF) OSCILLATOR<49S>-10---80 20.25M(+-20PPM,20PF) OSCILLATOR49S-10---80 14.31818M(+-15PPM,20PF) 2627A-pixwork300 PCB MAINBOARD04.12.17 LED-CHIP GREEN 0805 SA0805G1C-1A-01 CHIP RES 1/4W-0 1206 J
5.000 C124,C219,C221,C223,224 1.000 C222 12.000 C165-167,196 C209-C216 1.000 IC9 1.000 RCA1 1.000 RGA 1.000 S-VIDEO 1.000 VGA 1.000 X3
424000256201A 424003186142A 405T2701A5302 4105010300060 412700R014J70
1.000 X1 1.000 X4 1.000 1.000 LED1 1.000 L29
412700R01AJ80 412701011AJ80 412701021AJ80 412701031AF80 412701031AJ80 412701221AJ80 412702011AJ80 412702021AJ80 412702221AJ80 412702231AJ80 412702251AJ80 4127022R1AJ80 412703011AJ80 412703321AJ80
CHIP RES 1/10W-0 0603J CHIP RES 1/10W-100 0603 J CHIP RES 1/10W-1K 0603 J CHIP RES 1/10W-10K 0603 F
22.000 R14,R40,R28,R81,R82,R142,R143,R178,187,R233,R245-250, R41,R66,C254-C256,R97 1.000 R59 5.000 R2,R134,R188,R190,R226 2.000 R232,R73 19.000 R29-30,R118,119 R159-169,179 183,191 R228 1.000 R71 3.000 R116,R117,R153 7.000 R44-R48,R170,R49 2.000 R36,R37 1.000 R63 2.000 R93,R130 2.000 R34,R35 4.000 R92,R128,R129,R174 26.000 R90,R91,R104-R111,R135-R137,R144-R148,R171-R173,R227 ,R234,238,R253,R255
CHIP RES 1/10W-10K 0603 J CHIP RES 1/10W-1.2K 0603 J CHIP RES 1/10W-200 0603 J CHIP RES 1/10W-2K 0603 J CHIP RES 1/10W-2.2K 0603 J CHIP RES 1/10W-22K 0603 J CHIP RES 0603 1/10W-2.2M-J CHIP RES 1/10W-22 0603 J CHIP RES 1/10W-300 0603 J CHIP RES 1/10W-3.3K 0603 J
412704711AJ80 4127047R1AJ80 412705121AJ80 412705621AJ80 412706811AJ80 412706821AJ80 4127075R1AJ80 413510250RK60 413510450RZ60
CHIP RES 1/10W-470 0603 J CHIP RES 1/10W-47 0603 J CHIP RES 1/10W-5.1K 0603 J CHIP RES 1/10W-5.6K 0603 J CHIP RES 1/10W-680 0603 J CHIP RES 1/10W-6.8K 0603 J CHIP RES 1/10W-75 0603 J CHIP CAP 0603 50V-102-K CHIP CAP 50V-104 0603 Z
11.000 R132,R133,R60,R61,R67-R69,R192-R194,L43 14.000 R13,R87,R88,R89,R112-R115,R138,R141,R64,R101,R102, R103 1.000 R252 1.000 R62 3.000 R38,R39,R175 3.000 R131,R75,R254 18.000 R50-R57,R58,R94-R96,R98-R100,R184,R74,R76 5.000 C31-C34,C137 110.000 C2,C4-6,C9,C11-19,C48-53,C81-97,C99-110,C114-123, C138-142,155-156 C169-C179,C181-185,C188-C190, C126-129,C131,C63,C65,C67,C258 C192-C195,C198-C207,C232,C234 5.000 C111,C143,C144,C180,C228 9.000 C58-59,C112,113,186,187,146,147,148 8.000 C36-C40,C72,C73,C74 2.000 C25,C26 4.000 C55-C57,C75
413510R50RJ60 413520R50RJ60 413522416RZ60 413522R50RJ60 413533150RK60
CHIP CAP 50V-10P 0603 J NPO CHIP CAP 50V-20P 0603 J NPO CHIP CAP 16V-0.22u 0603 Z CHIP CAP 50V-22P 0603 J NPO CHIP CAP 50V-330P 0603 K
413533R50RJ60 413539250RK60 413539350RZ60 413547350RZ60 413568250RK60 413568350RZ60 413568410RZ60 415200BAV9960 415201N414870 4160000901421 4160000901520 416PCHAN20P03 417000024C320 4170000AC3200
CHIP CAP 50V-33P J 0603 NPO CHIP CAP 50V-392 0603 K CHIP CAP 0603 50V-39nF-Z CHIP CAP 0603 50V-47n-Z CHIP CAP 0603 50V-6.8nF-K CHIP CAP 50V-0.068 0603 Z CHIP CAP 0603 10V-0.68uF-Z DIODE (SOT-23B) BAV99 IODE 1N4148 1206 CHIP TRANSISTOR(SOT23) 9014 NPN CHIP TRANSISTOR 9015 MOSFET P-CHANNEL T0-252 MTD20P03HDLT4 OR 25P03 IC(SO8) 24C32 IC(SO14) AC32
3.000 C69,C70,C71 1.000 C132 1.000 C136 6.000 C42-C44,C133-C135 1.000 C77 1.000 C78 4.000 C27-C30 7.000 D1-D7 6.000 D11-13,17,18,D15 6.000 Q3-7,Q10 1.000 Q16 1.000 Q8 1.000 U5 1.000 UD
4170000LM3580 41700074HC140 417000HC37400 4170074LV1260 41700AMS11170 41700APL11170 41700Z8622910 41704M000161A 4170LV800DT10 4170LVC162440 4170MAX232A00 4170MST988310 41763LVDM8310 417AZ1084S3V3 417FSAV330M10 417PW11320Q10
IC(S0-8) LM358 IC 74HC14[SOP] IC(SSOP20 HC374 IC(SO14) SN74LV126 IC AMS1117[SOP]3.3V IC APL1117ADJ[SOT-223] IC Z86229 SO18 IC(TSOP54) HY57V641620HG 4M*16 SDRAM 7ns IC(TSOP48) AM29LV800DT-90EC ICTSSOP48 LVC16244 ICS016 MAX232A IC(LQFP80) MST9883B-C(/110) IC THC63LVDM83A THINE IC(TO-263) AZ1084S-3.3V IC(SO16) P15V330/FSAV330M IC PW113-20Q [PQFP208]
1.000 UE 1.000 U3 1.000 U2 2.000 UB UA 2.000 IC7,IC8 2.000 IC2,IC5 1.000 U7 1.000 U9 1.000 U18 2.000 U14U15 1.000 U12 1.000 U11 1.000 U19 1.000 IC4 1.000 U10 1.000 U17
417PW12350010 417S0HCF40520 417VPC3230D10 420FT15013010 42847R0082010 429025R6K0010 429042R2J7010 429043R3J5010 429043R3J8011 4290511R08010 4290512108010 4290550108010 7596T2701003F 4041920002010
IC PW1235 [PQFP256] IC HCF4052 SOP IC VPC3230D PQFP80 SOCKET SOP DF14-30S-1.25C CHIP RES 0603 47*4 CHIP INDUCTOR 1210 DR43-5R6K CHIP INDUCTOR 1210 ALM322522-2R2K CHIP INDUCTOR 1206 3.3uH-J CHIP INDUCTOR 0603 3.3uH-J CHIP INDUCTOR 0603 11 OHM@100MHz CHIP INDUCTOR 0603 BK1608HM121-T CHIP INDUCTOR 500 0603 2601B SOUND PCB SOCKET 2PIN/2.0
1.000 UC 1.000 U21 1.000 U4 1.000 CON1 20.000 RP7-RP20 RP33-38 5.000 L8 24 27 30 36 10.000 21-23 26 31 33-35 37,L41 1.000 L42 5.000 L9-L11,L39,L38 7.000 L12-17,44 1.000 R11 1.000 R86 1.000 5.000 CN3,CN6-CN9
4041920003010
SOCKET 3PIN/2.0
1.000 CN2
4041920004010
SOCKET 4PIN/2.0
1.000 CN5
4041920005010
SOCKET 5PIN/2.0
1.000 CN1
4041920006010
SOCKET 6PIN/2.0
1.000 CN10
4121010214J40
CARBON RES 1/4W-1K
4.000 R35-R38
414022125RM00 41404R716RM00
CAP-EL 25V-220uF M CAP-EL 16V-4.7uF M
1.000 C42 1.000 C47
414110116RM00
CAP-EL 16V-100uF M 6*7
5.000 C49 C55 C59 C60 C61
414110R16RM00
CAP-EL 16V-10uF-M CAP-EL 5*11 CD110-16V-22uF-M
6.000 C16-21
414122R16RM00
1.000 C48
414147125RM00
CAP-EL 25V-470uF M8*15
7.000 C1,C41,C43,C56,57,58,C51
415201N414840
DIODE 1N4148
1.000 D1
417TDA8947J10
IC TDA8947J
SOT243-1
1.000 U2
4202T30011310
RCA SOCKET AV6-8.4-20 EAR SOCKET EJ-0357-3P OSCILLATOR49S -10---80 18.432MHz 15PPM15P 2627SOUND300.PCB
1.000 RCA
4204T15010310
1.000 PHO
424004326183A
1.000 X1
405T2701059B0
1.000
412700R01AJ80
CHIP RES 1/10W-0 0603J
1.000 R26
412701021AJ80
5.000 R1,R2,R24,R27,R33
412701031AJ80
6.000 R3,R7,R8,R25,R29,R34
412702021AJ80
1.000 R30
412702211AJ80
CHIP RES 1/10W-220 0603 J
1.000 R12
412702231AJ80
1.000 R4
412703021AJ80
3.000 R6,R9,R13
412704731AJ80
4.000 R18-R21
4127047R1AJ80
CHIP RES 1/10W-47 0603 J
1.000 R14
412705121AJ80
CHIP RES 1/10W-5.1K 0603 J
2.000 R31 R32
412705611AJ80
CHIP RES 1/10W-560 0603 J
1.000 R10
412705621AJ80
CHIP RES 1/10W-5.6K 0603 J
1.000 R28
413510150RJ60
CHIP CAP 50V-100P 0603 J NPO
1.000 C2
413510250RK60
CHIP CAP 0603 50V-102-K CHIP CAP 25V-104 0603 Z
2.000 C26,C27
413510425RZ60
11.000 C3,C28-C36,C40
413515250RK60
CHIP CAP 50V-1500P 0603 K
3.000 C52-C54
413520R50RJ60
2.000 C22,C23
413533416RZ60
CHIP CAP 0603 16V-0.33uF-Z CHIP CAP 50V-470P 0603 K
9.000 C4-C12
413547150RK60
3.000 C37-C39
413556R50RJ60
3.000 C13-C15
4160000901421
CHIP CAP (SOT23) 9014 NPN CHIP TRANSISTOR 9015
6.000 Q3,Q5,Q6,Q1,Q7,Q8
4160000901520
1.000 Q4
41700APL11170
IC APL1117ADJ[SOT-223]
1.000 IC1
417MSP3450G10
IC MSP3450G-QA-C12-001 [PQFP80] CHIP INDUCTOR 1210 DR43-5R6K CHIP INDUCTOR 1210 ALM322522-2R2K
1.000 U1
429025R6K0010
1.000 L2
429042R2J7010
2.000 L3,L4
IC SPECIFICATION
-PW113 (Top View) -PW1235 -MST9883B -Z86229 -THC63LVDM83R -MSP34XOG -TDA8947J -VPC323XD
Pinout Information
Pin Descriptions
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
D7 D8 D9 D10 D11 D12 D13 D14 D15 TRST_N TCK TMS TDI TDO TESTEN VSSQ VDDQ3 RESET_N VSS VDD1 DGR0 DGR1 DGR2 DGR3 DGR4 DGR5 DGR6 DGR7 DGG0 DGG1 DGG2 DGG3 VSSQ VDDQ3 DGG4 DGG5 DGG6 DGG7 DGB0 DGB1 DGB2 DGB3 DGB4 DGB5 DGB6 DGB7 DE N DHS DVS DCLKNEG DCLK VSSQ
D6 D5 D4 D3 D2 D1 D0 A19 VDDPA2 VSSPA2 VDDPA1 VSSPA1 XI XO VDDQ3 VSSQ A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 VDD1 VSS A6 A5 A4 A3 A2 A1 NMI WR R D ROMOE ROMWE CS0 CS1 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 VDDQ3
PW113
(Top View)
VDDQ3 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 VSSQ VDDQ3 VSS VDD1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VHS VVS VSSQ VDDQ3 VCLK VPEN VFIELD TXD RXD VSS VDD1 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 VYUV7 VYUV6 VYUV5 VSSQ
VSSQ GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 VDD1 VSS GGE6 GGE7 GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 EXTRSTEN VDDQ3 VSSQ GCLK GVS GHSSOG GPEN GFBK GCOAST VDD1 VSS PORTC0 PORTC1 PORTC2 PORTC3 PORTC4 PORTC5 PORTC6 PORTC7 VYUV0 VYUV1 VYUV2 VYUV3 VYUV4 VDDQ3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Figure 2-1 Pin Locations
Pin Descriptions
Pinout Information
2.3
Pin Descriptions
Table 2-1 provides detailed Video Port pin descriptions.
Table 2-1 Video Port Pin Descriptions

Name VCLK Pin(s) 71 Type ID 5 Function VPort Pixel Clock. The VCLK pin is used for video port image capture. The polarity can be selected by the VCLKPOL bit. VPort Vertical Sync. Indicates start of next field or frame of input data. This signal is internally polarity corrected so VVS can be either active-high or active-low. The current status of the VVS signal is given by VPOL and VSOK status bits when the video port is selected by the PORTSEL bit. VVS is not used when a composite digital sync source is used (COMPEN). VVS is required in ITUR656 input mode. VPort Horizontal Sync. Indicates start of next line of data input. This signal is internally polarity corrected and monitored for composite sync content. The current status of the GHS signal is given by the HPOL, HSOK & COMP status bits when the video port is selected by the PORTSEL bit. VHS can supply horizontal sync information or digital composite sync information depending on the COMPEN bit. VHS is required in ITUR656 input mode. VPort Pixel Enable. Used when external flow control capture mode is enabled by the EXTFCE bit. When VPEN is active, the input data is valid. The polarity can be selected by the PENPOL bit. Use of this pin allows non-contiguous input data. VGPort Field Input. Video or Graphics port odd/even field indicator specifies whether odd or even field of interlaced input is being captured.This pin is enabled by the FLDSEL bit and the polarity can be specified by the FLDINV bit. Field information can also be derived from VVS and VHS, so VFIELD is not required in some applications.
VVS
74
ID 5
VHS
75
ID 5
VPEN
70
ID 5
VFIELD
69
ID 5
Pinout Information
Table 2-2 provides detailed Graphics Port pin descriptions.
Pin Descriptions
Table 2-2 Graphics Port Pin Descriptions

Name GCLK Pin(s) 31 Type ID 5 Function GPort Pixel Clock. The GCLK pin is used for graphics port image capture. The polarity can be selected by the GCKPOL bit.The GCLK input can be disabled by the GCLKOFF bit to reduce power consumption. GPort Vertical Sync. Indicates start of next field or frame of data. This signal is internally polarity corrected so GVS can be either active-high or active-low. The current status of the GVS signal is given by VPOL and VSOK status bits when the graphics port is selected by the PORTSEL bit. GVS is not used when a composite digital sync source is used which can be specified by the SOGSEL and COMPEN bits. GPort Pixel Enable. Used when external flow control capture mode is enabled by the EXTFCE bit. When GPEN is active, the input data is valid. The polarity can be selected by the GPENPOL bit. Use of this pin allows non-contiguous input data. GPort Horizontal Sync/GPort Sync-on-Green. This pin has two different functions depending on the SOGSEL bit:
SOGSEL GHSSOG Function GHS: GPort Horizontal Sync. Indicates the start of the next line of input data. This signal is internally polarity corrected and monitored for composite sync content. The current status of the GHS signal is given by the HPOL, HSOK & COMP status bits when the graphics port is selected by the PORTSEL bit. GHS can supply horizontal sync information or digital composite sync information depending on the COMPEN and SOGSEL bits. SOG: Pin is sync-on-green. Driven by an external sync stripper circuit, this pin is monitored (SOGACT status bit) and can supply composite sync information (depending on SOGSEL & COMPEN bits).
GVS
32
ID 5
GPEN
34
ID 5
GHSSOG
33
ID 5
GCOAST
36
OS
GPort PLL Coast. Tells the PLL when to coast (ignore GREF) during vertical blanking. Used to prevent the PLL from reacting to extra or missing HS pulses during vertical blanking. Coast duration and polarity is programmable through the PLLCM, PLLCB & PLLCE bits. GPort PLL Feedback / Line Advance Input. When PORTSEL=0, this pin is not used. When PORTSEL=1, this pin has two different functions depending on the EXTFCE bit:
EXTFCE GFBK Function GFBK: An input that is typically driven by the FBK output of an ADC/ PLL device. In free running capture mode this signal is used to define the horizontal capture region (along with the CAPL and CAPW registers), and advances the GPort capture controller to the next input line. The LAVPOL bit is used to select the polarity of GFBK. GLAV: An input to the graphics port line advance. Used in external flow control capture mode. When GLAV transitions (depending on LAVPOL and LAVMOD bits), the GPort capture controller advances to the next input line.
GFBK
35
ID 5
Pin Descriptions Table 2-2 Graphics Port Pin Descriptions (continued)

Name GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 Pin(s) 20 21 22 23 24 25 26 27 10 11 12 13 14 15 18 19 2 3 4 5 6 7 8 9 Type ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 ID 5 Function
Pinout Information
GPort Red Pixel Data. GPort Red Even Pixel Data when in 48-bit input mode.
GPort Green Pixel Data. GPort Green Even Pixel Data when in 48-bit input mode.
GPort Blue Pixel Data. GPort Blue Even Pixel Data when in 48-bit input mode.
Table 2-3 provides detailed Display/Graphics Port pin descriptions.
Table 2-3 Display/Graphics Port Pin Descriptions

Name DGR0 DGR1 DGR2 DGR3 DGR4 DGR5 DGR6 DGR7 Pin(s) 136 135 134 133 132 131 130 129 Type I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 DGPort Red Pixel Data. In dual pixel output mode these pins are the ODD red outputs. In single pixel output mode these pins are not used. Function
Pinout Information Table 2-3 Display/Graphics Port Pin Descriptions (continued)

Name DGG0 DGG1 DGG2 DGG3 DGG4 DGG5 DGG6 DGG7 DGB0 DGB1 DGB2 DGB3 DGB4 DGB5 DGB6 DGB7 Pin(s) 128 127 126 125 122 121 120 119 118 117 116 115 114 113 112 111 Type I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 I/O SR5 Function
Pin Descriptions
DGPort Green Pixel Data. In dual pixel output mode these pins are the ODD green outputs. In single pixel output mode these pins are not used.
DGPort Blue Pixel Data. In dual pixel output mode these pins are the ODD blue outputs. In single pixel output mode these pins are not used.
Table 2-4 provides detailed Display Port pin descriptions.
Table 2-4 Display Port Pin Descriptions

Name Pin(s) Type Function DPort Pixel Clock. Output clock for the display port pixel data. DCLK is enabled by the DCLKEN bit and can be inverted by the DCPOL bit. DCLK can be set to run at pixel rate, for dual pixel output mode, by setting the DCK2EN bit. The DCLK output can be disabled by the DCLKOFF bit to reduce power consumption. DPort Pixel Clock. DPort Vertical Sync. DVS can be either active-high or active-low depending on the VSPOL bit. Width and timing is controlled by the VPLSE and VDLY registers. DPort Vertical Sync. DHS can be either active-high or active-low depending on the HSPOL bit. Sync width can be controlled by the HPLSE register.
DCLK
106
OSR
DCLKNEG DVS
107 108
OSR OS
DHS
109
OS
Pin Descriptions Table 2-4 Display Port Pin Descriptions (continued)

Name DEN DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Pin(s) 110 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 83 82 81 80 79 78 77 76 Type OS OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR OSR Function
Pinout Information
DPort Pixel Enable. This signal is active whenever valid data is present. The polarity is specified by the DENPOL bit.
DPort Red Pixel Data. In dual pixel output mode these pins are the EVEN red outputs.
DPort Green Pixel Data. In dual pixel output mode these pins are the EVEN green outputs. These pins can also be used in conjunction with the PORTB pins for higher color depth.
DPort Blue Pixel Data. In dual pixel output mode these pins are the EVEN blue outputs.
Pinout Information
Table 2-5 provides detailed Microprocessor Interface pin descriptions.
Pin Descriptions
Table 2-5 Microprocessor Interface Pin Descriptions

Name WR RD ROMOE ROMWE CS0 Pin(s) 194 195 196 197 198 Type I/O D5 I/O D5 OS OS I/O D5 Function Write Enable. Low indicates a write to external RAM or other devices. Read Enable. Low indicates a read to external RAM or other devices. ROM Output Enable. Low output indicates a read from external ROM. ROM Write Enable. Low indicates a write to external ROM. Miscellaneous Chip Select 0. Low selects external devices. Miscellaneous Chip Select 1. When EXTRAMEN=0, low selects external devices. Chip select for external RAM. When EXTRAMEN=1, low selects external RAM. (RAMCS) Non-Maskable Interrupt. A high input triggers a non-maskable interrupt to the on-chip microprocessor.
CS1
199
I/O D5
NMI A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
193 192 191 190 189 188 187 184 183 182 181 180 179 178 177 176 175 174 173 164
ID 5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5
Microprocessor address bus output bits (19:1).
Pin Descriptions Table 2-5 Microprocessor Interface Pin Descriptions (continued)

Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pin(s) 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 Type I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 Microprocessor 16-bit bidirectional data bus. Function
Pinout Information
Table 2-6 provides detailed Peripheral Interface pin descriptions.
Table 2-6 Peripheral Interface Pin Descriptions

Name Pin(s) Type Function General-purpose I/O port bit controlled by PADAT0 and PAEN0. This pin has one other possible function when EXTRAMEN=1. When EXTRAMEN=1 and PAEN0=0, PORTA1 is microprocessor address bit 0 (A0). General-purpose I/O port bit controlled by PADAT1 and PAEN1. This pin has one other possible function when EXTRAMEN=1. When EXTRAMEN=1 and PAEN1=0, PORTA1 is microprocessor bytehigh enable (BHEN) General-purpose I/O port bit controlled by PADAT2 and PAEN2. This pin has one other possible function when GREFEN=1. PORTA2 205 I/O U5 When GREFEN=1 and PAEN2=0, PORTA2 is GPort PLL reference out, a delayed version of internal horizontal sync (typically connected to the external PLLs reference input) (GREF) General-purpose I/O port bit controlled by PADAT3 and PAEN3. This pin can also function as an external clock source for DCLK (DCLKEXT) when the internal PLLs are disabled. General-purpose I/O port bit controlled by PADAT4 and PAEN4. This pin has one other possible function when IREN=1. When IREN=1 and PAEN4=1, this pin can function as an input to the onchip IR receiver 0. (IRRCVR0)
PORTA0
207
I/O U5
PORTA1
206
I/O U5
PORTA3
204
I/O U5
PORTA4
203
I/O U5
Pinout Information Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name Pin(s) Type Function
Pin Descriptions
PORTA5
202
I/O U5
General-purpose I/O port bit controlled by PADAT5 and PAEN5. This pin has other possible functions depending on the IREN, EIEN registers. When EIEN=1 and PAEN5=1, this pin can function as an external interrupt to the on-chip CPU. When IREN=1 and PAEN5=1, this pin can function as an input to the onchip IR receiver 1. (IRRCVR1). . General-purpose I/O port bit controlled by PADAT6 and PAEN6. This pin can also function as BLKSPL when BLKSMPLEN=1. When BLKSMPLEN=1 and PAEN6=0, PORTA6 is GPORT black sample clamp pulse output (typically used as port of an external DC restoration circuit) (BLKSPL) This pin has one other possible function when PREF1EN=1. When PREF1EN=1 and PAEN6=0, PORTA6 is a variable duty-cycle pulse reference generator (PWM) output controlled by PREF1HI and PREF1LO. General-purpose I/O port bit controlled by PADAT7 and PAEN7. This pin has one other possible function when PREF0EN=1. When PREF0EN=1 and PAEN7=0, PORTA7 is a variable duty-cycle pulse reference generator (PWM) output controlled by PREF0HI and PREF0LO. General purpose I/O port bit controlled by PBDAT0 and PBEN0. PORTB0 can also function as GRO0 when in 48 bit graphics input mode; VR0 when in 24 bit RGB video input mode; Y0 when in 24 bit YUV video input mode. General purpose I/O port bit controlled by PBDAT1 and PBEN1. PORTB1 can also function as GRO1 when in 48 bit graphics input mode; VR1 when in 24 bit RGB video input mode; Y1 when in 24 bit YUV video input mode. General purpose I/O port bit controlled by PBDAT2 and PBEN2. PORTB2 can also function as:
Function DB1E DB0 GRO2 VR2 Y2 Cb0 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTA6
201
I/O U5
PORTA7
200
I/O D5
PORTB0
57
I/O D5
PORTB1
58
I/O D5
PORTB2
59
I/O D5
General purpose I/O port bit controlled by PBDAT3 and PBEN3. PORTB3 can also function as:
Function DB1O DB1 GRO3 VR3 Y3 Cb1 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTB3
60
I/O D5
Pin Descriptions Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name Pin(s) Type Function
Pinout Information
Function DG1E DG0 GRO4 VR4 Y4 Y0 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTB4
61
I/O D5
Function DG10 DG1 GRO5 VR5 Y5 Y1 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTB5
62
I/O D5
Function DR1E DR0 GRO6 VR6 Y6 Cr0 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTB6
63
I/O D5
Function DR1O DR1 GRO7 VR7 Y7 Cr1 When in Dual-pixel 27-bit output mode 30-bit output mode 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 30-bit YCbCr input mode (CSCD30BIT).
PORTB7
64
I/O D5
Pinout Information Table 2-6 Peripheral Interface Pin Descriptions (continued)

Name PORTC0 PORTC1 PORTC2 PORTC3 PORTC4 PORTC5 PORTC6 PORTC7 RXD Pin(s) 39 40 41 42 43 44 45 46 67 Type I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O D5 I/O U5 Function
Pin Descriptions
General purpose I/O port controlled by PCDAT(7:0) and PCEN(7:0). PORTC(7:0) can also function as:
Function GBO(7:0) VB(7:0) U(7:0) UV(7:0) When 48-bit graphics input mode 24-bit RGB video input mode 24-bit YUV video input mode 16-bit YUV video input mode
Serial Receive Data. RXD is the serial receive data for the on-chip serial port. This pin can also function as the 2-wire master data pin when 2WMEN=16. Serial Transmit Data. TXD is the serial transmit data for the on-chip serial port. This pin can also function as the 2-wire master clock output pin when 2WMEN=16.
TXD
68
I/O U5
Table 2-7 provides detailed Miscellaneous pin descriptions.
Table 2-7 Miscellaneous Pin Descriptions

Name TESTEN Pin(s) 142 Type ID 5 Function Test Mode Enable. Connect to ground for normal operation. Bidirectional reset pin. This pin requires a pull-up resistor to V33 (VDDQ3). The typical value is 3.3K ohm. When EXTRSTEN=1, RESET_N is an input. When EXTRSTEN=0, RESET_N is an output. In either case a low indicates reset. External Reset Enable. When EXTRSTEN=1, the internal reset is disabled and an external reset must be supplied on the RESET_N pin. When EXTRSTEN=0, the internal reset is enabled and RESET_N becomes a bidirectional pin that can be used to either drive external logic in the system or receive an external reset signal. Crystal Input. Connect to external crystal. XI can also function as the MCLK input LVTTL-level signal from an external oscillator. Crystal Output. Connect to external crystal.
RESET_N
139
BOD
EXTRSTEN
28
ID 5
XI XO
169 170
I O
Table 2-8 provides detailed Microprocessor Debug Port pin descriptions.
Table 2-8 Microprocessor Debug Port Pin Descriptions

Name TRST_N TCK TMS TDI TDO Pin(s) 147 146 145 144 143 Type ID 5 ID 5 ID 5 ID 5 I/O D5 Function Debug port reset (low true). Leave floating if debug port is not being used. Debug port serial data clock. Leave floating if debug port is not being used. Debug port mode select. Leave floating or pull to ground to disable. Debug port serial data in. Leave floating if debug port is not being used. Debug port serial data out. Leave floating if debug port is not being used.
Pin Descriptions
Table 2-9 provides detailed Power and Ground pin descriptions.
Pinout Information
Table 2-9 Power and Ground Pin Descriptions

Name VDD1 VSS VDDQ3 Pin(s) 16,37,65,84, 137,185 17,38,66,85, 138,186 29,52,72,86, 104,123,140, 171,208 1, 30, 53, 73, 87, 105, 124, 141, 172, 167 165 168 166 Type P P P 1.8V digital core power. Digital core ground. 3.3V digital I/O power. Function
VSSQ VDDPA1 VDDPA2 VSSPA1 VSSPA2
P P P P P
Digital I/O ground. 1.8V analog clock generator power. 1.8V analog clock generator power. Clock generator analog ground. Clock generator analog ground.
Pinout Information
Pin Descriptions
VB0 VB1 VB2 VB3 VDD VB4 VB5 VB6 VB7 PVSS SVHS SVVS SVCLK PVDD VG0 VG1 VG2 VG3 VSS VG4 VG5 VG6 VG7 PVSS PVCLK CREF PVVS PVHS PVDD VR0 VR1 VR2 VR3 VDD VR4 VR5 VR6 VR7 PVSS XTALI XTALO PVDD 2WA1 2WA2 2WCLK PVSS 2WDAT TDO VSS TCK TDI TMS TRSTN PVDD RESETn TEST PVSS MPDVDD MPDVSS MPAVDD MPAVSS NC NC PVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PVSS 193 NC 194 NC 195 DPAVSS 196 DPAVDD 197 DPDVSS 198 DPDVDD 199 PVDD 200 NC 201 PVSS 202 MA4 203 MA3 204 VDD 205 MA5 206 MA2 207 PVDD 208 MA6 209 MA1 210 MA7 211 PVSS 212 MA0 213 MA8 214 MA10 215 PVDD 216 MA9 217 MA13 218 VSS 219 MA11 220 MA12 221 PVSS 222 MCLKFB 223 PVDD 224 MRAS 225 MCAS 226 MWE 227 PVSS 228 MCLK 229 PVDD 230 MD8 231 MD7 232 PVSS 233 MD9 234 VDD 235 MD6 236 PVDD 237 MD10 238 MD5 239 PVSS 240 MD11 241 MD4 242 PVDD 243 MD12 244 MD3 245 PVSS 246 MD13 247 MD2 248 PVDD 249 MD14 250 VSS 251 MD1 252 PVSS 253 MD15 254 MD0 255 PVDD 256
192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
MCUCMD MCUWR MCUCS PVSS MCURDY VSS MCUD7 MCUD6 MCUD5 MCUD4 MCUD3 MCUD2 PVDD MCUD1 MCUD0 MCUA7 MCUA6 VDD MCUA5 MCUA4 MCUA3 PVSS MCUA2 MCUA1 MCUA0 ADGVSS ADGVDD PVDD ADAVSS ADAVDD VREFOUT VREFIN COMP RSET AVS33R AVD33R ADR AVS33G AVD33G ADG AVS33B AVD33B ADB ADDVDD ADDVSS PVSS CGMS DEN TESTCLK PVDD DR7 DR6 VDD DR5 DR4 PVSS DR3 DR2 VSS DR1 DR0 PVDD DG7 DG6
PW1235
DG5 DG4 PVSS DG3 DG2 VDD DG1 DG0 PVDD DB7 DB6 DB5 DB4 PVSS DB3 DB2 VSS DB1 DB0 PVDD DENR DENB DENG PVSS DHS DVS DCLK PVDD DGR7 DGR6 DGR5 DGR4 PVSS DGR3 DGR2 VDD DGR1 DGR0 PVDD DGG7 DGG6 DGG5 DGG4 PVSS DGG3 DGG2 DGG1 DGG0 PVDD DGB7 DGB6 VSS DGB5 DGB4 PVSS DGB3 DGB2 DGB1 DGB0 PVDD DGCLK DGVS DGHS PVSS
Figure 2-1 Pin Layout
Pin Descriptions
Pinout Information
2.2.1
Video Port Pins
Table 2-1 provides detailed pin descriptions for the Video Port.
Table 2-1 Video Port Pin Descriptions

Name PVHS Pin(s) 28 Type I Function Primary Video (PV) Port horizontal sync input. Indicates start of next line of input data. This signal is internally polarity corrected (PVHS_POL) so PVHS can be either activehigh or active-low. [Input, pull-down, 5V-tolerant] Primary Video (PV) Port vertical sync input. Indicates start of next field or frame of input data. This signal is internally polarity corrected (PVVS_POL) so PVVS can be either active-high or active-low. [Input, pull-down, 5V-tolerant] Video input clock reference. [Input, pull-down, 5V-tolerant] cref_mode = 1
PVVS
27
P VCLK
CREF
VR, VG, VB
N-1
sampling points
CREF
26
cref_mode = 0
PVCLK
CRE F
VR, VG, VB
N-1
sampling points
PVCLK SVVS
25 12
I I
SVHS SVCLK
11 13
I I
Primary Video (PV) Port pixel clock input. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) vertical sync input. Indicates start of next field or frame of input data. This signal is internally polarity corrected (svvs_pol) so SVVS can be either active-high or active-low. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) horizontal sync input. This signal is internally polarity corrected (svhs_pol) so SVHS can be either active-high or activelow. [Input, pull-down, 5V-tolerant] Secondary Video (SV) Port (ITU-R BT656 format) pixel clock input. [Input, pull-down, 5V-tolerant]
Pinout Information Table 2-1 Video Port Pin Descriptions (continued)

Name VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 VG0 VG1 VG2 VG3 VG4 VG5 VG6 Pin(s) 30 31 32 33 35 36 37 38 15 16 17 18 20 21 22 Type I I I I I I I I I I I I I I I
10 10
Pin Descriptions
Function Video port red data input. These pins have different functions depending on the settings of the PVmode register. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 Reserved. Primary Video (PV) Port. UV[7:4]: ITU-R BT601 YUV 4:1:1 UV pixel data. Primary Video (PV) Port UV[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data. Primary Video (PV) Port. R[7:0]: red pixel data or V[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VR[7:0] Pin Function
11
Video port green data input. These pins have different functions depending on the settings of the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 Reserved. Primary Video (PV) Port. Y[7:0]: ITU-R BT601 YUV 4:1:1 UV pixel data. Primary Video (PV) Port. Y[7:0]: ITU-R BT601 YUV 4:2:2 UV pixel data. Primary Video (PV) Port. G[7:0]: green pixel data or Y[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VG[7:0] Pin Function
VG7
23
11
VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7
1 2 3 4 6 7 8 9
I I I I I I I I
Video port blue data input. These pins have different functions depending on the settings for the Primary Video (PV) Port mode registers. [Input, pull-down, 5V-tolerant]
PV_mode 00 01 10 11 Reserved. Secondary Video (SV) Port YUV[7:0]: ITU-R BT656 format pixel data. Primary Video (PV) Port. B[7:0]: blue pixel data or U[7:0]: ITU-R BT601 YUV 4:4:4 pixel data. VB[7:0] Pin Function
2.2.2
Digital/Graphics (DG) Port Pins
Table 2-2 provides detailed pin descriptions for the Digital/Graphics (DG) Port.
Table 2-2 Digital/Graphics (DG) Port Pin Descriptions

Name DGS DGHS DGCLK Pin(s) 67 66 68 Type I I I Function Digital/Graphics (DG) port vertical sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital/Graphics (DG) port horizontal sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital/Graphics (DG) port pixel clock. [Tri-state output, 8mA drive, 5V-tolerant]
Pin Descriptions Table 2-2 Digital/Graphics (DG) Port Pin Descriptions (continued)
Name DGR0 DGR1 DGR2 DGR3 DGR4 DGR5 DGR6 DGR7 DGG0 DGG1 DGG2 DGG3 DGG4 DGG5 DGG6 DGG7 DGB0 DGB1 DGB2 DGB3 DGB4 DGB5 DGB6 DGB7 Pin(s) 91 92 94 95 97 98 99 100 81 82 83 84 86 87 88 89 70 71 72 73 75 76 78 79 Type I I I I I I I I I I I I I I I I I I I I I I I I Function
Pinout Information
Digital/Graphics (DG) port red data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGR[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). R[7:0]: red pixel data or V[7:0]: YUV 4:4:4 pixel data.
Digital/Graphics (DG) port green data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGG[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). G[7:0]: green pixel data or Y[7:0]: YUV 4:4:4 pixel data.
Digital/Graphics (DG) port blue data. [Bi-directional, input with pull-down, tri-state 4mA drive output, 5V-tolerant]
DGB[7:0] Pin Function Digital/Graphics (DG) Port input (single pixel mode). B[7:0]: blue pixel data or U[7:0]: YUV 4:4:4 pixel data.
2.2.3
System Power Pins
Table 2-3 provides detailed pin descriptions for System Power.
Table 2-3 System Power Pin Descriptions

Name VDD Pin(s) 5, 34, 93, 123, 140, 175, 205, 235 19, 49, 77, 112, 134, 187, 219, 251 Type P Digital core power (2.5V). Function
VSS
Digital core ground.
Pinout Information Table 2-3 System Power Pin Descriptions (continued)

Name Pin(s) 14, 29, 42, 54, 64, 69, 80, 90, 101, 109, 120, 131, 143, 165, 180, 200, 208, 216, 224, 230, 237, 243, 249, 256 10, 24, 39, 46, 57, 65, 74, 85, 96, 105, 115, 126, 137, 147, 171, 189, 193, 202, 212, 222, 228, 233, 240, 246, 253 60 61 58 59 197 196 199 198 157 154 151 158 155 152 163 164 149 148 166 167 Type Function
Pin Descriptions
PVDD
Digital I/O power (3.3V).
PVSS
Ground.
MPAVDD MPAVSS MPDVDD MPDVSS DPAVDD DPAVSS DPDVDD DPDVSS AVD33R AVD33G AVD33B AVS33R AVS33G AVS33B ADAVDD ADAVSS ADDVDD ADDVSS ADGVDD ADGVSS
P G P G P G P G P P P G G G P G P G P G
Memory PLL analog power 2.5V. Memory PLL analog ground. Memory PLL guard ring / digital power 2.5V. Memory PLL guard ring / digital ground. Display PLL analog power 2.5V. Display PLL analog ground. Display PLL digital power 2.5V. Display PLL digital ground. Analog power (+3.3V) for R (V/Pr) channel. Analog power (+3.3V) for G (Y/Y) channel. Analog power (+3.3V) for B (U/Pb) channel. Analog ground for R (V/Pr) channel. Analog ground for G (Y/Y) channel. Analog ground for B (U/Pb) channel. Analog power supply (+2.5V) for the analog display port. Analog ground for the analog display port. Digital power supply (+2.5V) for the analog display port. Digital ground for the analog display port. Guard ring power for the analog display port. Guard ring ground for the analog display port.
Pin Descriptions
Pinout Information
2.2.4
Miscellaneous Pins
Table 2-4 provides detailed descriptions for Miscellaneous Pins.
Table 2-4 Miscellaneous Pin Descriptions

Name XTALI XTALO RESETn CGMS TCK TDI TDO TMS TRSTn TEST TESTCLK NC NC Pin(s) 40 41 55 146 50 51 48 52 53 56 144 201 62, 63, 194,195 Type I O I I I I O I I I I Function Crystal oscillator input. Connect to an external 10MHz crystal. Crystal oscillator output. Connect to an external 10MHz crystal. Hardware asynchronous reset. The signal is active low. Must be continuously asserted for a minimum of 100 s after power-up to satisfy the SDRAM power-up requirement. [Input, Schmitt trigger, pull-up, 5V-tolerant] CGMS Enable Debug port test data clock. TCK provides the clock input for the Test Bus (also known as the Test Access Port). Debug port test data in. TDI transfers serial test data into VISTA. TDI provides the serial input necessary for JTAG specification support. Debug port test data out. TDO transfers serial test data out of VISTA. TDO provides the serial input necessary for JTAG specification support. Debug port test mode select. TMS is a JTAG specification support signal used by debug tools. Debug port test reset. TRSTn resets the Test Access Port (TAP) logic. TRSTn must be driven low during power on RESETn. Test mode. Active high. Must be low during normal operation. [Input, pull-down, 5Vtolerant] Used for testing, can be used to supply display clock. [Input, pull-down, 5V-tolerant] No connect. No connect.
2.2.5
Host Interface Pins
Table 2-5 provides detailed pin descriptions for the Host Interface.
Table 2-5 Host Interface Pin Descriptions

Name 2WCLK 2WDAT 2WA1 2WA2 Pin(s) 45 47 43 44 Type I I/O I I Function Clock signal of two-wire serial bus. [Input, pull-up, 5V-tolerant] Data signal of two-wire serial bus. [Bi-directional, tri-state 4mA drive output, 5Vtolerant] Programmable two-wire serial bus address bit 1. [Input, pull-down, 5V-tolerant] Programmable two-wire serial bus address bit 2. [Input, pull-down, 5V-tolerant]
2.2.6
Memory Pins
Table 2-6 provides detailed pin descriptions for Memory.
Table 2-6 Memory Pin Descriptions

Name MCLK MCLKFB Pin(s) 229 223 Type O I Function SDRAM clock. This signal is rising edge active. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM clock feedback. For latching in read data. [Input, 5V-tolerant]
Pinout Information Table 2-6 Memory Pin Descriptions (continued)

Name MRAS MCAS MWE MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 Pin(s) 225 226 227 213 210 207 204 203 206 209 211 214 217 215 220 221 218 255 252 248 245 242 239 236 232 231 234 238 241 244 247 250 254 Type O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Descriptions
Function SDRAM row address strobe. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM column address strobe. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant] SDRAM write enable. This signal is active low. [Tri-state output, 8mA drive, 5V-tolerant]
SDRAM address bus. Multiplexed row and column address and bank select. Row addresses use MA[11:0] for 8MB SDRAM and MA[10:0] for 2MB SDRAM. Column addresses use MA[7:0]. [Tri-state output, 8mA drive, 5V-tolerant] Note: MA10 is a control signal during column address charging and pre-charging. For 8MB SDRAM the bank select pins ba0 and ba1 should be connected to MA12 and MA13, respectively. For 2MB SDRAM, connect ba0 to MA12.
SDRAM data bus. [Bi-directional, tri-state 8mA drive output, pull-up, 5V-tolerant]
2.2.7
Digital Display Output Port Pins
Table 2-7 provides detailed pin descriptions for the Digital Display Output Port.
Table 2-7 Digital Display Output Port Pin Descriptions

Name DVS DHS DCLK Pin(s) 103 104 102 Type O O O Function Digital display output port vertical sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port horizontal sync. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port pixel clock. [Tri-state output, 8mA drive, 5V-tolerant]
Pin Descriptions Table 2-7 Digital Display Output Port Pin Descriptions (continued)
Name DENR DENG DENB DEN DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Pin(s) 108 106 107 145 132 133 135 136 138 139 141 142 121 122 124 125 127 128 129 130 110 111 113 114 116 117 118 119 Type O O O I O O O O O O O O O O O O O O O O O O O O O O O O Function
Pinout Information
Display pixel enable red. [Tri-state output, 4mA drive, 5V-tolerant] Digital display pixel enable green. [Tri-state output, 4mA drive, 5V-tolerant] Digital display pixel enable blue. [Tri-state output, 4mA drive, 5V-tolerant] Digital display output port output enable. [Input, pull-up, 5V-tolerant] Active level controlled by DEN_POL [reg 0x61 bit 2]. Note: DEN only controls the data bus [DR(7:0), DG(7:0), DB(7:0)] and not the control signals [DVS, DHS, DCLK, DENR, DENG, DENB]. Digital display output port red data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode 000 011 DR[7:0] Pin Function DPort single pixel output. R[7:0]: red pixel data or V[7:0]: YUV 4:4:4 pixel data. UV[7:0]: ITU-R BT601 YUV 4:2:2 pixel data
Digital display output port green data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode 000 011 DG[7:0] Pin Function DPort single pixel output. G[7:0]: green pixel data or Y[7:0]: YUV 4:4:4 pixel data Y[7:0]: ITU-R BT601 YUV 4:2:2 pixel data
Digital display output port blue data. [Tri-state output, 4mA drive, 5V-tolerant]
uv_mode xxx DB[7:0] Pin Function DPort single pixel output. B[7:0]: blue pixel data or U[7:0]: YUV 4:4:4 pixel data.
2.2.8
Analog Display Port Pins
Table 2-8 provides detailed pin descriptions for the Analog Display Port.
Table 2-8 Analog Display Port Pin Descriptions

Name ADR ADG ADB VREFIN VREFOUT Pin(s) 156 153 150 161 162 Type O O O I O Analog display port red (V/Pr) data. Analog display port green (Y/Y) data. Analog display port blue (U/Pb) data. Reference voltage input. Voltage reference output. This output nominally delivers 1.23v reference voltage from bandgap reference block. It is normally connected to VREFIN pin. Function
Pinout Information Table 2-8 Analog Display Port Pin Descriptions (continued)
Name Pin(s) Type
Pin Descriptions
Function Full-Scale adjust resistor. A resistor should be connected between this pin and AVS33 to control the magnitude of the full-scale video signal. RSET(ohm)=VREFIN(V)*10.66/IOFS(A), where IOFS is full-scale output current. Compensation pin. This pin should be connected through 0.1uF ceramic capacitor to AVD33 (+3.3v) externally.
RSET
159
I/O
COMP
160
i/O
PIN CONFIGURATION
GND AVDD GND VSOUT SOGOUT HSOUT DCK GND V DD R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] V DD V DD GND
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin 1 IDENTIFIER
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
GND AVDD CLAMP MIDSCV GND PV DD PV DD FILT GND VSYNC HSYNC COAST GND PV DD PV DD GND GND VDD VDD GND
MST9883B
PIN DESCRIPTIONS
Pin Name
REDIN GRNIN BLUIN SOGIN CLAMP HSYNC VSYNC COAST SCL SDA A0 R [7:0] G [7:0] B [7:0] DCK HSOUT VSOUT SOGOUT FILT VREF MIDSCV AVDD PVDD VDD GND Reference Reference 3.3v Power 3.3v Power 3.3v Power System Ground
Pin Type
Analog Input Analog Input Analog Input Analog Input Digital CMOS Input Digital CMOS Input Digital CMOS Input Digital CMOS Input Digital CMOS Input Digital CMOS Input/Output Digital CMOS Input Digital CMOS 3-state Output Digital CMOS 3-state Output Digital CMOS 3-state Output Digital CMOS 3-state Output Digital CMOS 3-state Output Digital CMOS 3-state Output Digital CMOS 3-state Output
Function
Red analog input Green analog input Blue analog input Sync on Green analog input External Clamp Input Horizontal SYNC Input Vertical SYNC Input Hold PLL Frequency, do not track HSYNC Serial Interface clock Serial Interface data pin Serial interface address pin Red output data Green output data Blue output data Output data clock HSYNC output VSYNC output SYNC on Green Slicer Output No Connection Internal Reference Bypass Internal Mid-Scale Voltage Bypass Analog Power PLL Power Digital Output Power System Ground
Pin Number(s)
54 48 43 49 38 30 31 29 56 57 55 70-77 2-9 12-19 67 66 64 65 33 58 37 39,42,45,46,51,52,59,62 26,27,34,35 11,22, 23, 69,78,79 1,10,20,21,24,25,28,32,36,4 0,41,44,47,50,53,60,61,63,6 8,80
PIN CONFIGURATION
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54pin TSOP II 400mil x 875mil 0.8mm pin pitch
PIN DESCRIPTION
PIN CLK CKE CS BA0,BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE LDQM, UDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
Standard TSOP
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
21490G-2
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SO
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
FBGA Top View, Balls Facing Down
A6 A13 A5 A9 A4 WE# A3 RY/BY# A2 A7 A1 A3
B6 A12 B5 A8 B4 RESET# B3 NC B2 A17 B1 A4
C6 A14 C5 A10 C4 NC C3 A18 C2 A6 C1 A2
D6 A15 D5 A11 D4 NC D3 NC D2 A5 D1 A1
E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6
G6
H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
BYTE# DQ15/A-1 F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE# G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE#
Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package an d/or data integr ity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
PIN CONFIGURATION
A0A18 = 19 addresses DQ0DQ14 = 15 data inputs/outputs DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY# VCC = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Selects 8-bit or 16-bit mode = Chip enable = Output enable = Write enable = Hardware reset pin, active low = Ready/Busy# output = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Device ground = Pin not connected internally
LOGIC SYMBOL
19 A0A18 DQ0DQ15 (A-1) CE# OE# WE# RESET# BYTE# RY/BY# 16 or 8
VSS NC
PIN DESCRIPTION
Table 1. Z86229 Pin Identification*
I2C SEL GREEN BLUE SEN HIN SMS VIDEO CSYNC LPF 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RED BOX SDO SCK SDA VIN/INTRO VDD VSS (A) RREF
18-Pin DIP/SOIC
Figure 2. Z86229 Pin Configuration
0Q

(WPEVKQP +% #FFTGUU 5GNGEVKQP 8KFGQ 1WVRWV 8KFGQ 1WVRWV 5GTKCN 'PCDNG *QTK\QPVCN +P 5GTKCN /QFG 5GNGEV %QORQUKVG 8KFGQ %QORQUKVG 5[PE .QQR (KNVGT 4GUKUVQT 4GHGTGPEG 2YT 5WRRN[ #PCNQI )0& 8&& 2QYGT 5WRRN[ 8+0+0641 8GTVKECN +P+PVGTTWRV 1WV 5&# 5GTKCN &CVC 5%5GTKCN %NQEM 5&1 5GTKCN &CVC 1WV $1: 15& 6KOKPI 5KIPCN 4'& 8KFGQ 1WVRWV
5[ODQN +% 5'. )4''0 $.7' 5'0 *+0 5/5 8+&'1 %5;0% .2( 44'( 855 #
&KTGEVKQP +PRWV 1WVRWV 1WVRWV +PRWV +PRWV +PRWV +PRWV 1WVRWV 1WVRWV +PRWV
+P1WVRWV +P1WVRWV +PRWV 1WVRWV 1WVRWV 1WVRWV
Note: *DIP and SOIC pin configurations are identical.
#$51.76' /#:+/7/ 4#6+0)5
5[ODQN 8&& 8+0 8176 ++0 +176 +&& 2& 656) 6.
2CTCOGVGT &% 5WRRN[ 8QNVCIG &% +PRWV 8QNVCIG &% 1WVRWV 8QNVCIG &% +PRWV %WTTGPV RGT 2KP &% 1WVRWV %WTTGPV RGT 2KP &% 5WRRN[ %WTTGPV 2QYGT &KUUKRCVKQP RGT &GXKEG 5VQTCIG 6GORGTCVWTG .GCF 6GORGTCVWTG OO HTQO %CUG HQT UGEQPFU
8CNWG VQ VQ 8&& VQ 8&& VQ
7PKV 8 8 8 O# O# O# O9 % %
Notes: *Voltages referenced to VSS (A). Values beyond the maximum ratings listed above may cause damage to the device. Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.
PIN DEFINITIONS Inputs

I2C SEL (Pin 1). This pin selects 28h for writing and 29h for Reset Operation. When the SMS and SEN pins are both in the Low (0) state, the part is in the Reset state; therefore, in the I2C mode, the SEN pin can be used as an NReset input. When SPI mode is used, if three wire operation is required, both SMS and SEN can be tied together and used as the NReset input. In either mode, NReset must be held Low (0) for at least 100 ns.
reading when this input is Low(0). When the input is High(1), the device selects 2Ah for writing and 2Bh for reading.
SEN (Pin 4). This pin enables the signal for the SPI mode
of operation on the Serial Control Port. When this pin is Low (0), the SPI port is disabled and the SDO pin is in the highimpedance state. Transitions on the SCK and SDA pins are ignored. SPI mode operation is enabled when SMS is High (1).
HIN (Pin 5). For this pin, the Horizontal Sync input signal at the CMOS level must be supplied. When the device is used in VIDEO-LOCK mode, the signal pulls the on-chip VCO within the proper range. The circuit uses the frequency of this signal, which must be within +3% Fh, but the overall signal can be of either polarity. When used in the H-lock mode, the VCO phase locks to the rising edge of this signal. The HPOL bit of the H Position register can be set to operate with either polarity of input signal. This signal is usually the H Flyback signal. The timing difference between HIN rising edge and the leading edge of composite sync (of VIDEO input) is one of the factors which affects the horizontal position of the display. Any shift resulting from the timing of this signal can be compensated for with the horizontal timing value in the H Position Register. H-lock is intended for use when the part is generating an OSD display when no video signal is present. SMS (Pin 6). This pin allows the mode select pin for the Se-
Input/Output
VIN/INTRO (Pin 13). In external (EXT) vertical lock mode
of operation, the internal vertical sync circuits lock to the V IN input signal applied at this pin. The part locks to the rising or falling edge of the signal in accordance with the setting of the V Polarity command. The default is rising edge. The VIN pulse must be at least 2 lines wide. In INTRO Mode, when configured for internal vertical synchronization, this pin is an output pin providing an interrupt signal to the master control device in accordance with the settings in the Interrupt Mask Register.
SDA (Pin 14). When the Serial Control Port has been set to
I2C mode operation, this pin serves as the bidirectional data line for sending and receiving serial data. In SPI mode operation, the device operates as a serial data input. SPI mode output data is available on the SDO pin.
Outputs
RED, GREEN, BLUE (Pins 2, 3, 18). These pins are osi-
tive-acting CMOS-level signals.
Color Mode: Red, Green, and Blue characters are incorporated as video outputs for use in a color receiver Mono Mode: In this mode, all three outputs carry the character luminance information
rial Control Port. When this input is at a CMOS High state (1), the Serial Control Port operates in the SPI mode. When the input is Low (0), the Serial Control Port operates in the I2C slave mode. In SPI mode, the SEN pin must be tied High. (See Reset Operation section.)
VIDEO (Pin 7). This pin is a composite NTSC video input,
Note: The selection of Color/Mono Mode is user controlled in
1.0V p-p (nom), band limited to 600 kHz. The circuit operates with signal variation between 0.71.4V p-p. The polarity is sync tips negative. This signal pin should be AC coupled through a 0.1 F capacitor, driven by a source impedance of 470 ohms or less.
SCK (Pin 15). This pin is an input for a serial clock signal
bit D1 of the Configuration Register (Address=00h). (See Internal Registers section.)
CSync (Pin 8). Sync slice level. A 0.1 F capacitor must be
tied between this pin and analog ground VSS(A). This capacitor stores the sync slice level voltage.
LPF (Pin 9). Loop Filter. A series RC low-pass filter must
from the master control device. In I2C mode operation, the clock rate is expected to be within I2C limits. In SPI mode, the maximum clock frequency is 10 MHz.
be tied between this pin and analog ground V SS(A). There must also be second capacitor from the pin to V SS(A).
2+0 &'(+0+6+105
10 kOhms, 2%.
%QPVKPWGF
RREF (Pin 10). Reference setting resistor. Resistor must be
Power Supply
VSS (Pins 11). These pins are the lowest potential power pins for the analog and digital circuits. They are normally tied to system ground. VDD (Pin 12). The voltage on this pin is nominally 5.0
SDO (Pin 16). This pin provides the serial data output when
SPI mode communications have been selected. This pin is not used in I2C mode operation.
BOX (Pin 17). Black box keying output is an active High,
CMOS-level signal used to key in the black box for captions/text displays. This output is in a high-impedance state when the background attribute has been set to semi-transparent.
Volts, and may range between 4.75 to 5.25 Volts with respect to the V SS pins.
Note: The recommended printed circuit pattern for implement-
ing the power connection and critical components is referenced in the Recommended Application Information section on page 49.
General Description
The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 20 ns s Wide operating voltage range: 26V s Low input current: 1 A maximum s Low quiescent current: 80 A maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number MM74HC374WM MM74HC374SJ MM74HC374MTC MM74HC374N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Output Control L L L H L X H L X X H L Q0 Z Clock Data Output
Top View
H = HIGH Level L = LOW Level X = Don't Care = Transition from LOW-to-HIGH Z = High Impedance State Q0 = The level of the output before steady state input conditions were established
Pin Out
THC63LVDM83R THC63LVDM63R
RS TD1 TA5 TA6 GND TB0 TB1 TD2 VCC TD3 TB2 TB3 GND TB4 TB5 TD4 R/F TD5 TB6 TC0 GND TC1 TC2 TC3 TD6 VCC TC4 TC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
TA4 TA3 TA2 GND TA1 TA0 TD0 LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ LVDS GND PLL GND PLL VCC PLL GND /PDWN CLK IN TC6 GND
TA4 1 2 RS TA5 3 TA6 4 GND 5 TB0 6 TB1 7 VCC 8 9 TB2 10 TB3 GND 11 TB4 12 TB5 13 R/F 14 TB6 15 TC0 16 17 GND TC1 18 TC2 19 TC3 20 VCC 21 TC4 22 TC5 23 GND 24
48 47 46 45 44
43
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
TA3 TA2 GND TA1 TA0 N/C LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ LVDS GND PLL GND PLL VCC PLL GND /PDWN CLK IN TC6
THine
THC63LVDM83R Pin Description
Pin Name TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 /PDWN Pin # 47, 48 45, 46 41, 42 37, 38 39, 40 51, 52, 54, 55, 56, 3, 4 6, 7, 11, 12, 14, 15, 19 20, 22, 23, 24, 27, 28, 30 50, 2, 8, 10, 16, 18, 25 32 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN IN H: Normal operation, L: Power down (all outputs are Hi-Z) Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
LVDS swing control.

RS 1 IN RS VCC : GND LVDS swing 350mV : 200mV
R/F VCC CLKIN GND LVDS VCC LVDS GND PLL VCC PLL GND
17 9, 26 31 5, 13, 21, 29, 53 44 36, 43, 49 34 33, 35
IN Power IN Ground Power Ground Power Ground
Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Pins for TTL inputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
THC63LVDM63R Pin Description

Pin Name TA+, TATB+, TBTC+, TCTCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 /PDWN Pin # 40, 41 38, 39 34, 35 32, 33 44, 45, 47, 48, 1, 3, 4 6, 7, 9, 10, 12, 13, 15 16, 18, 19, 20, 22, 23, 25 27 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN H: Normal operation, L: Power down (all outputs are Hi-Z) Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
LVDS swing control.

RS 2 IN RS VCC : GND LVDS swing 350mV : 200mV
Pin Name R/F VCC CLKIN GND LVDS VCC LVDS GND PLL VCC PLL GND
Pin # 14 8, 21 26 5, 11, 17, 24, 46 37 36, 42 29 28, 30
Type IN Power IN Ground Power Ground Power Ground
Description Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Pins for TTL inputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
Absolute Maximum Ratings 1

Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Output Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4sec) Maximum Power Dissipation @+25 C -0.3V ~ +4.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) continuous +150 C -65 C ~ +150 C +260 C 1.4W
Electrical Characteristics CMOS/TTL DC Specifications

VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VIH VIL IINC IPD IRS Parameter High Level Input Voltage Low Level Input Voltage Input Current Pull Down Current RS Pull Down Current
0V VIN V CC
Conditions
Min. 2.0 GND
Typ.
Max. VCC 0.8

10
Units V V A A A
R/F pin, VIH=VCC RS pin, VIH=VCC
100 100
1. Absolute Maximum Ratings are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of Electrical Characteristics specify conditions for device operation.
Input configuration
Power amplifier
Issued Date: September 18, 2003 Model No.: V270W - L03
Approval
TFT LCD Approval Specification
MODEL NO.: V270W1 - L03

Customer: Approved by: Note:
LCD TV Marketing and Project Management Dept. Project Manager
- CONTENTS -
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The information described in this technical specification is tentative and it is possible to be changed without prior notice. Please contact CMO s representative while your product design is based on this specification. Version 2.0
Approval
- CONTENTS REVISION HISTORY 1. GENERAL DESCRIPTION
1.1 OVERVIEW 1.2 FEATURES 1.3 APPLICATION 1.4 GENERAL SPECIFICATIONS 1.5 MECHANICAL SPECIFICATIONS -------------------------------------------------------------------------------------------------------------
3 4
2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT 2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE 2.2.2 BACKLIGHT UNIT
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE 3.2 BACKLIGHT UNIT
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4. BLOCK DIAGRAM
4.1 TFT LCD MODULE 4.2 BACKLIGHT UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE 5.2 BACKLIGHT UNIT 5.3 BLOCK DIAGRAM OF INTERFACE 5.4 LVDS INTERFACE 5.5 COLOR DATA INPUT ASSIGNMENT
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS 6.2 POWER ON/OFF SEQUENCE
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15
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS 7.2 OPTICAL SPECIFICATIONS
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17
8. PACKAGING
8.1 PACKING SPECIFICATIONS 8.1 PACKING METHOD
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21
9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
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10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS 10.2 SAFETY PRECAUTIONS
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24
11. MECHANICAL CHARACTERISTICS
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REVISION HISTORY
Version Ver 1.0 Ver 2.0 Date August 1,03 Sep. 18,03 Page Section Description (New) All 17 All 7.2 Preliminary Specification is first issued. Contrast ratio:Typ. (600)600 Response time TR:Typ. (15)15 TF: Typ. (10)10 Gray to Gray: Typ (16.6)16.6 Center Luminance of White: Min. (450)450 Typ. (550)550 Average Luminance of White: Min. (400)400 Typ. (450)450
Color Chromaticity Min. Typ. Max. Min. Red Rx (0.616)(0.646)(0.676)0.616 Ry (0.302)(0.332)(0.362)0.302 Green Gx(0.239)(0.269)(0.299)0.239 Gy(0.570)(0.600)(0.630)0.570 Blue Bx(0.112)(0.142)(0.172)0.112 By(0.042)(0.072)(0.102)0.042
Viewing Angle Horizontal x+ Typ. (85)85 x- Typ. (85)85 Vertical Y+ Typ. (85)85 Y- Typ. (85)85 Shock (Non-Operating) Max. Value (100)100 Vibration (Non-Operating) Max. Value (1.0)1.0
Typ.
Max.
0.646 0.332 0.269 0.600 0.142 0.072
0.676 0.362 0.299 0.630 0.172 0.102
2.1
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Approval
1. GENERAL DESCRIPTION
1.1 OVERVIEW
V270W1- L03 is a 27 TFT Liquid Crystal Display module with 14-CCFL Backlight unit and 1ch-LVDS interface. This module supports 1280 x 720 WXGA format and can display true 16.7M colors ( 8-bit/color). The inverter module for backlight is build-in.
1.2 FEATURES
- Ultra wide viewing angle Super MVA technology - High brightness (550 nits) - High contrast ratio (600:1) - Fast response time - High color saturation NTSC 75% - WXGA (1280 x 720 pixels) resolution, true HDTV format. - DE (Data Enable) only mode - LVDS (Low Voltage Differential Signaling) interface
1.3 APPLICATION
- TFT LCD TVs
1.4 GENERAL SPECIFICATIONS

Item Active Area Bezel Opening Area Driver Element Pixel Number Pixel Pitch (Sub Pixel) Pixel Arrangement Display Colors Display Operation Mode Surface Treatment Specification 597.12(H) x 335.88 (V) (26.97 diagonal) 603.22 (H) x 341.98 (V) a-si TFT active matrix 1280 x R.G.B. x 720 0.1555 (H) x 0.4665 (V) RGB vertical stripe 16.7M Transmissive mode / Normally black Anti-glare with anti-reflective coating Hard coating (2H), Haze: 40% Reflection Rate: < 2% Unit mm mm pixel mm color Note (1) -
1.5 MECHANICAL SPECIFICATIONS

Item Horizontal(H) Vertical(V) W/O INV Depth(D) W/I INV Weight Min. 40 Typ. 637.55 379.8 40.5 4300 Max. 36 41 Unit mm mm mm mm g Note Module Size Depth(D) -
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions. Note (2) Module Depth does not include connectors.
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Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Storage Temperature Operating Ambient Temperature Shock (Non-Operating) Vibration (Non-Operating) (a) 90 %RH Max. (Ta 40 C). (b) Wet-bulb temperature should be 39 C Max. (Ta > 40 C). (c) No condensation. Note (2) The temperature of panel display area surface should be 0 C Min. and 60 C Max. Note (3) 2 ms, half sine wave, 1 time for X, Y, Z. Note (4) 10 ~ 500 Hz, 10 min, 1 time each X, Y, Z. Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture. Symbol TST TOP SNOP VNOP Value Min. -20 0 Max. +60 +50 100 1.0 Unit C C G G Note (1) (1), (2) (3), (5) (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
Relative Humidity (%RH)

100 90 80
60
Operating Range
40
20 5 -40 -20 0
Storage Range
20 40 60 80
Temperature (C)
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2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE
Item Power Supply Voltage Logic Input Voltage Symbol Vcc VIN Value Min. -0.3 -0.3 Max. +6.0 4.3 Unit V V Note (1)
2.2.2 BACKLIGHT UNIT

Item Lamp Voltage
On/Off Control Voltage Internal/External PWM Select Voltage Internal PWM Control Voltage External PWM Control Voltage Operating Temperature Storage Temperature
Symbo VL
VBLON VSEL VIPWM VEPWM TOP TST
Test
595% RH 595% RH
Min.
0
Type
Max.
3.0K
Unit
Note
VRMS (1), (2), IL = 4.7 mA
-0.3
0 -30
75 80
(3)
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation should be restricted to the conditions described under Normal Operating Conditions. Note (2) Specified values are for lamp (Refer to 3.2 for further information). Note (3) Protect inverters from moisture condensation and freezing.
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Parameter Power Supply Voltage Ripple Voltage Rush Current White Black Vertical Stripe LVDS differential input high threshold voltage LVDS differential input low threshold voltage LVDS common input voltage Terminating Resistor Power Supply Current Note (2) Measurement Conditions: Symbol Vcc VRP IRUSH lcc VTH VTL Vic RT Min. 4.5 -100 1.125 Value Typ. 5.0 2.1 1.4 1 1.2 1.25 100 Max. 5.5 200 3 +100 1.375 Ta = 25 2 C Unit V mV A A A A mV mV V ohm Note (2) (3)a (3)b (3)c
Note (1) The module should be always operated within above ranges.
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Approval
+5.0V Q1 2SK1475 Vcc FUSE R1 47K C3 (LCD Module Input) 1uF
(High to Low) (Control Signal) R2 SW 1K +12V 47K
Q2 2SK1470
VR1 C1
C2
0.01uF 1uF
Vcc rising time is 470s

+5V
0.9Vcc 0.1Vcc
GND 470s
Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 2 C, fv = 60 Hz, whereas a power dissipation check pattern below is displayed. a. White Pattern b. Black Pattern
Active Area
Active Area
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Approval
c. Vertical Stripe Pattern
R G B R G B B R G B R G B R B R G B R G B R R G B R G B
Active Area
3.2 BACKLIGHT UNIT

Parameter Lamp Input Voltage Lamp Current Lamp Turn On Voltage Operating Frequency Lamp Life Time Power Consumption Symbol VL IL VS FL LBL PL Min. 1008 4.4 1200 1790 54 50K Value Typ. 1120 4.7 56 92 Max. 1232 5.0 3000 3000 58 Unit
Ta = 25 2 C Note
VRMS IL = 4.7 mA mARMS (1) VRMS (2), Ta = 25 C (2), Ta = 0 C VRMS KHz (3) Hrs (5) W (4), Inverter Input
Note (1) Lamp current is measured by utilizing high frequency current meters as shown below:
A A A A A A A A A A A A A A
HV (Pink) HV (White) HV (Pink) HV (White) HV (Pink) HV (White) HV (Pink) HV (White) HV (Pink) HV (White) HV (Pink) HV (White) HV (Pink) HV (White)
1 2 1 2 1 2 1 2 1 2 1 2 1 2 LV (Gray)
LCD Module
Inverter
Note (2) The voltage shown above should be applied to the lamp for more than 1 second after startup.
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Approval
Otherwise the lamp may not be turned on. Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the display, and this may cause line flow on the display. In order to avoid interference, the lamp frequency should be detached from the horizontal synchronous frequency and its harmonics as far as possible. Note (4) PL =(lamp1-lamp14 IL VL )/0.8, PL is based on the inverter efficiency, which is 80%. Note (5) The lifetime of a lamp is defined as the time in which it continues to operate under the condition Ta = 25 2 oC and IL = (4.35) ~ (4.95) mArms until one of the following events occurs: (a) When the brightness becomes equal or less than 50% of its original value. (b) When the effective discharge length becomes equal or less than 80% of its original value. (Effective discharge length is defined as an area that has equal or more than 70% brightness compared to the brightness at the center point.) Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the inverter must have specifications for the modularized lamp. The performance of the Backlight, such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for the lamp. All the parameters of an inverter should be carefully designed to avoid producing too much current leakage from high voltage output of the inverter. When designing or ordering the inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module should be operated in the same manners when it is installed in your instrument.
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Approval
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
SCAN DRIVER IC
LVDS INPUT /
RX0(+/-) RX1(+/-) RX2(+/-) RX3(+/-) RXC(+/-)
OVER DRIVING CONTROLLER /
TIMING CONTROLLER
TFT LCD PANEL (1280x3x720)
INPUT CONNECTOR (JAE-FI-SE30P-HF)
Vcc GND
DATA DRIVER IC DC/DC CONVERTER & REFERENCE VOLTAGE
VL
LAMP CONNECTOR
BACKLIGHT UNIT
4.2 BACKLIGHT UNIT

Lamp connector HV : BHR-03-VS-1(JST) *7 LV : ZHR-2 (JST) *1 1 LV(Gray) 1 HV(Pink) 2 HV(White)
2 HV(White) 1 HV(Pink) 2 HV(White)
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I25 26 27 28 29 30 Name NC NC NC NC NC NC NC GND RX3+ RX3RXCLK+ RXCLKGND GND RX2+ RX2RX1+ RX1RX0+ RX0GND GND GND GND GND VCC VCC VCC VCC VCC Description No Connection No Connection No Connection No Connection No Connection No Connection No Connection Ground Positive LVDS differential data input. Channel 3 Negative LVDS differential data input. Channel 3 Positive LVDS differential clock input. Negative LVDS differential clock input. Ground Ground Positive LVDS differential data input. Channel 2 Negative LVDS differential data input. Channel 2 Positive LVDS differential data input. Channel 1 Negative LVDS differential data input. Channel 1 Positive LVDS differential data input. Channel 0 Negative LVDS differential data input. Channel 0 Ground Ground Ground Ground Ground +5.0V power supply +5.0V power supply +5.0V power supply +5.0V power supply +5.0V power supply
Note (1) Connector Part No.: FI-SE30P-HF (JAE) Note (2) The first pixel is even.
5.2 BACKLIGHT UNIT

Pin 1 2 Symbol HV HV Description High Voltage High Voltage Color Pink White
Note (1) Connector Part No.: BHR-03VS-1 (JST) or equivalent Note (2) Users connector Part No.: SM02(8.0)B-BHS-1TB (JST) or equivalent Pin 1 2 Symbol LV NC Description Low Voltage No Connection Color Gray
Note (1) Connector Part No.: ZHR-2 (JST) or equivalent Note (2) Users connector Part No.: S2B-ZR-SM3A-TF (JST) or equivalent
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Approval
5.3 BLOCK DIAGRAM OF INTERFACE CNF1
Rx0+ R0-R7 G0-G7 B0-B7 DE TxIN Rx0Rx1+ Rx1Rx2+ Rx2Rx3+ Rx3Host Graphics Controller LVDS Transmitter THC63LVDM83A (LVDF83A)
R0~R7 G0~G7 B0~B7 DE : Pixel R Data : Pixel G Data : Pixel B Data : Display timing signal
51
100pF
RxOUT
51 51
100pF
R0-R7 G0-G7 B0-B7 DE
51 51
100pF
51 51
100pF
51
CLK+ PLL CLK-
51
100pF
PLL
DCLK Timing Controller
51
LVDS Receiver THC63LVDF84A
Notes: 1) The system must have the transmitter to drive the module. 2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used differentially.
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Approval
5.4 LVDS INTERFACE
SIGNAL TRANSMITTER THC63LVDM83A PIN INPUT INTERFACE CONNECTOR Host TFT-LCD PIN RECEIVER THC63LVDF84A OUTPUT TFT CONTROL INPUT
R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 24bit B5 DE R6 R7 G6 G7 B6 B7 RSVD 1 RSVD 2 RSVD 3
51 52 54 55 56 3 4 6 7 11 12 14 15 19 20 22 23 24 30 50 2 8 10 16 18 25 27 28
TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN7 TxIN8 TxIN9 TxIN12 TxIN13 TxIN14 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN26 TxIN27 TxIN5 TxIN10 TxIN11 TxIN16 TxIN17 TxIN23 TxIN24 TxIN25
TA OUT0+ TA OUT0-
Rx 0+ Rx 0-
TA OUT1+ TA OUT1-
Rx 1+ Rx 1-
TA OUT2+ TA OUT2-
Rx 2+ Rx 2-
TA OUT3+ TA OUT3-
Rx 3+ Rx 3-
27 29 30 32 33 35 37 38 39 43 45 46 47 51 53 54 55 1 6 7 34 41 42 49 50 2 3 5
Rx OUT0 Rx OUT1 Rx OUT2 Rx OUT3 Rx OUT4 Rx OUT6 Rx OUT7 Rx OUT8 Rx OUT9 Rx OUT12 Rx OUT13 Rx OUT14 Rx OUT15 Rx OUT18 Rx OUT19 Rx OUT20 Rx OUT21 Rx OUT22 Rx OUT26 Rx OUT27 Rx OUT5 Rx OUT10 Rx OUT11 Rx OUT16 Rx OUT17 Rx OUT23 Rx OUT24 Rx OUT25
R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 DE R6 R7 G6 G7 B6 B7 Not connect Not connect Not connect
DCLK
31
TxCLK IN
TxCLK OUT+ RxCLK IN+ 26 TxCLK OUT- RxCLK IN-
RxCLK OUT
DCLK
R0~R7: Pixel R Data (7; MSB, 0; LSB) G0~G7: Pixel G Data (7; MSB, 0; LSB) B0~B7: Pixel B Data (7; MSB, 0; LSB) DE : Display timing signal
Notes: 1)RSVD(reserved)pins on the transmitter shall be H or L.
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Approval
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color. The higher the binary input, the brighter the color. The table below provides the assignment of color versus data input. Color Black Red Green Basic Blue Colors Cyan Magenta Yellow White Red(0) / Dark Red(1) Red(2) Gray : Scale : Of Red(253) Red Red(254) Red(255) Green(0) / Dark Green(1) Green(2) Gray : Scale : Of Green(253) Green Green(254) Green(255) Blue(0) / Dark Blue(1) Blue(2) Gray : Scale : Of Blue(253) Blue Blue(254) Blue(255) 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 Red 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 0 1 : : 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 0 0 1 1 1 0 1 0 : : 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 Data Signal Green 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 0 1 : : 0 1 1 0 0 0 : : 0 0 0 0 0 1 0 1 0 1 1 0 0 0 : : 0 0 0 0 1 0 : : 1 0 1 0 0 0 : : 0 0 0 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 Blue 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 0 1 : : 0 1 1 0 0 0 1 1 1 0 1 0 0 0 : : 0 0 0 0 0 0 : : 0 0 0 0 1 0 : : 1 0 1
R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 G5 G4 G3 G2 G1 G0 R7 R6 B5 B4 B3 B2 B1 B0
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram. Signal Clock Vertical Active Display Term Item Frequency Frame Rate Total Display Blank Total Display Blank Symbol 1/Tc Fr Tv Tvd Tvb Th Thd Thb Min. 70 48 730 720 10 1450 1280 170 Typ. 74.25 60 750 720 30 1650 1280 370 Max. 80 850 720 130 2000 1280 720 Unit Note MHZ Hz Tv=Tvd+Tvb Th Th Th Tc Th=Thd+Thb Tc Tc -
Horizontal Active Display Term
Note: Because of this module is operated by DE only mode, Hsync and Vsync input signals should be set to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
Tv Tvd Tvb
DE Th
DCLK Tc DE Thb Thd
DATA
Valid display data (1280 clocks)
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6.2 POWER ON/OFF SEQUENCE To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram below.
Power Supply VCC

0V 0T110ms 0T250ms 0T350ms 1sT4
0.9 VCC 0.1VCC
0.9 VCC 0.1VDD
T1
T3
T2
T4
Signals
0V
VALID
Power Off
Power On
Backlight (Recommended) 450msT5 100msT6

T5
50%
50%
T6
Power ON/OFF Sequence
Note. (1) The supply voltage of the external system for the module input should be the same as the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD operation of the LCD turns off before the backlight turns off, the display may momentarily become abnormal screen. (3) In case of VCC = off level, please keep the level of input signals on the low or keep a high impedance. (4) T4 should be measured after the module has been fully discharged between power of and on period. (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Ambient Temperature Ambient Humidity Supply Voltage Input Signal Inverter Current Inverter Driving Frequency Inverter Symbol Value Unit o Ta C 252 Ha %RH 5010 VCC 5.0 V According to typical value in "3. ELECTRICAL CHARACTERISTICS" IL 4.7 mA FL 56 KHz --
7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be measured under the test conditions described in 7.1 and stable environment shown in Note (7). Item Contrast Ratio Response Time Center Luminance of White Average Luminance of White White Variation Cross Talk Red Color Chromaticity Green Blue White Viewing Angle Horizontal Vertical Symbol CR TR TF Gray to gray LC LAVE W CT Rx Ry Gx Gy Bx By Wx Wy x+ xY+ YCondition Min. 400 Typ. 600 15 10 16.6 450 400 0.616 0.302 0.239 0.570 0.112 0.042 0.255 0.263 550 450 0.646 0.332 0.269 0.600 0.142 0.072 0.285 0.293 85 85 85 85 Max. 25 20 Unit ms ms ms Note
Note(2) Note(3) Note(4)
x=0, Y =0 Viewing Normal Angle
CR10
cd/m2 Note(5) cd/m2 Note(8) 1.6 Note(6) 4.0 % 0.676 0.362 0.299 0.630 0.172 0.102 0.315 9, 300K 0.323 No gray scale Deg. inversion -
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Note (1) Definition of Viewing Angle (x, y): Viewing angles are measured by Eldim EZ-Contrast 160R Normal x = y = 0 yX- = 90 xx x+ y+ y+ 12 oclock direction y+ = 90
6 oclock y- = 90
y-
x+
X+ = 90
Note (2) Definition of Contrast Ratio (CR): The contrast ratio can be calculated by the following expression. Contrast Ratio (CR) = L255 / L0 L255: Luminance of gray level 255 L 0: Luminance of gray level 0 CR = CR (5) CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (8). Note (3) Definition of Response Time (TR, TF):
Gray Level 255

100% 90%
Gray Level 255
Optical Response Gray Level 0

10% 0%
TF
TR
Time
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Approval
Note (4) Definition of Gray to Gray Switching Time:
Drive signal of LCD Panel
Time
100% 90%
Optical Response
10% 0%
Gray to gray switching time
Gray to gray switching time
Time
The driving signal means the signal of gray level 0,63,127,191,255. Note (5) Definition of Luminance of White (LC, LAVE): Measure the luminance of gray level 255 at center point and 5 points LC = L (5) LAVE = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5 L (x) is corresponding to the luminance of the point X at the figure in Note (8). Note (6) Definition of Cross Talk (CT): CT = | YB YA | / YA 100 (%) Where: YA = Luminance of measured location without gray level 0 pattern (cd/m2) YB = Luminance of measured location with gray level 0 pattern (cd/m2) Active Area
YA, U (D/2,W/8)
(0, 0)
(0, 0) (D/4,W/4)
Active Area
YB, U (D/2,W/8)
YA, L (D/8,W/2)
Gray 128
YB, L (D/8,W/2) YA, R (7D/8,W/2) YB, D (D/2,7W/8) (D,W)
Gray 00 Gray
Gray 128
YB, R (7D/8,W/2) (3D/4,3W/4)
YA, D (D/2,7W/8)
(D,W)
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Note (7) Measurement Setup: The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight for 1 hour in a windless room.
LCD Module LCD Panel Center of the Screen Display Color Analyzer (Minolta CA210)
Light Shield Room (Ambient Luminance < 2 lux)
Note (8) Definition of White Variation (W): Measure the luminance of gray level 255 at 5 points W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Horizontal Line D
D/4 D/2 3D/4
Vertical Line
W/4
2 X
W/2
: Test Point X=1 to 5
3W/4
Active Area
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8. PACKAGING 8.1 PACKING SPECIFICATIONS (1) 4 LCD TV Modules / Carton (2) Carton Dimensions : 742(L) X 327 (W) X 510 (H) (3) Weight : Approximately 19Kg ( 4 Modules Per Carton) 8.2 PACKING METHOD Figures 8-1 and 8-2 are the packing method
LCD TV Module
Tape
Carton dimensions: 742(L)x327(W)x510(H)mm Weight : Approx 19Kg(4 modules per 1 carton)
Anti-Static Bag
PE Foam(Bottom)
Drier
Carton
Carton Label
Figure.8-1 packing method
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Corner Protector:L1020*50mm*50mm Pallet:L1100*W1100*H135mm Bottom Cap:L1100*W1100*H120mm Pallet Stack:L1100*W1100*H1163mm Gross Weight:180kg
PE Sheet Carton Label Film
Bottom Cap PP Belt
Figure. 8-2 packing method
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
CHI
MEI
E207943
V270W1
MADE IN TAIWAN
OPTOELECTRONICS
-L03 Rev. XX
MADE IN TAIWAN
XXXXXXXYMDLNNNN
(a) Model Name: V270W1-L03 (b) Revision: Rev. XX, for example: A0, A1 B1, B2 or C1, C2etc. (c) Serial ID: X X X X X X X Y M D L N N N N Serial No. Product Line Year, Month, Date CMO Internal Use CMO Internal Use Revision CMO Internal Use Serial ID includes the information as below: (a) Manufactured Date: Year: 1~9, for 2000~2009 Month: 1~9, A~C, for Jan. ~ Dec. Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U. (b) Revision Code: Cover all the change (c) Serial No.: Manufacturing sequence of product (d) Product Line: 1 -> Line1, 2 -> Line 2, etc.
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Approval
10. PRECAUTIONS
10.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly. (2) It is recommended to assemble or to install a module into the users system in clean working areas. The dust and oil may cause electrical short or worsen the polarizer. (3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight. (4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the damage and latch-up of the CMOS LSI chips. (5) Do not plug in or pull out the I/F connector while the module is in operation. (6) Do not disassemble the module. (7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily scratched. (8) Moisture can easily penetrate into LCD module and may cause the damage during operation. (9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD modules in the specified storage conditions. (10) When ambient temperature is lower than 10C, the display quality might be reduced. For example, the response time will become slow, and the starting voltage of CCFL will be higher than that of room temperature.
10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit. (2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap. (3) After the modules end of life, it is not harmful in case of normal operation and storage.
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11. MECHANICAL CHARACTERISTICS
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Exploded View Diagram

1 Akai LCD TV

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SERVICE MANUAL

PRECAUTIONS DURING SERVICING

X-RAY RADIATION PRECAUTION

MAKE YOUR CONTRIBUTION TO PROTECT THE ENVIRONMENT

PRODUCT SAFETY NOTICE

Goo d ea rth grou nd su ch as th e wat er p ip e , c o n du c t or , etc.

Pl ace this pro be on eac h e x p os ed me t al li c part

AC Leak age Curr ent Check

- ADAPTIVE 2/4 LINE COMB FILTER FOR PAL/NTSC

GENERAL SPECIFICATIONS ITEM DESCRIPTION

C U3 SYNC U10 PC SWITCH YPrPb ADC BUFFER U11 U14

TV AUDIO AV AUDIO AUDIO SCART AUDIO DECODER POWER AMP

POWER A 24VDC 11----20VDC 5VDC 5VDC_SB 3VDC_SB STAND BY A

R28 AV2_L SD R41 AV2_R SL SD SR

CON5 is for LCD control (J24's) supplement, D MUTE D

R35 22R C26 R37 2.2K C

RCA1 2 1 1,7,9 7 7,1 7,1 GREEN 7,1

U21 1 2 3 4 5 6 7 8 0Y 2Y YOUT 3Y 1Y INH VEE VSS VDD 2X 1X XOUT 0X 3X A B CD4052 VCC 16 15 14 13 12 11 10 9

C234 0.1 DEN DDEN DVI-DE A B1 A B1

V-RED U26 bypass cap

R193 470 R68 470

HS_IN VS_IN SDA SCL SEN PREF

GND R73 10K 10 6 1 11 GND GND

D13 R74 IN4148 R76

V-BOX C75 33pF

C80 V33VT 100uF/16V

R207 470 +12 R205 22K R206 470

CVBS0 VDDA VDDC VDDP

L41 FB B 3 IC9 7805 IN GND OUT 1 L42 FB

A R208 5.6K RST1#

ADC0 ADC1 ADC2 ADC3

VOUT VOUT RST1# RST1#

SDA SCL SCL D 2 CN3 2 1 CON2

C42 47nF GND GND

GND VID_BUS 5,6,8,9

VINY7 VINY6 VINY5 VINY4 VINY3 VINY2 VINY1 VINY0

L39 VINCK 11R/100MHZ 11R/100MHZ VHREF VINHS VINVS VIODD +5

C44 47nF C33 1nF GND

R248 0_NS R249 R250 0_NS 0_NS VSS 16

V-BLU S-B V-GRN S-G

S1A S2A S1B S2B

BLU GRN RRED V-BOX1

V-RED S-R GND A2 A1 A0 4 3 2 1 V-BOX RGB/V R251 6.8K

S1C S2C S1D S2D IN EN

5 6 VDD C53 0.1 7 8

SDA SCL TEST VCC

DISPLAY BUS (G-PORT)

PW1230 MEMORY BUS

BSL1 BSL0 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

VCC VCC VCC VCC VCC VCC VCC

DDHS DDVS DEN

NVRAS# NVCAS# NVWE#

SDA SCL RST1#

SDA SCL RST1#

149 163 166

5 34 93 123 140 175 205 235

151 154 157

R191 58 60 10K VYY VZZ

VDD VDD VDD VDD VDD VDD VDD VDD

ADDVDD ADAVDD ADGVDD

AVD33B AVD33G AVD33R

19 49 77 112 134 187 219 251

148 164 167 BGND