Professional Documents
Culture Documents
L5 CLblocks
L5 CLblocks
Credits:
Slides adapted from:
J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 A.B. Marcovitz, Intro. to Logic and Computer Design, McGraw Hill, 2008 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005
1
it passes (connects) one of its data inputs to the output. the data input selected is a function of a set of control inputs called selection inputs.
A 0 1 Z I0 I1
I1 0 0 0 0 1 1 1 1
I0 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
Z 0 0 1 0 0 1 1 1
2
Multiplexers (contd)
Z mk I k
k 0
2 n 1
2:1 mux
4:1 mux
Cascading multiplexers
8:1 mux
4:1 mux
4:1 mux
Control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 Control signal A chooses which of the upper or lower mux's output to gate to Z
with the variables used as control inputs and the data inputs tied to 0 or 1
1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B
Example:
Z F
Generalization
data inputs can also be tied to variables not just 0s an 1s
I0
.
I1
. .
. . . In-1 In
. . . . 0 1 0 0 0 1
F
1 0 1 1
In
In'
Activity
0 when BC
D when BC
A when BC
0 D A 0
0 1 4:1 MUX 2 3 S1 S0 B C
0 when BC
Demultiplexers
Route a single input to one of many outputs, as a function of a set of control inputs
y0 y1 y2 y3 y4 y5 y6 y7
1:8 demux
s[2:0]
10
Three-State Buffers
Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other (multiple drivers conflict).
B1 B2 1 ?
Use of tri-state logic permits the outputs of two or more gates or other logic devices to be connected together
11
When the enable B is 1, the output C equals A. When the enable B is 0, the output C acts like an open circuit. In this case the output C is effectively disconnected from the buffer output so that no current can flow. This is often referred as Hi-Z (high-impedance) state because the circuit offers a very high impedance to the flow of current.
12
13
14
15
16
Decoders
A decoder is a logic circuit that converts coded inputs into coded outputs. Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs)
17
Decoders (contd)
Decimal
18
Binary Decoders
The most common decoder circuit is an n-to-2n decoder (or binary decoder)
19
20
21
1:2 decoders
G
O0 O1 O2 O3
\G active-low enable
O0 O1 O2 O3
active-high enable
2:4 decoders
22
S1 S0
S1 S0
n-to-2n decoders can implement any function of n variables with the variables used as control inputs the appropriate minterms summed to form the function
0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B C A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC
decoder generates appropriate minterm based on control signals (it "decodes" control signals)
23
F1
F2
F3
24
Encoders
An encoder performs the inverse function as a decoder The simplest encoder to build is a 2n-to-n (binary encoder)
25
Priority Encoders
I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE
0
1 0 0
0
x 1 0
0
x x 1
0
x x x
0
x x x
0
x x x
0
x x x
0
x x x
0
1 1 1
0
1 1 0
0
1 0 1
1
0 0 0
0
0 0 0 0
0
0 0 0 0
0
0 0 0 0
1
0 0 0 0
x
1 0 0 0
x
x 1 0 0
x
x x 1 0
x
x x x 1
1
0 0 0 0
0
1 1 0 0
0
1 0 1 0
26
0
0 0 0 0
27
Programmable Arrays
ROM (read only memories) PLA (programmable logic array) PAL (programmable array logic) CPLD (complex programmable logic devices) FPGA (field programmable gate arrays)
28
A ROM consists of a two dimensional array of semiconductor devices interconnected to store an array of binary data Two-level canonical form combinational logic can be implemented using a ROM as a look-up-table (LUT)
B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 F3 0 0 0 1 1 0 1 0 F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C'
A 0 0 0 0 1 1 1 1
truth table
29
30
ROM Structure
2n words
31
A PLA performs the same basic LUT task as a ROM. A PLA with n inputs and m outputs can realize m combinational functions of n variables. The internal organization of a PLA is different from that of the ROM
32
PLA (contd)
33
34
Activity
A B C
35
Activity (contd)
Manipulating logic functions so that they can use available resources is called Technology Mapping
A B C ABC ABC
AC
AB AB BC
observe that AB = ABC + ABC can rewrite W to reuse terms: W = ABC + ABC + AC W = ABC + ABC + AC X = ABC + AB + AB Y = ABC + BC + BC
W X Y
Now it fits
BC
36
The PAL is a special case of the PLA in which the AND array is programmable and the OR array is fixed
37
38
CPLDs contain a matrix of logic macrocells that usually consist of programmable array logic followed by a flip-flop or latch. The macrocells are connected using a single large programmable interconnect block
FPGAs contain a regular structure of programmable basic logic cells surrounded by programmable interconnect.
39
40
41