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    PCB Lab Manual

    Uploaded by

    trivedi_urvi9087
    The document describes several experiments conducted to analyze various circuit configurations including a 5V regulated power supply, Zener diode characteristics, CE amplifier characteristics, CE transistor input and output characteristics, and different clipping circuit configurations. For each experiment, the circuit diagram, analysis setup, output waveforms and conclusions are presented. PCB layout designs are also included for the different clipping circuit configurations studied.

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    PCB Lab Manual

    Uploaded by

    trivedi_urvi9087
    601 views16 pages
    The document describes several experiments conducted to analyze various circuit configurations including a 5V regulated power supply, Zener diode characteristics, CE amplifier characteristics, CE transistor input and output characteristics, and different clipping circuit configurations. For each experiment, the circuit diagram, analysis setup, output waveforms and conclusions are presented. PCB layout designs are also included for the different clipping circuit configurations studied.

    Original Description:

    Lab manual for PCB design using circuitmaker and trax maker

    Original Title

    Pcb Lab Manual

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    © Attribution Non-Commercial (BY-NC)

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    The document describes several experiments conducted to analyze various circuit configurations including a 5V regulated power supply, Zener diode characteristics, CE amplifier characteristics, CE transistor input and output characteristics, and different clipping circuit configurations. For each experiment, the circuit diagram, analysis setup, output waveforms and conclusions are presented. PCB layout designs are also included for the different clipping circuit configurations studied.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    601 views16 pages

    PCB Lab Manual

    Uploaded by

    trivedi_urvi9087
    The document describes several experiments conducted to analyze various circuit configurations including a 5V regulated power supply, Zener diode characteristics, CE amplifier characteristics, CE transistor input and output characteristics, and different clipping circuit configurations. For each experiment, the circuit diagram, analysis setup, output waveforms and conclusions are presented. PCB layout designs are also included for the different clipping circuit configurations studied.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
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    Download as doc, pdf, or txt
    of 16

    EC Department

    DATE:

    EXPERIMENT NO. AIM: Create PCB layout for 5V regulated power supply.

    CIRCUIT DIAGRAM :
    U1 78L05
    IN OUT COM

    R1 1k

    C1 1uF V1 -12/12V 50 Hz

    C3 1uF

    C4 1uF

    C2 1uF D2 LED1

    D1 18DB05

    ANALYSIS SETUP:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    OUTPUT WAVEFORM/OUTPUT CHARACTERISTICS:

    A: c2_2

    6.000 V

    5.000 V

    4.000 V

    3.000 V

    2.000 V

    1.000 V

    0.000 V 0.000 s

    0.500 s

    1.000 s

    1.500 s

    2.000 s

    2.500 s

    3.000 s

    3.500 s

    4.000 s

    4.500 s

    5.000 s

    PCB LAYOUT:

    Top overlay:

    Bottom layer:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    EXPERIMENT NO. 2 AIM: . Obtain Zener diode characteristics using circuit maker

    CIRCUIT DIAGRAM :
    D1 1N4756 A

    + V1 10V

    R1 1k

    ANALYSIS SETUP:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    OUTPUT WAVEFORM/OUTPUT CHARACTERISTICS:

    CONCLUSION:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    EXPERIMENT NO.3 AIM: . Obtain the characteristic of CE amplifier using circuit maker

    CIRCUIT DIAGRAM :

    V1 11V +V

    R1 6.6k V2 -25m/25mV C2 10uF

    R3 740

    C3 1uF B

    Q1 2N3700 R4 540 C1 10uF R5 10k

    5kHz R2 4k

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    ANALYSIS SETUP:

    OUTPUT WAVEFORM:
    A: r1_1 B: c3_1 5.000 V 4.000 V

    3.000 V

    2.000 V

    1.000 V

    0.000 V

    -1.000 V

    -2.000 V

    -3.000 V

    -4.000 V

    -5.000 V 0.000ms

    0.500ms

    1.000ms

    1.500ms

    2.000ms

    2.500ms

    3.000ms

    CONCLUSION:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    AIM: CE DC CIRCUIT DIAGRAM :

    Rc 10

    Rb 100

    Q1 2N2369 + Vc 10V

    + Vb 10V

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    ANALYSIS SETUP: Input

    INPUT CHARACTERISTICS:
    A: q1[ib] 200.0mA

    150.0mA

    100.0mA

    50.00mA

    0.000mA

    -50.00mA 0.000 V

    2.500 V

    5.000 V

    7.500 V

    10.00 V

    12.50 V

    15.00 V

    17.50 V

    20.00 V

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    ANALYSIS SETUP: OUTPUT

    OUTPUTWAVE FORM/OUTPUT CHARACTERISTICCS

    A: q1[ic]

    4.500 A

    3.500 A

    2.500 A

    1.500 A

    0.500 A

    -0.500 A 0.000 V

    5.000 V

    10.00 V

    15.00 V

    20.00 V

    25.00 V

    30.00 V

    35.00 V

    40.00 V

    45.00 V

    50.00 V

    CONCLUSION:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    EC Department

    DATE:

    EXPERIMENT NO. 8 AIM: Create PCB layout for all types of clamping circuits:

    CIRCUIT DIAGRAM:

    1. Positive shunt biased clipper

    R2 1k

    B D1 DIODE

    V2 -240/240V

    1kHz

    + V1 10V

    ANALYSIS SETUP:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    10

    EC Department

    DATE:

    OUTPUT WAVEFORM:
    A: v2_1 B: d1_a 250.0 V

    150.0 V

    50.00 V

    -50.00 V

    -150.0 V

    -250.0 V 0.000ms

    0.500ms

    1.000ms

    1.500ms

    2.000ms

    2.500ms

    3.000ms

    3.500ms

    4.000ms

    4.500ms

    5.000ms

    CIRCUIT DIAGRAM :

    2. Negative Series biased clipper

    D1 A DIODE V1 -240/240V

    R1 1k + V2 10V

    5kHz

    OUTPUT WAVEFORM
    A: v1_1 B: r1_2 250.0 V 150.0 V

    50.00 V

    -50.00 V

    -150.0 V

    -250.0 V 0.000ms

    0.100ms

    0.200ms

    0.300ms

    0.400ms

    0.500ms

    0.600ms

    0.700ms

    0.800ms

    0.900ms

    1.000ms

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    11

    EC Department

    DATE:

    CIRCUIT DIAGRAM :

    3. Negative Shunt Biased Clipper

    A V1 -20/20V

    R1 1k

    D1 DIODE

    1kHz +

    V2 10V

    OUTPUT WAVEFORM/OUTPUT CHARACTERISTICS:

    A: v1_1 B: r1_2

    20.00 V 15.00 V 10.00 V 5.000 V 0.000 V -5.000 V -10.00 V -15.00 V -20.00 V 0.000ms

    0.500ms

    1.000ms

    1.500ms

    2.000ms

    2.500ms

    3.000ms

    3.500ms

    4.000ms

    4.500ms

    5.000ms

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    12

    EC Department

    DATE:

    CIRCUIT DIAGRAM :

    4. Positive Series Biased Clipper

    A V1 -20/20V

    D1 DIODE

    R1 1k 1kHz + V2 10V

    OUTPUT WAVEFORM:

    A: v1_1 B: d1_a

    20.00 V 15.00 V 10.00 V 5.000 V 0.000 V -5.000 V -10.00 V -15.00 V -20.00 V 0.000ms

    0.500ms

    1.000ms

    1.500ms

    2.000ms

    2.500ms

    3.000ms

    3.500ms

    4.000ms

    4.500ms

    5.000ms

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    13

    EC Department

    DATE:

    CIRCUIT DIAGRAM :

    5. Combine Clipper
    R1 A 1k V1 -6/6V

    D1 DIODE

    D2 DIODE

    2kHz + V2 2V V3 2V

    OUTPUT WAVEFORM:

    A: v1_1 B: r1_2

    7.500 V

    5.000 V

    2.500 V

    0.000 V

    -2.500 V

    -5.000 V

    -7.500 V 0.000ms

    0.250ms

    0.500ms

    0.750ms

    1.000ms

    1.250ms

    1.500ms

    1.750ms

    2.000ms

    2.250ms

    2.500ms

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    14

    EC Department

    DATE:

    PCB LAYOUT:

    1. Positive Series biased clipper

    2. Positive shunt biased clipper

    3. Negative series biased clipper

    4. Negative shunt biased clipper

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    15

    EC Department

    DATE:

    5. Combined clipper

    Top overlay:

    Bottom layer:

    GOVERNMENT GIRLS POLYTECHNIC, SURAT

    16

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