16 BIT KOGGE-STONE TREE ADDER

Shayan Kazemkhani Nghia Do Jia Kang Yu Toan Luong

Advisor: David Parent May 8th 2006

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Agenda
Abstract Introduction
Why Tree Adder? Theory

Project Details Summary of Results Lessons Learned Cost Analysis Conclusion

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Abstract
We designed 16 bit Kogge-Stone Tree Adder - the most commonly used parallel prefix carry-lookahead adder topology. 200MHz clock frequency Area 1000*600 um^2 Power density AMI06 Technology

Introduction
Why? - minimum logic depth, wide wiring channels, regular structure and large fanout points. Prefix Adder Structure
A4 B4 A3 B3 A2 B2 A1 B1 Cin

1: Bitwise PG logic G4 P4 G3 P3 G2 P2 G1 P1 G0 P0

2: Group PG logic G3:0 C3 G2:0 C2 G1:0 C1 G0:0 C0 3: Sum logic

C4 Cout S4 S3 S2 S1

PROJECT DETAILS
17 pin outs
33 input D-flip flops and 17 output D-flip flops

Create schematic and layout for 16 bit tree adder

Test schematic using test bench

Run DRC and LVS to verify the design

BLOCK DIAGRAM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 14:13 13:12 12:11 11:10 10:9

9:8

8:7

7:6

6:5

5:4

4:3

3:2

2:1

1:0

15:12 14:11 13:10

12:9

11:8 10:7

9:6

8:5

7:4

6:3

5:2

4:1

3:0

2:0

15:8

14:7

13:6

12:5

11:4 10:3

9:2

8:1

7:0

6:0

5:0

4:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
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Longest path calculation

Tphl = 5ns/(14+3) = .29ns

Table of actual Wn & Wp

Schematic

Layout

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DRC Report

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Extraction report

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LVS Report

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Cost Analysis
Estimate amount of time spent on project: - Verifying NC Verilog 5 hrs - Verifying Timing 10 hrs - Layout 40 hrs - Post Extracted Timing 10 hrs

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Lessons Learned
Start early Work in group Study previous projects Seek advice from Dr. Parent and previous students Save time for debugging error
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Conclusions
We designed and implemented a 16 bit Kogge-Stone Tree Adder that operates at 200MHz in an area of 1000*600 um^2

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Acknowledgements
Thanks to Cadence Design Systems for the VLSI lab Thanks to Dr. David Parent Thanks to all 166, 167, and 224 students

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