VLSI DESIGN AND TECHNOLOGY TITLE: Modeling of Basic Gates BATCH : Cy/C4 ROLL NO : 17

TUTORIAL -1 DATE: 5/1/2012

AIM: Modeling of Basic Gates and Verify on ESDK kit 1) AND GATE:
VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity and1 is port (a,b : in std_logic ; c : out std_logic); end and1; architecture and11 of and1 is begin c <= a and b; end and11;

COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 2) OR GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity or21 is port (a,b : in std_logic ; c : out std_logic); end or21; architecture test of or21 is begin c <= a or b; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 3) NOT GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity not11 is port (a: in std_logic ; c : out std_logic); end not11; architecture test of not11 is begin c <= not a; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 4) NAND GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity nand21 is port (a,b : in std_logic ; c : out std_logic); end nand21; architecture test of nand21 is begin c <= a nand b; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 5) NOR GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity nor21 is port (a,b : in std_logic ; c : out std_logic); end nor21; architecture test of nor21 is begin c <= a nor b; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 6) XOR GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity xor12 is port (a,b : in std_logic ; c : out std_logic); end xor12; architecture test of xor12 is begin c <= a xor b; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY 7) XNOR GATE:

VHDL PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity xnor21 is port (a,b : in std_logic ; c : out std_logic); end xnor21; architecture test of xnor21 is begin c <= a xnor b; end test;

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COMPILATION REPORT:

VECTOR WAVEFORM:

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VLSI DESIGN AND TECHNOLOGY

TUTORIAL -1

Conclusion:

Grade

Lab-In-Charge

H.O.D.

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