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  • LISTL1SL2SCC1

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    Vishal Mehta
    14 views22 pages
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    ANAGRAM

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    14 views22 pages

    LISTL1SL2SCC1

    Uploaded by

    Vishal Mehta
    ANAGRAM

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as txt, pdf, or txt
    of 22

    sim: command line: .

    /sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32


    :1:l -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32


    :1:l -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:l -cache:il1 il1:2048:32
    :1:l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32


    :1:f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:f -cache:il1 il1:2048:32
    :1:f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1 il1:2048:32
    :1:r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1


    :1:r -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:2048:32:1:r -cache:il1
    :1:r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    il1:2048:32
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    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1


    :1:l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:l -cache:il1
    :1:l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:f -cache:il1
    :1:f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1
    :1:r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1
    :1:r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1
    :1:r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1
    :1:r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    il1:1024:64
    none -tlb:d
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    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64


    :1:r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:64:1:r -cache:il1 il1:1024:64
    :1:r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32


    :2:l -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:l -cache:il1 il1:1024:32
    :2:l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32


    :2:f -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:f -cache:il1 il1:1024:32
    :2:f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1 il1:1024:32
    :2:r -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1 il1:1024:32
    :2:r -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1 il1:1024:32
    :2:r -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb
    :dtlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1 il1:1024:32
    :2:r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1


    :2:r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:1024:32:2:r -cache:il1
    :2:r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
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    il1:1024:32
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    il1:1024:32
    none -tlb:d
    il1:1024:32
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    il1:1024:32
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    il1:1024:32
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    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
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    il1:1024:32
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    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d
    il1:1024:32
    none -tlb:d

    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l


    :l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:l
    :l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f
    :f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
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    -cache:il1 il1:512:64:2
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    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:64:2
    -tlb:itlb none -tlb:dtl

    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f -cache:il1 il1:512:64:2


    :f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f -cache:il1 il1:512:64:2
    :f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f -cache:il1 il1:512:64:2
    :f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:f -cache:il1 il1:512:64:2
    :f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:64:2:r -cache:il1 il1:512:64:2
    :r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l -cache:il1 il1:512:32:4
    :l -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l -cache:il1 il1:512:32:4
    :l -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l -cache:il1 il1:512:32:4
    :l -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l -cache:il1 il1:512:32:4
    :l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l


    :l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:l
    :l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:512:32:4
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:32:4
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    -cache:il1 il1:512:32:4
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    -cache:il1 il1:512:32:4
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    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:512:32:4
    -tlb:itlb none -tlb:dtl

    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4


    :f -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4


    :f -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:f -cache:il1 il1:512:32:4
    :f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r -cache:il1 il1:512:32:4
    :r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r


    :r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:512:32:4:r
    :r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:l
    :l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:512:32:4
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    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f


    :f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:f
    :f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r
    :r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:256:64:4
    -tlb:itlb none -tlb:dtl
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    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r -cache:il1 il1:256:64:4


    :r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r -cache:il1 il1:256:64:4
    :r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r -cache:il1 il1:256:64:4
    :r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:64:4:r -cache:il1 il1:256:64:4
    :r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8


    :l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:l -cache:il1 il1:256:32:8
    :l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8


    :f -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:f -cache:il1 il1:256:32:8
    :f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:16384:32:1:l -cache:il2 il2:16384:32:1:l -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:16384:32:1:f -cache:il2 il2:16384:32:1:f -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:16384:32:1:r -cache:il2 il2:16384:32:1:r -tlb:itlb none -tlb:d
    tlb none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:8192:32:2:l -cache:il2 il2:8192:32:2:l -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r -cache:il1 il1:256:32:8
    :r -cache:dl2 dl2:8192:32:2:f -cache:il2 il2:8192:32:2:f -tlb:itlb none -tlb:dtl
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r


    :r -cache:dl2 dl2:8192:32:2:r -cache:il2 il2:8192:32:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:32:4:l -cache:il2 il2:4096:32:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:32:4:f -cache:il2 il2:4096:32:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:4096:32:4:r -cache:il2 il2:4096:32:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:32:8:l -cache:il2 il2:2048:32:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:32:8:f -cache:il2 il2:2048:32:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:2048:32:8:r -cache:il2 il2:2048:32:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:256:32:8:r
    :r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:256:32:8
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    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l


    :l -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:l
    :l -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:f
    :f -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:128:64:8
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    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl

    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r


    :r -cache:dl2 dl2:8192:64:1:l -cache:il2 il2:8192:64:1:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:8192:64:1:f -cache:il2 il2:8192:64:1:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:8192:64:1:r -cache:il2 il2:8192:64:1:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:4096:64:2:l -cache:il2 il2:4096:64:2:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:4096:64:2:f -cache:il2 il2:4096:64:2:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:4096:64:2:r -cache:il2 il2:4096:64:2:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:2048:64:4:l -cache:il2 il2:2048:64:4:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:2048:64:4:f -cache:il2 il2:2048:64:4:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:2048:64:4:r -cache:il2 il2:2048:64:4:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:1024:64:8:l -cache:il2 il2:1024:64:8:l
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:1024:64:8:f -cache:il2 il2:1024:64:8:f
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i
    sim: command line: ./sim-cache -cache:dl1 dl1:128:64:8:r
    :r -cache:dl2 dl2:1024:64:8:r -cache:il2 il2:1024:64:8:r
    b none ./benchmarks/cc1.alpha -O ./benchmarks/1stmt.i

    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl
    -cache:il1 il1:128:64:8
    -tlb:itlb none -tlb:dtl

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