R.

Lauwereins Imec 2001

Karnaugh map
v w zw xy 00 y 01 z 00 01 11 0 4 1 5 3 7 10 2 6 14 10 10 18 22 30 26 z xy 19 17 16 00 23 21 20 01 31 29 28 11 27 25 24 10 y 11 01 00 w

Digital design Combinatorial circuits Sequential circuits FSMD design

VHDL

11

12 13 15 8 9 11

10

F(v,x,y,z,w) Differs from course book

2/1

 R.Lauwereins Imec 2001

Karnaugh map
Differs from course book w zw xy 00 z 00 01 11 0 4 1 5 3 7 10 2 6 10 18 22 z xy 19 17 16 00 23 21 20 01 x y 11 01 00 v w

Digital design Combinatorial circuits Sequential circuits FSMD design

01
y x 11 10

12 13 15 14
8 9 11 10

30 31 29 28 11
26 27 25 24 10

VHDL

F=(u,v,x,y,z,w) x 10 11 01 40 41 43 44 45 47 36 37 39 42 46 38 58 62 54 59 57 56 10 63 61 60 11 55 53 52 01 x

2/2

00

32 33 35 34

50 51 49 48 00

 R.Lauwereins Imec 2001

Dont care conditions

Incompletely specified Boolean function
x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 w 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a 1 0 1 1 0 1 1 1 1 1 x x x x x x b 1 1 1 1 1 0 0 1 1 1 x x x x x x c 1 1 0 1 1 1 1 1 1 1 x x x x x x d 1 0 1 1 0 1 1 0 1 1 x x x x x x e 1 0 1 0 0 0 1 0 1 0 x x x x x x f 1 0 0 0 1 1 1 0 1 1 x x x x x x g 0 0 1 1 1 1 1 0 1 1 x x x x x x

Digital design Combinatorial circuits Sequential circuits FSMD design

BCD7-segment a f e d g b c

VHDL

2/3

 R.Lauwereins Imec 2001

Dont care conditions

Step 2: determine all prime implicants
w a z
1 0 1 1 0 1 1 1

Digital design Combinatorial circuits Sequential circuits FSMD design

w b z
1 1 1 1 1 0 1 0 x x x x 1 1 x x

w c z
1 1 1 0 1 1 1 1 x x x x 1 1 x x

w d z
1 0 1 1 0 1 0 1 x x x x 1 1 x x

x x x x 1 1 x x

e
1 0 0 1

f
1 0 0 0 1 1 0 1

g
0 0 1 1 1 1 0 1

VHDL

y x

0 0 0 1

x x x x
1 0 x x

x x x x
1 1 x x

x x x x
1 1 x x

2/4

 R.Lauwereins Imec 2001

Dont care conditions

Step 3: Determine all essential prime implicants
w a z
1 0 1 1 0 1 1 1

Digital design Combinatorial circuits Sequential circuits FSMD design

w b z
1 1 1 1 1 0 1 0

w c z
1 1 1 0 1 1 1 1

w d z
1 0 1 1 0 1 0 1

x x x x
1 1 x x Complete coverage

x x x x
1 1 x x Complete coverage

x x x x
1 1 x x Complete coverage

x x x x
1 1 x x Complete coverage

VHDL

e
1 0 0 1

f
1 0 0 0
1 1 0 1 x x x x 1 1 x x Complete coverage

g
0 0 1 1
1 1 0 1 x x x x 1 1 x x Incomplete coverage

y x

0 0 0 1 x x x x 1 0 x x Complete coverage

2/5

 R.Lauwereins Imec 2001

Dont care conditions

Note down the standard form
yw z yw x y zw zw z w y yz yzw zw yz yw

Digital design Combinatorial circuits Sequential circuits FSMD design

g
0 0 1 1 1 1 0 1

x x x x
1 1 x x

VHDL

2/6

a=yw+z+yw+x b=y+zw+zw c=z+w+y d=yw+yz+yzw+zw+x e=yw+zw f=zw+yz+yw+x g=yz+yz+yw+x

 R.Lauwereins Imec 2001

Dont care conditions

xyzw

Digital design Combinatorial circuits Sequential circuits FSMD design

VHDL

a
2/7

 R.Lauwereins Imec 2001

Technology Mapping: Gate Arrays

Conversion rules (based on the laws of De Morgan):

Digital design Combinatorial circuits Sequential circuits FSMD design

(xy) = (x + y)

(x+y) = (xy)

VHDL

Optimisation rule:
(x) = x

2/8

 R.Lauwereins Imec 2001

Technology Mapping: Gate Arrays

Realisation of an invertor:

Digital design Combinatorial circuits Sequential circuits FSMD design

VHDL

2/9

 R.Lauwereins Imec 2001

Technology Mapping: Gate Arrays

Decomposition:

Digital design Combinatorial circuits Sequential circuits FSMD design

VHDL

2/10

 R.Lauwereins Imec 2001

Ripple-carry adders
Half adder
xi 0 0 1 1 yi 0 1 0 1 ci+1 0 0 0 1 si 0 1 1 0

Digital design Combinatorial circuits Sequential circuits FSMD design

ci+1 0

yi 0 1

si 0

yi 1 0

xi

xi

VHDL

xi

yi
ci+1

xi

yi

HA

ci+1
2/11

si

si

1 CLB

 R.Lauwereins Imec 2001

Ripple-carry adders
Full adder
xi 0 0 0 0 1 1 1 1 yi 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 ci+1 0 0 0 1 0 1 1 1 si 0 1 1 0 1 0 0 1

Digital design Combinatorial circuits Sequential circuits FSMD design

yi ci+1 1 ci 1 1 1 ci 1 xi si

yi xi 1 1 1

VHDL

xi yi ci

1 CLB
2/12

ci+1

si

 R.Lauwereins Imec 2001

Ripple-carry adders
Full adder: alternative implementation
xi 0 0 0 0 1 1 1 1 yi 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 ci+1 0 0 0 1 0 1 1 1 si 0 1 1 0 1 0 0 1

Digital design Combinatorial circuits Sequential circuits FSMD design

yi ci+1 1 ci xi yi ci 1 1 1 ci 1 xi si

yi xi 1 1 1

VHDL

1 gate less, larger delay from xi&yi to ci+1, same delay from ci to ci+1 xi yi ci+1 FA si ci ci+1 si

2/13

 R.Lauwereins Imec 2001

Ripple-carry adders
4-bit ripple-carry adder
x3 c4 FA s3 y3 c3 x2 FA s2 y2 c2 x1 FA s1 y1 c1 x0 FA s0 y0 c0=0

Digital design Combinatorial circuits Sequential circuits FSMD design

VHDL

Critical path: x0 or y0 to c4: 1 XOR + 4 AND + 4 OR

In principal 1 CLB per bit Because of special circuitry (dedicated carry chain): 1 CLB per 2 bits
2/14

 R.Lauwereins Imec 2001

Adder-subtractors
X Y S
S 0 1 Function X+Y X-Y=X+Y*=X+Y+1 Note Addition Subtraction

Digital design Combinatorial circuits Sequential circuits FSMD design

Cout

Adder/ subtractor F

x3 S

y3

x2

y2

x1

y1

x0

y0

VHDL

c4

FA

c3

FA

c2

FA

c1

FA

c0

f3
overflow

f2

f1

f0

2/15

Only for 2-complement!!!

 R.Lauwereins Imec 2001

Decoders
E 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 C3 0 0 0 0 0 0 0 1 C2 0 0 0 0 0 0 1 0 C1 0 0 0 0 0 1 0 0 C0 0 0 0 0 1 0 0 0

Digital design Combinatorial circuits Sequential circuits FSMD design

E A1 A0

C3

C2

C1

C0

VHDL

A1..0 E Decoder 2 CLB

C3..0
2/16

 R.Lauwereins Imec 2001

Selectors
S1 0 0 1 1 S0 0 1 0 1 Y D0 D1 D2 D3

Digital design Combinatorial circuits Sequential circuits FSMD design

D3

D2

D1

D0 S1 S0

VHDL

D3..0
In principle: 2-to-1 MUX is 1/2 CLB Due to special provisions: 4-to-1 MUX is 1 CLB

S1..0

4-to-1 MUX Y

2/17

 R.Lauwereins Imec 2001

Selectors
D3 D2 D1 D0
S1 0 0 1 1 S0 0 1 0 1 Y D0 D1 D2 D3

Digital design Combinatorial circuits Sequential circuits FSMD design

Decoder

S1 S0

Y Alternative implementation

VHDL

2/18

 R.Lauwereins Imec 2001

Selectors
D15..12 S1..0 S1..0 D11..8 S1..0 D7..4 S1..0 D3..0

Digital design Combinatorial circuits Sequential circuits FSMD design

4-to-1 selector

4-to-1 selector

4-to-1 selector

4-to-1 selector

VHDL

S3..2

4-to-1 selector Y

2/19

 R.Lauwereins Imec 2001

Buses
Problem with high fan-in MUX:
fan-in OR gate too big all inputs have to be routed to 1 central location: substantial routing delay and difficult routing

Digital design Combinatorial circuits Sequential circuits FSMD design

Solution: bus with tristate drivers

D3 D2 D1 D0 S1 S0
E 0 1 Y Z D

VHDL

Decoder

2/20

 R.Lauwereins Imec 2001

Magnitude comparators
x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 y1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 x x0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y y0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 G G (X>Y) (X>Y) 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 L L (X<Y) (X<Y) 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

Digital design Combinatorial circuits Sequential circuits FSMD design

y0

x0 1

y1

x1

1 1 1 1 1 y0

x0

VHDL

y1

x1

1 1 1 1 1 1

2/21