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VLSI Design Styles
VLSI Design Styles
System Specifications
Manual
Automation
Chip
Physical Design
Converts a circuit description into a geometric description.
This description is used for fabrication of the chip. 1. 2. 3. 4. Partitioning Floorplanning and placement Routing Compaction
n-channel Transistor
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Fabrication Layers
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12
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VLSI Fabrication
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Silicon Wafer
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16
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Poly-Diffusion Interaction
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Contacts
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Contact Spacing
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M2 Contact (Via)
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Stick Diagrams
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Introduction
User / Field Programmability. Array of logic cells connected via routing channels. Different types of cells:
Special I/O cells. Logic cells.
Mainly lookup tables (LUT) with associated registers.
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Switch Matrix
D Q Output Buffer Pad
CLB
CLB
Q D Delay
Input Buffer
Programmable Interconnect
C1 C2 C3 C4 H1 DIN S/R EC
S/R Control
G4 G3 G2 G1
SD D Q
EC RD
F4 F3 F2 F1
SD D Q
1 H' F'
EC RD
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G4 G3 G2 G1
DIN
SD D Q
YQ
EC RD
1 G' H' S/R Control
F4 F3 F2 F1
SD D Q
XQ
EC RD
1 H' F'
K
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CLB Functionalities
Two 4-input function generators
Implemented using Lookup Tables using 16x1 RAM. Can also implement 16x1 memory.
Two Registers
Each can be configured as flip-flop or latch. Independent clock polarity. Synchronous and asynchronous Set / Reset.
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Look Up Tables
Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table Example: 4-bit address
Combinatorial Logic A B C D Z A B C D 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Z 0 0 0 1 1 1 0 0 0 1
WE G4 G3 G2 G1