FPGA Implementation of AES Algorithm

AIM: The main aim of the project is to design and implement FPGA Implementation of AES Algorithm. ABSTRACT: The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable ate Arrays !FP As" offer a #uic$er% more customi&able solution. This research investigates the AES algorithm with regard to FP A and the 'ery High Speed (ntegrated )ircuit Hardware *escription language !'H*+". Software is used for simulation and optimi&ation of the synthesi&able 'H*+ code. All the transformations of both Encryptions and *ecryption are simulated using an iterative design approach in order to minimi&e the hardware consumption.

V.Mallikarjuna (Project manager)

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

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Fig, AES Encryption Process.

V.Mallikarjuna (Project manager)

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Fig, AES *ecryption Process

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-ilin. /.0(SE% 1odelsim 2.3c. APPLICATI # A"$A#TAGES: All the transformations of algorithm are simulated using an iterative design approach in order to minimi&e the hardware consumption.4 The throughput reaches the value of 5601bit7sec for both encryption and decryption process. REFERE#CES:

V.Mallikarjuna (Project manager)

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

 1ar$o 1ali% Franc 8ova$ and Anton 9iasi&&o :Hardware (mplementation of AES Algorithm; <=ournal of E+E)T>()A+ E8 (8EE>(8 % 'ol. 62% 8o. /?@A% 026?02/. 9ehrou& A. Forou&an and *ebdeep 1u$hopadhyay :)ryptography and 8etwor$ Security; !0nd edition". F(PS @/B% :Advanced Encryption Standard !AES";% 8ovember 02. +.Thulasimani%;A Single )hip *esign and (mplementation of AES ?@0C7@/07062 Encryption Algorithms;? (nternational =ournal of Engineering Science and Technology% 'ol. 0!6"% @A60?@A6/. 8ation (nstitute of Standards and Technology !8(ST"% *ata Encryption Standard !*ES"% 8ational Technical (nformation Service% Sprinfgield% 'A 00@2.

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &