Design of 8-bit microprocessor using Verilog (SAP-1 architecture)

Computer Architecture & Design Lab Assignment

Submitted by Abhishe Dutta ! "#1bct$"1 %ibe Shrestha ! "#1bct$"&

Date - 'a( ))* )""+

,itle
Design a 8-bit microprocessor using Verilog an- .erif( it/s operations0 1se SAP-1 (Simple As Possible) architecture as (our reference0

2ntro-uction
,he Simple-As-Possible (SAP)-1 computer is a .er( basic mo-el of a microprocessor e3plaine- b( Albert Paul 'al.ino1. ,he SAP-1 -esign contains the basic necessities 4or s* interacts 4ith memor( an- other parts of the s(stem li e instruction set is .er( limite- an- is simple0 ,he features in SAP-1 computer are

for a

functional

'icroprocessor0 2ts primar( purpose is to -e.elop a basic un-erstan-ing of ho4 a microprocessor input an- output0 ,he

5 bus - A single 8 bit bus for a--ress an- -ata transfer0 1# %(tes memor( (6A') 6egisters are accumulator an- %-register each of 8 bits0 Program counter ! initiali7es from ""8("-) to 998(1$-) -uring program e3ecution0 'emor( A--ress 6egister ('A6) to store memor( a--resses0 A--er:Subtracter for a--ition an- subtraction instructions0 A Control 1nit A Simple ;utput0 # machine reser.e- for each instruction

,he instruction format of SAP-1 Computer is (<<<<) (<<<<) the first four bits ma e the opco-e 4hile the last four bits ma e the operan-(a--ress)0

1 Albert Paul 'al.ino* Ph0 D0 intro-uce- the concept of SAP (Simple As Possible) computers in his boo =Digital Computer >lectronics ! An 2ntro-uction to 'icrocomputers? - )n- >-ition0

SAP-1 instruction set consists of follo4ing instructions 'nemonic LDA ADD S1% ;1, 8L, ;peration Loa- a--resse- memor( contents into accumulator A-- a--resse- memor( contents to accumulator Subtract a--resse- memor( contents from accumulator Loa- accumulator -ata into output register Stop processing ;PC;D> """" """1 ""1" 111" 1111

>3ample@ if """" 1""" is store- at memor( location """" of 6A' then SAP1 computer interprets it as follo4s@

'achine c(cle an- 2nstruction c(cle

SAP1 has si3 ,-states (three fetch an- three e3ecute c(cles) reser.e- for each instruction0 Aot all instructions reBuire all the si3 ,-states for e3ecution0 ,he unuse- ,;peration (A;P) c(cle0 >ach ,-state is calle- a machine c(cle for SAP10 A ring counter is use- to generate e.er( falling e-ge of cloc pulse0 ,he ring counter output is reset after the #th 9>,C8 CCCL> ! ,1* ,)* ,D machine c(cle ,E* ,$* ,# machine c(cle ,-state0 a ,-state at state is mar e- as Ao

><>C1,> CCCL> -

Architecture
10 Program Counter (PC)

implemente- in =pc0.? file 2t counts from """" to 1111 an- it signals the memor( a--ress of ne3t instruction to be fetche- an- e3ecute-

)0 2nput an- 'A6 ('A6)

implemente- in =input'A60.? file During a computer run* the a--ress in PC is latche- into 'emor( A--ress 6egister ('A6)0

D0 6A'

implemente- in =mem1# 0.? file the program co-e to be e3ecute- an- -ata for SAP1 computer is store- here0 During a computer run* the 6A' recei.es E-bit a--resses from 'A6 an- a reaoperation is performe-0 8ence* the instruction or -ata 4or- store- in 6A' is place- on the 5 bus for use b( some other part of the computer0 2t is as(nchronous 6A'* 4hich means that the output -ata is a.ailable as soon as .alia--ress an- control signal are applie-

E0 2nstruction 6egister (26)

implemente- in =ir0.? file 26 contains the instruction (compose- of ;PC;D>FADD6>SS) to be e3ecute- b( SAP1 computer0

$0 Controller- SeBuencer

implemente- in =cu0.? file it generates the control signals for each bloc so that actions occur in -esire- seBuence0 CLG signal is use- to s(nchroni7e the o.erall operation of the SAP1 computer0 A 1) bit 4or- comes out of the Controller-SeBuencer bloc 0 ,his control 4or-etermines ho4 the registers 4ill react to the ne3t positi.e CLG e-ge0

#0 Accumulator

implemente- in =accumulator0.? file it is a 8 bit buffer register that stores interme-iate results -uring a computer run0 2t is al4a(s one of the operan-s of ADD*S1% an- ;1, instructions0

+0 A--er-Subtracter

implemente- in =a--ersubtracter0.? file it is a )/s complement a--er-subtractor this mo-ule is as(nchronous (uncloc e-)* 4hich means that its contents can change as soon as the input 4or-s change

80 % 6egister

implemente- in =register0.? file it is 8 bit buffer register 4hich is primaril( use- to hol- the other operan- (one operanis al4a(s accumulator) of mathematical operations0

&0 ;utput 6egister

this registers hol- the output of ;1, instruction0

1"0 %inar( Displa(

it is a ro4 of eight L>Ds to sho4 the contents of output register0

Discussion
,he -esign of mo-ules li e Program Counter* 2nput an- 'A6* 6A'* 2nstruction 6egister* Accumulator* A--er-Subtracter* % register* ;utput register 4as eas( as similar -esigns 4ere alrea-( -one in Lab assignments0 ,he most complicate- part 4as the -esign of Controller:SeBuencer(C:S)0 ,he first problem 4e face- arose -ue to failure to un-erstan- about the settling times for -ata lines0 5e trie- to chec the -ata lines at the instant it change- an- hence 4e got the ol- .alue of the -ata line0 ,his problem 4as resol.e- b( a--ing a 1ms -ela( ( H1I )0 ,he secon- problem 4e face- in -esigning C:S 4as ='a3imum 8DL co-e reache-?0 5e -elete- the co-e for test bench of other mo-ules to -ecrease the si7e of our proJect0 ,his 4as probabl( the limitation of beta .ersion of Silos 4or bench (Silos)""101)") 4hich 4e use- in this proJect for co-ing an- testing of Verilog co-e for SAP1 computer0 ,he tas of s(nchroni7ing each bloc 4as also .er( complicate-0 ,he presence of a share- bus (5%1S) also cause- se.eral complications -uring the -esign0

Conclusion
5e became familiar 4ith the 4or ing of a 8-bit microprocessor an- the 4a( each mo-ule contributes to the o.erall functioning of the computer0 Although the concept of SAP1 is .er( simple* the no4le-ge gaine- 4hile -esigning it can be e3ten-e- to -esign of more comple3 microprocessors0 5e successfull( -esigne- a 8-bit microprocessor base- on SAP1 architecture an- .erifie- it/s operations in Verilog0

6eferences
10 Albert Paul 'al.ino0 Digital Computer Electronics An Introduction to Microcomputers: SAP-1(Page 140 ! ,ata 'cKra4-8ill Publishing Compan( Limite- 1&&" )0 Peter '0 A(asulu0 Introduction to "erilog Lan0 )""$