ASM to VHDL State Machines :

VHDL 1

lc

lb

la

ra rb rc

Provide a sequencer to duplicate the left-turn, right-turn and hazard

indicators for a 1965 Ford Thunderbird.

ASM to VHDL State Machines :

Light sequence for a right turn

Develop an ASM model for the three sequences, left, right and hazard
(both).
Assign state values.
Derive the excitation equations.
Derive the output equations.
Write the VHDL description.
Test your design.
Pocket the cheque.

ASM to VHDL State Machines :

idle
left <= "000"
right <= "000"

0
turn(0)

turn(1)

0
turn(1)
1

both_1

left <= "001"

right <= "001"

left_1

right_1

left <= "001"

right <= "000"

left <= "000"

right <= "001"

ASM to VHDL State Machines :

both_2

left_2

left <= "011"

right <= "011"

both_3

left <= "111"

right <= "111"

right_2

left <= "011"

right <= "000"

left_3

left <= "000"

right <= "011"

right_3

left <= "111"

right <= "000"

left <= "000"

right <= "111"

ASM to VHDL State Machines :

state

value

idle
left <= "000"
right <= "000"

idle
right_1
right_2
right_3
left_1
left_2
left_3
both_1
both_2
both_3

0000
0001
0011
0010
1000
1100
0100
1001
1011
1010

0
turn(0)

turn(1)

0
turn(1)
1

both_1

left_1

left <= "001"

right <= "000"

left <= "001"

right <= "001"

both_2

left_2

left <= "011"

right <= "011"

both_3

left <= "111"

right <= "111"

right_1

left <= "000"

right <= "001"

right_2

left <= "011"

right <= "000"

left_3

left <= "000"

right <= "011"

right_3

left <= "111"

right <= "000"

left <= "000"

right <= "111"

ASM to VHDL State Machines :

Present state
0000
0000
0000
0000
0001
0011
0010
1000
1100
0100
1001
1011
1010

turn
00
01
10
11
XX
XX
XX
XX
XX
XX
XX
XX
XX

5
next state
0000
0001
1000
1001
0011
0010
0000
1100
0100
0000
1011
1010
0000

ASM to VHDL State Machines :

Next, fill in the k-maps.

P3 = 0 , P2 = 0
T1,T0
00

01

P1 00
P0

11

10

00

01

11

10

00

01

11

10

00

00

00

01

01

01

11

11

11

11

10

10

10

10

N3

00

N2

01

01

11

N1

10

11

10

N0

P3 = 0 , P2 = 1
00

01

11

10

00

01

11

10

00

01

11

10

00

00

00

00

00

01

01

01

01

11

11

11

11

10

10

10

10

N3

N2

N1

01

N0

ASM to VHDL State Machines :

P3 = 1 P2 = 0
T1,T0
00

01

11

10

P1 00
P0

00

01

00

01

11

10

00

01

11

10

00

00

00

01

01

01

11

11

11

11

10

10

10

10

N3

N2

01

N1

11

10

N0

P3 = 1, P2 = 1
00
01

00

01

11

10

00

00

01

11

10

00

01

11

10

00

01

01

11

11

11

11

10

10

10

10

N2

01

11

10

00

01

N3

00

N1

N0

ASM to VHDL State Machines :

n3 <= reset and ((not p3 and not p2 and
not p1 and not p0
and turn(1))
or (p3 and not p2 and not p1)
or (p3 and not p2 and p0));
n2 <= reset and (p3 and not p1 and
not p0);
n1 <= reset and (not p2 and p0);
n0 <= reset and ((not p3 and not p2 and
not p1 and turn(0))
or (not p3 and not p2 and not p1
and p0));

ASM to VHDL State Machines :

-- purpose: set current_state_0 new value

update0: block (
((not (clkstable) and clk) = 1)
)
begin

-- block updat0

current_state(0) <= guarded n0;

end block update0;

ASM to VHDL State Machines :