VHDL CODE FOR 4-BIT SISO:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
Din: in STD_LOGIC;
Qout,Qbar:out STD_LOGIC);
end D_FF;
architecture Behavioral of D_FF is
begin
process(clk,reset)
begin
if reset='1'then
Qout<='0';
Qbar<='0';
else if clk'event and clk='1' then
Qout<=Din;
Qbar<=not (Din);
end if;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sso is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
s_in : in STD_LOGIC;
s_out:out STD_LOGIC);
end sso;
architecture Behavioral of sso is

signal d:std_logic_vector(7 downto 0);

component D_FF
port(clk,reset,Din:in std_logic;
Qout,Qbar:out std_logic);
end component;
begin
X1:D_FF port map (clk,reset,s_in,d(0),d(1));
X2:D_FF port map (clk,reset,d(0),d(2),d(3));
X3:D_FF port map (clk,reset,d(2),d(4),d(5));
X4:D_FF port map (clk,reset,d(4),d(6),d(7));
s_out<=d(6);
end Behavioral;