component inv_addroundkey is port ( it : in std_logic_vector (127 downto 0); key : in std_logic_vector (127 downto 0); ot : out std_logic_vector (127

downto 0) ); end component inv_addroundkey;

component inv_shiftrow_subbytes is port ( it : in std_logic_vector (127 downto 0); ot : out std_logic_vector (127 downto 0) ); end component inv_shiftrow_subbytes;

component demux1_2 is port ( i : in std_logic_vector (127 downto 0); s : in std_logic; o1, o2 : out std_logic_vector (127 downto 0) ); end component demux1_2;