UNIVERSITY OF MANAGEMENT AND TECHNOLOGY

School of Engineering
BSEE
EL-320 Digital System Design Lab (Mid Evaluation Quiz)
Date:
Maximum marks: 20
Student ID:
Name:
Note: Attempt All the Questions
Part 1. MCQs

Time: 30 min
Section:

(5)

1) What is the output of the following code at first posedge of clk , if a = 2b01 and b
= 2b11?
(2 marks)
//////////////////////////////////////////////////////////////////////////////////
module write_out(clk,a,b,c);
input clk;
input [1:0] a,b;
output reg [1:0] c;
reg [1:0] r1, r2, r3;
always @ (posedge clk)
begin
r1 <= a & b;
r2 = r1 ^ b;
r3 <= r1 | r2;
c = r3;
end
initial
begin
r1 = 0;
r2 = 0;
r3 = 0;
end
endmodule
////////////////////////////////////////////////
a) 2b00
b) 2b01
c) 2b11
d) 2hX

2) The coding style followed in the above code (See Q1. Part (1)) is known as:
(1 mark)
a)
b)
c)
d)

Gate-level Modeling
Behavioural-level Modeling
Data-flow level Modeling
Both (a) and (c)

3) A mux having n inputs has select lines:

a)
b)
c)
d)

(1 mark)

2n
2n
log2n
n

4) Adding a User Constraints file (.ucf file) to your project in Xilinx is a part of:
(1 mark)
a)
b)
c)
d)

Design Entry
Design Synthesis
Design Implementation
None of the above

Student ID:

Name:
Part 2. Short Questions:

Section:
(15)

1) What are priority encoders?

(2 marks)

2) Write atleast three differences between a function and a task.

marks)

(3

3) Declare a register type array having 32 entries and each entry having 8 bits.
marks)

(2

4) Draw output waveform of the following code:

//////////////////////////////////////////////////////////////////////////////////
module draw_output_waveform;
reg clk;
reg [3:0] A, i;
reg [7:0] adder;
/////////////////////////
always @ (posedge clk)
begin
adder <= adder + A;
end
/////////////////////////
nitial
begin
for (i=0; i<10; i=i+1)

(4 marks)

begin
#100 clk = 0;
#100 clk = 1;
end
end
/////////////////////////
initial
begin
#200 adder = 0;
end
///////////////////////////
initial
begin
#100 A = 10;
#400 A = 5;
end
/////////////////////////
initial
begin
#900 $finish;
end
endmodule

5) Write a verilog code

(4 marks)