cng Vi X L

1. c im cu trc ca BVXL(cng sut, di t, kh nng nh a ch, tc ). Cho B VXL c tn s lm vic 750Mhz, theo kin trc NeuManm, bn trong c thit k 4 ALU v thc hin 1 lnh VXL cn 5 vi lnh vi h s thi gian truy cp b nh l 100 ns. Xc nh tc thc hin lnh ca b VXL. Tr li: 1.1 Nhng c im cu trc ca b VXL: + Cng sut ca b VXL: l kh nng x l d liu .im: di t ca b VXL(data word length), tnh bng s byte. Dung lng nh VL c th nh a ch (addressing capacity). Tc x l lnh ca B VXL (instruction execute speed) * Cng sut my tnh (tc x.l thng tin, kh nng lu tr thng tin, kh nng kt ni nhiu loi thit b ngoi vi, ) ph thuc vo cng sut ca b VXL trong CPU. * di t: Mi b VXL c th x l d liu vi di t c nh. Ph thuc vo tng th h VXL v mc pht trin ca cng ngh VXL, di t c th l 4 bit, 8 bit, 16 bit, 32 bit, 64 bit. Tp lnh ca b VXL thng c cc lnh thc hin theo t v theo byte. Nu 1 t l 2 byte th cng phn bit byte cao v byte thp. Byte thp chim cc bit t 0 n 7, Byte cao chim cc bit t 8 n 15. rng t c di bao nhiu bit th cng c by nhiu bit i vi cc thanh ghi, ALU v bus d liu bn trong b VXL. Bus d liu bn ngoi cng thng c chng di nhng cng c th ch 1 byte trong khi di x l bn trong ca b VXL l 6 bit. di t cng ln cng to ra nhiu kh nng tnh ton ca b VXL, khong biu din s rng hn, tc tnh ton nhanh hn. * Kh nng nh a ch: Cc t d liu v lnh my ct trong BN ti cc ngn nh khc nhau. Mi ngn nh phi c a ch nhn bit. Di nh a ch cng ln th dung lng BN cng nhiu. nh a ch, b VXL thng c thanh ghi a ch. rng ca thanh ghi a ch quyt nh gii a ch ca vng nh vt l m b VXL tha mn. VD: rng ca thanh ghi l 6 bit c th nh c a ch khong nh vt l l 216 = 26 . 210 = 64 KB = 65536 t 8 bit. Vi s m h c s 2 ta c th nh gi ngay c rng ca thanh ghi a ch hay bus a ch. VD: nh c a ch n 32Gb, cn phi c 35 ng dy a ch (A0-A34). Kh nng nh a ch cng ln th cng cho php to ra 1 h thng my tnh c cu hnh mnh vi nhiu loi thit b ngoi vi, b nh chnh c dung lng ln (n vi trm MB) v kh nng x l nhanh. * Tc thc hin lnh: Tc thc hin lnh ca b VXL c th o bng tc thc hin cc lnh du phy ng FLOPS hoc tnh bng triu lnh/giy (MIPS). Cng thc tnh MIPS theo kin trc NeuMan l: MIPS = (f*N)/(M+T) Trong : f : tn s lm vic ca B VXL N: s lng cc n v x l s hc v logic (ALU) khng ph thuc vo nhau bn trong b VXL M: s lng vi lnh trung bnh ca 1 lnh trong b VXL T : h s tg truy cp BN (chu trnh ch i trong khi truy cp BN) Theo CT ny, tc thc hin lnh ca b VXL c th thay i nh 4 yu t. nng cao tc VXL kin trc song song , ng ng, ng x l, BN d tr. V bus rng c p dng cho cac chip VXL cng ngh cao hin nay. MIPS ph thuc vo tn s nhp ng h ca b VXL. Tn s nhp cng ln th tc thc hin lnh cng cao. Cc b VXL khi s/x thng c k hiu ch ci hay s c th phn bit tn s nhp ng h. Tn s nhp ng h ca b VXL ph thuc vo cng ngh ch to b VXL. Phn ln cc b VXL c ch to theo 2 cng ngh bn dn: NMOS v CMOS 1.2 Tc thc hin lnh ca b VXL: f = 750MHz N=4 M=5 T=100 MIPS=(f*N)/(M+T)=(750*4)/(5+100)=... Cu 2: Hy nu cc c tnh nng cao tc ca b VXL l g? nh ngha kin trc siu hng? Khun dng d liu? Tr li : * Nhng c tnh nng cao tc ca b VXL: 1. X l song song v kin trc siu hng 2. ng x l 3. K thut nh d tr 4. K thut ng ng 5. Bus rng + X l song song : l 2 qu trnh, tnh ton cng xy ra ng thi. Trong kin trc my tnh, s kt hp 2 b VXL trong khi x l trung tm (CPU) to ra kh nng x l song song trong cng 1 tg. Kin trc ny c th to ra tc x l d liu ln gp i so vi kin trc ch dng 1 b VXL. Cng c th thc hin song song ngay bn trong cu trc ca b VXL, bng cch thit k sao cho qu trnh x l D.liu bn trong chip VXL chia thnh cc phin khc nhau v thc hin song song nh s phn chia khi logic iu khin(CU) bn trong thnh phn ring. + ng x l : l b VXL ring bit kt ni vi b VXL thng qua bus h thng. B ng x l ch thc hin 1 s chc nng c bit, v d nh cc php ton i hi s chnh xc s dng du phy ng. Tc x l ca b ng x l nhng php tnh ny s nhanh hn rt nhiu so

vi b x l chnh. Cc b VXL cng ngh cao hin nay cy vo bn trong khi x l du phy ng FPU cng lm tng tc tnh ton cc php tnh nhanh v chnh xc hn nhiu. + B nh lu tr (cache memory): BN cache l BN c tc cao, n c th nm ngay bn trong b VXL vi dung lng hn ch hoc nm k ngay bn cnh b VXL v kt ni trc tip vi chip x l vi dung lng ln, trong khi BN chnh kt ni vi b VXL thng qua bus h thng. S trao i d liu gia BN chnh v b VXL b hn ch v tc , v vy tng tc x l, phi t chc lm sao khi thc hin chng trnh, b VXL trc ht tm kim lnh BN d tr trc, nu khng c lnh cha trong BN d tr th mi phi tm ti BN chnh. iu ny c ngha l nu a s lnh khng c trong BN d tr th tc x l chm hn gp i so vi truy cp thng vo BN chnh. V vy phi t chc lm sao a s cc lnh ca chng trnh nm hn trong BN d tr, v d cc lnh c tn sut xut hin trong chng trnh cao th c th ct trong BN d tr. Dung lng BN d tr phi ln m bo lu tr nhng chng trnh ng dng ln. Ngy nay, dung lng BN d tr bn trong cc chip VXL cha cao (32Kb :16Kb Dcache, 16Kb Icache). Vi BN d tr bn ngoi c th t ti dung lng 2-4 MB. + K thut ng ng : M phng dy chuyn lp rp my mc, h thng ng dn, trong 1 s VXL hin nay c chc nng thc hin cc lnh my lin tc thnh 1 dy chuyn vi 5 cng on : nhp D.Liu ca lnh t BN, gii m lnh, thc hin cc lnh, ghi kt qu thc hin lnh vo BN. Khi lnh th 1 bt u bc vo thc hin, giai on 2 th m lnh ca lnh tip theo c c t BN ra thc hin bc 1 (gii m lnh). C nh vy, cc lnh c thc hin theo 1 dy chuyn lin tc nh l dng nc i trong ng ng. Tc x lnh v th c tng ln rt cao. + Bus rng : K thut bus rng p dng cho c bn trong ln bn ngoi b VXL. Bn trong b VXL, thanh ghi tng (A) c di gp i bus, nh vy tc tnh ton s nhanh hn, bi khng phi thc hin cc php truy cp vi BN lu tr cc kt qu trug gian ca cc php tnh. * Kin trc siu hng : Kin trc ca b VXL c cc khi chc nng x l song song bn trong gi l kin trc siu hng, ngha l cng 1 lc nhiu hng x l khc nhau bn trong VXL. Kin trc siu hng l s pht trin tip theo ca kin trc RISC, n khng nhng nng cao tc x l m cn nng cao tin cy ca CPU, bi v khi c s c 1 chip VXL th chip VXL cn li vn m nhim chc nng c bnh thng. * Khun dng d.liu : Khun dng d.liu ca cc loi VXL c phn bit theo cc s c du, khng du, cc k t m ASCII, m BCD (h 2 - 10) : - khng du v c du : B Byte (8 byte), H na t (16 bit), W t (32 bit), D t kp (64 bit) (s phn loi ny cho cc b VXL 32 bit) Bit du l bit cao nht (MSB) - cc k t m ASCII : mi k t c m ha bng 8 bit. - D liu m BCD : d liu c biu din bng cc nhm s 4 bit. Mi nhm s 4 bit c gi tr khng vt qu 10 (1010). Phn bit d liu m BCD ng gi v khng ng gi. Trong BCD ng gi, tt c 64 bit c chia ra 8 nhm (8 digit) v c 8 digit c dng m ha. Hai BCD digit trong 1 byte. Trong BCD khng ng gi, ch dng 4 bit thp trong tng byte lm digit m BCD, 4 bit cao ca tng byte khng dng ti v u ghi gi tr 0. Cc du phy ng phn ra s chnh xc n 32 bit v chnh xc kp 64 bit theo chun IEEE 754-1985. Cng c th m rng chnh xc n 80 bit 1 s b VXl. S du phy ng c bit ln nht (MSB) dng lm du, du = 0, l s dng. Du = 1 l du m. Cu 3 : 1. S cu trc bn trong ca BVXL 8, 16 bit. < hnh v > 2. Gii thch chc nng tng b phn (ALU, cc thanh ghi, CU): a. n v s hc logic (ALU) - cha khi logic thc hin x l d.liu - Thc hin cc php tnh s hc v logic : and, sub, mul, div, and, or, not,... Shift left, Shift right, decr, incr, - C hai cng vo (in) nhn d.liu vo ALU v cng ra (out) ly kt qu x l d.liu ca ALU ra ngoi. - cc thanh ghi temp1 v temp2 lm nhim v nhn d.liu t cc ni khc nhau bn trong BVXL thng qua bus d.liu bn trong v lu tr trung gian d liu trong qu trnh x l d.liu trong ALU. Tng t, cng ra kt ni vi bus d.liu bn trong do kt qu php ton c th c ra ti cc ni khc nhau, d.liu thng c a ti ni b cng. - cc lnh my c ALU x l c th l 1 hay 2 ton hng. - Lnh my c c t BN vo BVXL c gii m nh b gii m lnh to ra chui cc tn hiu i ti ALU .khin qu trnh x.l d.liu trong ALU. b. Cc thanh ghi : c chia thnh nhm theo mc ch s.dng - Nhm thanh ghi dng chung: + Thanh ghi A (b cng), B, C, D, E, H, L : 8 bit + x l 16 bit, c cc lnh thc hin vi cc cp thanh ghi BC, CE, HL - Cc thanh ghi khc : thanh ghi trng thi (SR), con tr ngn xp (SP), thanh m lnh (PC), thanh ghi lnh (instruction register), * Thanh ghi tng A (accumulator): - tham gia phn ln cc php tinh - di ca thanh tng c th tnh bng di t hoc gp i di t ca BVXL. - nhng lnh I/O vi ngoi vi l nhm lnh trao i byte d.liu gia thanh ghi tng A vi cc thanh ghi ca iu khin ngoi vi. - Lnh nhp d.liu IN PORT l lnh c d.liu t cng ca ngoi vi vo thanh ghi A v OUT PORT l c ni dung thanh ghi A ra port ngoi vi. * Thanh m chng trnh PC (program counter) - 1 chng trnh c BVXL thc hin phi cha trong BN chnh. PC cha .ch ca lnh trong BN v ch ra cho BVXL bit lnh tip theo nm ngn nh no ly ra thc hin. - trong cc BVXL cng ngh cao c c ch qun l BN o. C ch nh a ch o c s bin i .ch o thnh .ch VL ni dung ca .ch lnh s phc tp.

* Thanh ghi trng thi SR (status register) - dng ghi kt qu ca cc lnh k.tra, s.snh v 1 s lnh tnh ton vi cc thanh ghi - thanh ghi trng thi cn gl thanh ghi c, s/dng cc bit c c th thc hin r nhnh chng trnh = cc lnh nhy v r nhnh c .kin * Con tr ngn xp SP (stack pointer) - Ngn xp l BN c c ch truy cp theo kiu LIFO, lun c truy cp nh TOP. N lm nhim v lu tr nhng thng tin phi dng i dng li nhiu ln. - Cc lnh tc ng n ngn xp: call, ret, int, - Cc lnh chuyn dng ct gi n.dung v phc hi cc thanh ghi ca ngn xp l push v pop, cc lnh ny lm thay i nh ca ngn xp. - Con tr ngn xp SP cha .ch ca nh ngn xp v n.dung ca SP s thay i mi khi thc hin cc lnh va nu trn - khi khi ng h thng my tnh, con tr ngn xp lun c khi to v a ch nh ca ngn xp. * Thanh ghi .ch BN v logic (memory address register and logic) - c di 16 bit, cc u ra ca n c iu khin ni ra bus /c ca h.thng my tnh thc hin chn ngn nh or chn cng ngoi vi no . - Trong chu k c lnh, 1 lnh my c c t BN, lc ny ndung thanh ghi /c ngn nh v n.dung ca thanh m lnh PC l nh nhau, ngha l thanh ghi .ch BN tr ti t lnh ang c c t BN. - Thanh ghi ch BN khng th t ng tng hay gim ndung m n nhn ch lnh t PC, t SP v thanh ghi ch s. - Ph thuc vo cc loi VXL, n c th c .di khc nhau: 16, 32, 64 bit * Thanh ghi lnh IR (instruction register) - cha lnh ang thc hin - nh l b m duy tr ndung m lnh v u ra ca IR a ti b gii m lnh to ra chui cc tn hiu iu khin thc hin lnh. c. Control Unit (n v iu khin) - c lin h thng tin vi t.c cc .v trong BVXL bi n .khin ton b h.g x l thng tin bn trong BVXL. - kqua gii m lnh c a n khi logic iu khin CL (control logic) to ra chui cc tn hiu .khin qu trnh ghi c vi cc thanh ghi bn trong, tnh ton trong ALU - t CL, cc xung tn hiu .khin i ra bus iu khin ca h.thng tc ng n BN hoc n v I/O thc hin trao i d.liu - CL nhn tn hiu .khin t bn ngoi, nh tn hiu ngt (INT, NMI), HOLD, RESET, x l bn trog trc khi a ra cc tn hiu tr li nh: chp nhn ngt INTA, dng HALT, - CL quyt nh th t lm vic ca tng v trong b VXL v s trao i thng tin vi th gii bn ngoi chip VXL. - CL l trung tm .khin ca BVXL 3. Cc vi mch h tr cho BVXL Mi loi VXL c nhng mch h tr ph hp i theo: - cc b VXL cng ngh cao hin nay (k t 80386) c nhng vi mch VLSI h tr gp nhiu chc nng .khin khc nhau c a vo c th thnh 1 CPU ca 1 my vi tnh. - Cc my tnh th h pentium 586/ 150 233 MHz vi bng m PSI/ ISA c cc vi mch VLSI h tr nh: 82437VX, 82438VX, to nhp ng h, iu khin I/O - Cc my vi tnh hin nay u c kh nng thit lp ban u cho cc vi mch h tr (chipset), l cc ch chipset features setup, bios features setup,

Cu 4: S khi n v giao tip bus (BIU) ca cc b VXL cng ngh cao. Gii thch chc nng tng b phn: BIU, PUIQ, SFU, cache, IU, MMU. Tr li:

S Y S T E M B S

32k Data bus 32 + i Address Bus

Data interface

Prefetch Unit And Instruction Queue

Address interface

Instruction Cache (Icache) Data Cache (Dcache)

Control Bus

Control interface

MMU

Internal Bus 32n

* Chc nng ca tng b phn: 1. BIU: 2. PUIQ (khi tin c lnh v hng lnh) - cha cc mch logic c trc cc lnh t Icache v t vo hng xp cc lnh theo nguyn tc vo trc ra sau FIFO - cc lnh ny c chuyn ti khi gii m lnh DU (decoding unit) - phn ln cc h VXL ngy nay cho php 1 s lnh ng thi c gii m (x l song song ) 3. SFU (special function unit): khi chc nng c bit, c th l: - khi ha - khi x l tn hiu - khi x l nh - b XL ma trn v vector 4. Cache: l BN tc nhanh nm gia BVXL v BN chnh - S tn ti BN d tr vi k.thc ln lm tng hiu sut ca BVXL v n cho php BVXL truy nhp thng tin nhanh hn nhiu so vi truy cp vo BN chnh - BN d tr kp (dual cache memory) phn ra BN d tr cc lnh (Icache), BN d tr lu tr d.liu (Dcache). C 2 cache u kt ni vi bus bn trong. Chng nhn thng tin t BN chnh thng qua bus D.liu v BIU. - Icache kt ni trc tip vi PUIQ, n chuyn 1 hay 1 s lnh vo PUIQ trong 1 c.k - Thng qua bus D.liu bn trong BN d tr D.liu (Dcache) v bus D.liu iu hnh (ODB) giao tip vi cc n v chc nng khc (IU, SFU, FPU) * Trong nhiu loi VXL cn c thm BN d tr th cp (secondary cache memory) - cache bn trong chip VXL l cache s cp (primary cache) - cache th cp nm bn ngoi chip v gia cache s cp v BN chnh bn trong cu trc BN. N c tc truy cp nhanh hn truy cp BN chnh (v n nm bn ngoi BVXL nn n c th c dung lng ln hn cache s cp). - dung lng ca cache th cp c th ln n vi MB (pentium III cho php m rng ti 4 MB) 5. IU (integer unit): n v nguyn - C c tnh cu trc phc v cho x l song song n c cc n v thao tc thc hin cc php s hc nguyn cng/tr, nhn/chia, c tp cc thanh ghi 32 bit hoc 64 bit. - Cc BVXL CISC thng c 8 16 thanh ghi. - Cc VXL RISC c ti 32 thanh ghi, i khi c hn 100 thanh ghi. - Dng d.liu i theo 2 ng ti cc v thao tc cc php tnh s hc. v gii m phn chia lnh DID nhn cc ch th c gii m ca CU v gi chng ti cc v x.l cc php tnh thch ng. - Cc php tnh vi s nguyn chuyn ti cc v x.l cc s nguyn ca IU, cc php tnh du phy ng chuyn ti v x.l du phy ng FDU, - D.liu t Dcache thng qua bus d liu thao tc ODB chuyn ti cc v x.l - v dch ng cho php thc hin cc lnh dch nhiu bit nhanh trong 1 c.k n. Cu 5: Gii thch phng php x.l lnh theo kin trc siu hng (superscalar). Vi xu hng pht trin cng ngh RISC, CU c hon ton cng ha hay thng c lp trnh. Tr li: Kin trc siu hng (superscalar) th hin trong c tnh thc hin cc lnh song song . Khi tin c lnh gi ra i lnh cng 1 thi im ti khi gii m. Khi iu khin ln lt to ra cc ch th cho 1 s ng thc hin. S lng lnh khng nht thit phi = s ng, tuy nhin s i lnh = s ng s l hiu qu nht, v nh vy l i lnh cng thc hin song song . Decoding Unit Control Unit Pipelined Pipelined Pipelined Operation Operation Operation Unit 1 Unit 2 Unit i n v iu khin CU ca BVXL c th hon ton cng hoc c lp trnh. Trong hu ht cc BVXL, cng ngh CISC (Intel X86 v Motorola) CU thng c lp trnh. Vi xu hng pht trin cng ngh RISC, CU c hon ton cng ha nhm tng tc thc hin hu ht cc lnh trong 1 chu k n. Cu 6: Chc nng ca n v qun l BN MMU. Tr li: MMU ca b VXL c cc chc nng: - Chuyn i a ch o (virtual address) hay a ch logic thnh a ch vt l (physical), tc l .ch thc. a ch vt l c chuyn ti Cache, hoc thng qua BIU v Bus .ch ti BN bn ngoi BVXL chn vng nh. - m bo c ch phn trang trong t chc BN o - m bo c ch phn on (segment) cho BN - Bo v BN cho c hai c ch phn trang v phn on - Qun l b m bin i truy cp nhanh TLB v qun l BN d tr chuyn i ATC. Phc v qu trnh chuyn i cc trang nh o thnh trang nh vt l. .v phn trang, TLB (hoc ATC) u c trong Mmu ca hu ht cc BVXL hin i. Trong Intel X86 c v phn on. Trong trng hp khng c TLB, MMU cha phn logic gim st truy nhn n cc bng v th mc tng ng trong BN chnh.

To Instruction Cache To Prefetch Unit To BIU Internal Bus

Translation Lookaside Buffer (TLB)

Paging Unit

Segmentation Unit

From IU Cu 7: B nh Cache : Cu trc Cache, Thut ton thay th (phng php thay th dng ca tp trong Cache) Tr li: 1. Cu trc Cache: Cache ghi nh mt tp hp Ai cc .ch ca BN chnh v cc t d.liu M(Ai). D liu trao i gia Cache v BN chnh c nhm theo cc khi, hay khi cc dng. Mi mt khi lnh nh vy l 1 phn khi ca 1 trang no ca BN chnh. Do .ch cha trong Cache l .ch khi. Cc dng ct gi trong Cache khng c .ch ring bit, m chng c tham chiu ti nh .ch ca chng lu trong BN chnh. V tr chnh xc ca cc dng trong Cache c x.nh bng phng php s.xp .ch gia BN chnh v Cache. Ni dung ca mng Cache l nhng bn sao ca tp cc khi nh khng lin tip nhau km theo .ch ca BN chnh. 2. Thut ton thay th (phng php thay th dng ca tp trong Cache) B1: CPU yu cu lnh/d.liu lu tr trong a ch a B2: Khi ni dung t .ch a khng c bn trong BN Cache, CPU phi mang n v trc tip t BN RAM. B3: B phn .khin Cache ti 1 hng (thng thng 64 byte) bt u t .ch a v bn trong BN Cache. iu nhiu hn d.liu CPU yu cu, do nu chng trnh tip tc chy tun t (c ngha l yu cu .ch a + 1), lnh/d.liu tip theo CPU s yu cu c ti trong BN Cache. B4: Mch in gi l PreFetch ti nhiu v.tr d.liu hn sau dng sau, c ngha l bt u nhng ni dung ti t a ch a + 64 vo BN Cache. Nu chng trnh thng chy tun t th CPU khng bao h cn ly d.liu trc tip t BN RAM v, nhng lnh v d.liu CPU yu cu s thng nm trong BN Cache trc khi CPU hi ti chng. Nu chng trnh thng chy tun t th CPU khng bao gi cn ly d liu trc tip t b nh RAM v (ngoi tr vic ti lnh u tin), nhng lnh v d liu CPU yu cu s thng nm trong b nh Cache trc khi CPU hi ti chng. Tuy nhin nhng chng trnh li khng chy nh vy, chng s thng nhy t v tr b nh ny ti v tr b nh khc. Thch thc ln nht ca B phn iu khin Cache chnh l c gng phng on CPU s nhy ti a ch no, ti ni dung ca a ch vo bn trong b nh Cache trc khi CPU yu cu n trnh trng hp CPU phi i ti b nh RAM ca h thng, v iu lm chm hiu sut lm vic ca ton b h thng. Nhim v ny c gi l D on r nhnh v nhng CPU mi u c c im ny. Nhng CPU hin i c t l hit t nht l 80%, c ngha l t nht 80% thi gian CPU khng cn truy cp trc tip ti b nh RAM ca h thng v thay th vo truy cp ti b nh Cache . Cho dng X = 275 trong BN chnh vi s lng cc tp trong Cache l k = 128. Xc nh dng X ca BN chnh c xp vo tp bao nhiu ca BN Cache. Dng 275 s c xp nh sau : 275/128 = 2 + 19/128, ngha l dng 275 ca BN chnh c xp vo tp 19 trong Cache. Cu 8: Cc kiu ca BVXL song song v h.sut ca XL song song . Hy so snh cu trc my tnh chia s BN v phn tn BN. Tr li: * Cc kiu ca BVXL song song : Phn loi Flynn: - Chui lnh l chui d.liu SISD - Chui lnh l nhiu chui d.liu SIMD - Nhiu chui lnh 1 chui d.liu MISM - Nhiu chui lnh nhiu chui d.liu MISM Phn loi theo cu trc: - Truyn thng theo cc bin s dng chung Cc h kt ni cht ch hay cc BVXL gi l VXL i xng SMP. - H thng VXL chia s BN: C 1 VXL c 1 BN I/O dng ring ca n * So snh cu trc my tnh chia s BN v phn tn BN : My tnh chia s B nh My tnh phn tn B nh - H thng my tnh m trong mi .v x.l kt ni vi - H thng my tnh vi t chc, m trong cc v nh 1 v nh to thnh 1 khi x l ring (vi ti nguyn kt ni trn mng N lm thnh ring) v kt ni vi nhau trn mng kt ni N trao i ti nguyn, th gi l my tnh c BN phn phi ti 1 BN chnh tng th m bo chia s cho tt c cc v x.l, nguyn. gi l my tnh c BN chia s.

Cu 9 : Cc BVXL cu trc ng (pipeline Processors) - b XL ng gm c 1 chui lin tip cc mch x l m cc mch x l thng gl phn on hay tng. Thng qua chui ny, dng ton hng c x l . Mi phn on x l tng phn ca cc ton hng v cc kt qu cui cng ch nhn c khi ton b chui cc ton hng i qua ht cc phn on ca ng. - Mi phn on x.l tng phn cc ton hng v k.qu cui cng ch nhn c khi ton b chui cc ton hng i qua ht cc phn on ca ng. Cu trc ca BVXL ng: Phn on 1, (S1) Phn on 2, (S2) Phn on m, (Sm) Thanh ghi ra, (R) R1 C1 R2 C2
Rm Cm

Cc thanh ghi Ri l nhng b m nhn d.liu Di 1 (l cc kt qu tnh c trong c.k xung nhp ng h trc ca cc v tnh Ci 1) t phn on Si 1, ngoi tr cc thanh ghi Ri nhn d.liu bn ngoi ng. - Mt ng ng lnh n gin c th c t chc gm 2 phn on: phn on c lnh (S1) v phn on thc hin lnh (S2) a ch lnh c lnh (Fetch instruction) S1 Thc hin lnh (execute instruction) S2 Kt qu

Mt ng ng lnh c bn c th hnh thnh nh phn theo chu k lnh: c lnh(S1), gii m lnh(S2), c cc ton hng(S3), thc hin lnh (S4), ct gi kt qu (S5) n b nh

c lnh S1

Gii m lnh S2

c ton hng S3

Thc hin lnh S4

Ct gi kt qu S5