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CHNG 6

TRUYN NI TIP NG B
GIAO TIP GIA DTE V DCE NG B CC GIAO THC NG B
Giao thc ng b nh phn Giao thc hng bit

VI IC LSI DNG TRONG TRUYN NG B

USART 8251A ca Intel SSDA 6852 ca Motorola

KM TRA H THNG THNG TIN

Php o t s PAR Biu mt

V phng din thc hin s ng b gia my thu v pht trong mt h thng thng tin hai ch truyn bt ng b v ng b c nhng im khc bit : - Ch truyn bt ng b: pht bn tin ngi ta pht i tng k t mt v s ng b c thc hin cho tng k t ny bi cc bit Start v Stop thm vo trc v sau mi k t . Xung ng h c to ra mt cch ring r my thu v my pht. Nh vy, s ng b c thc hin chnh xc khi tn s xung ng h my thu hon ton ng vi tn s xung ng h my pht, nu khng tin tc nhn c s c li. - Ch truyn ng b: pht mt bn tin ngi ta xem n l mt khi v pht i mt ln c khi , s ng b c thc hin bng cch cho my pht pht km theo tn hiu d liu cc xung ng h m my thu khi d ra s dng ng b tn hiu my thu. Thc t, vic ny ch c thc hin khi h thng thu pht khp kn v mt vt l, hay ni cch khc my pht v thu phi gn nhau. Khi my pht khng th gi ring tn hiu xung ng h ti my thu th my thu phi c mch tch bit thi gian t chnh tn hiu d liu thc hin s ng b. my thu ng b, ngoi vic d tn hiu ng b ra, my thu phi bit phn bit c ranh gii ca mi k t vic phc hi bn tin khng b li. Ta thy vic thc hin giao thc bt ng b tng i n gin, gi thnh thp nhng hiu qu khng cao. Gi s pht mt k t m ASCII th phi dng t nht 9 bit (7 bit k t, 1 bit start, 1 bit stop), th t l hao l 2/9 = 0,22=22%. Trong khi , t l ny trong ch ng b l rt thp, khong vi %. Nh vy, ch truyn bt ng b ch thun li khi pht nhng bn tin ngn v vi vn tc thp (<1200 bps). V ch truyn ng b t ra u vit hn khi pht nhng bn tin di vi vn tc cao hn (>1200 bps). Dng vi cc Modem m tn, pht ng b c th t vn tc 9600 bps. Chng ny cp n cc giao thc ng b, kho st vi IC LSI thc hin vic pht ni tip ng b thng dng v cui cng s lc qua cc phng php kim tra h thng thng tin.

6.1 GIAO TIP GIA DTE V DCE NG B

Trong ch truyn ng b, my thu phc hi xung ng h t dng d liu nhn c. Chun giao tip RS-232 v RS-449 c cc ng dnh cho xung ng h lin lc gia cc cp thit b u cui (DTE) v modem (DCE). Bng 6.1 cho bit ni nhn d liu v cc chn lin h ca hai chun giao tip ni trn
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Bng 6.1
K hiu TCLK RCLK ETCLK

Cc chn truyn tn hiu ng b ca RS-232 v RS-449 RS-232

Chn 15 17 24 Tn Trans. clock (t DCE) Receive Clock (t DCE) Ext trans.clock (t DTE) K hiu ST RT TT Chn 6 & 23 8 & 26 17 & 25

RS-449
Tn Send timing (t DCE) Receive timing (t DCE) Terminal timing (t DTE)

Khi s dng modem, ng b thu thng c cp t modem (DCE) ti thit b u cui (DTE). Tuy nhin xung ng h c th pht sinh t modem hoc t DTE (Cc IC to thnh modem v IC giao tip u c mch to xung ng h) v vic iu khin c th thc hin ring r c my thu v pht hoc thc hin theo c hai chiu vi mt xung ng h duy nht. (H 6.1) m t cc kh nng kt ni mch ca RS-449 thc hin ng b. (H 6.1a) Thit b u cui (DTE) mi trm thu pht iu khin s ng b (xung ng h t DTE n DCE theo ng TT) (H 6.1b) Modem (DCE) mi trm thu pht iu khin s ng b (xung ng h t DCE n DTE theo ng ST) (H 6.1c) Thit b u cui trm A iu khin s ng b theo c hai chiu (xung ng h t DTE A n DCE A theo ng TT, trm B hai ng TT (ST) v RT ni chung li) (H 6.1d) Modem trm A iu khin s ng b theo c hai chiu (xung ng h t modem n DTE theo ng ST trm A, trm B hai ng ST (TT) v RT ni chung li) DTE
A SD TT RT RD SD TT RT RD

DCE
A

DCE
B SD TT RT RD SD TT RT RD

DTE
B

(a)

DTE
A SD ST RT RD SD ST RT RD

DCE
A

DCE
B SD ST RT RD SD ST RT RD

DTE
B

(b)

DTE
A SD TT RT RD SD TT RT RD

DCE
A

DCE
B SD TT RT RD SD ST RT RD

DTE
B

(c)

DTE
A SD ST RT RD SD ST RT RD

DCE
A

DCE
B SD TT RT RD SD ST RT RD

DTE
B

(d) (H 6.1)

6.2 CC GIAO THC NG B

Mt h thng thng tin c th c nh dng bng cc giao thc khc nhau.
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Trong ch truyn ng b, c th chia giao thc ra lm hai loi : - Giao thc iu khin Byte hay k t (Byte - Controlled Protocol, BCP, hay Character-Oriented Protocol). - Giao thc hng Bit (Bit - Orientied Protocol, BOP). - Trong giao thc iu khin byte (BCP), khi d liu bao gm nhiu k t, mi k t l mt n v thng tin (7 hoc 8 bit) v cc thng tin iu khin cng xut hin di dng t. Cc k t d liu (bn tin chnh thc) hp vi t iu khin thnh mt khung thng tin. Mt khung thng tin thng bt u bng mt hay nhiu t dng cho s ng b, thng l t SYNC, n bo cho my thu bit bt u mt khi d liu. Ngoi ra, trc v sau bn tin chnh thc cn c cc t iu khin, bao gm cc a ch cc i, trm, cc t bo bt u v kt thc vn bn, cc t bo m kim tra li ... - Trong giao thc hng bit (BOP), khi d liu xem nh mt chui bit, cc t iu khin v k t d liu khng hn l cc t 8 bit m c th l mt tp hp cc bit ty theo giao thc c th. Ging nh trong BCP, bt u khi tin cng c tn hiu bo, l t 8 bit gi l C (Flag) , c ny cng c t cui bn tin. Nh vy tc dng ca c l thit lp s ng b v nh du im bt u v im kt thc. Khi d liu bao gm c cc c hnh thnh mt Khung (Frame). Trc v sau bn tin chnh thc c cc t iu khin, c gi chung l Trng iu khin (Control Field). Tt c qui nh chi tit v bn tin, cc thng bo hi nhn u thc hin trong trng iu khin ny. (H 6.2) cho ta hai dng khung ca hai protocol ny

(H 6.2)

Chng ta gii thiu di y: - Giao thc iu khin byte c ngh bi IBM vo nm 1964 v c s dng rt rng ri trong cc ng dng im - im (poin - point) v nhiu im (multipoint) vi cc phng thc n cng v bn song cng. l giao thc truyn ng b nh phn (Binary Synchronous Communication, BSC, i khi gi l BISYNC). Giao thc BSC c ISO ly lm c s xy dng giao thc hng k t chun quc t vi tn Basic Mode (d liu dng m EBCDIC
thay cho m ASCII v m d sai l CRC thay cho BCC)

- Giao thc hng bit, do hng IBM pht trin v s dng c tn l iu khin lin kt d liu ng b (Synchronous Data Link Control - SDLC) v ISO ly lm c s pht trin thnh giao thc iu khin lin kt d liu mc cao (High Level Data Link Control, HDLC).

6.2.1 Giao thc ng b nh phn

y l giao thc iu khin vic truyn nhn d liu nh mt s k t c bit trong cc bng m. Cc thng tin d liu c gi i trong cc khung d liu m hai bin l cc k t SYNC bo my thu bit bt u bn tin. Cc t iu khin dng trong BISYNC ly t bn m ASCII, gm mt s t nh sau :
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SYN SOH STX ETX EOT ETB ENQ ACK NAK NUL DLE CAN

K t ng b m ASCII dng Hex K t bt u ca Header K t bt u vn bn K t kt thc vn bn K t kt thc pht K t kt thc truyn khi K t hi K t bo cho bit nhn d liu K t bo cho bit cha nhn d liu K t rng K t gii phng ng d liu K t hy Mt khung d liu ca BISYNC tiu biu c cu trc sau : SYN u SYN SOH header STX text ETX

16H 01H 02H 03H 04H 17H 05H 06H 15H 00H 10H 18H

BCC Cui

- Phn vn bn (text) cha d liu thng tin. Kch thc vng text c gii hn nn vi cc vn bn ln ngi ta chia thnh nhng khi nh (block) v trong phn Header c phn identifier (id) ch th t cc khi. - Phn header cha i ch n v tn hiu tr li ACK/NAK nu c yu cu. - BCC l k t 1 Byte dng kim tra khung. y l byte duy nht c to ra kim tra li trong ton khi. BCC c th l mt php kim tra chn l (dng trong BSC), hoc chc ch hn l kim tra d tha theo chu k (Cycle Redundancy Check, CRC ) (Dng trong Basic Mode, vi CRC - 16). Di y l v d truyn ch TEST v kim tra chn l theo hng STX 0 1 0 0 0 0 0 1 T 0 0 1 0 1 0 1 1 E 1 0 1 0 0 0 1 1 S 1 1 0 0 1 0 1 0 T 0 0 1 0 1 0 1 1 EXT 1 1 0 0 0 0 0 0 BCC 1 1 1 0 1 0 0 0 b0 b1 b2 b3 b4 b5 b6 b7

i vi v d trn cc bit s c truyn nh sau : STX 01000001 u T 00101011 E 10100011 S 11001010 T 00101011 ETX 11000000 BCC 11101000 Cui

Trong v d ny ngi ta dng kim tra chn v BCC ch kim tra cc k t t STX n ETX. Trn thc t, s kim tra c thc hin trn ton khi (t SOH n ETX). Khi nhn c bn tin, my thu thc hin php tnh kim tra tng, so snh vi BCC nhn c, sau s tr li bng tn hiu ACK (ng) hoc NAK (Khng ng). My pht s khng gi bn tin khc khi cha c xc nhn rng bn tin trc nhn ng (phng thc bn song cng). Di y l mt s th tc chnh trong BSC/Basic Mode: - Mi truyn tin: Gi s trm A mun mi trm B truyn tin, trm A s gi lnh sau y ti B:
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EOT B ENQ Trong B l a ch ca trm c mi truyn tin EOT chuyn lin kt sang trng thi iu khin Khi B nhn c lnh ny, c th xy ra 2 trng hp: - Nu B c tin truyn th B to cu trc tin theo dng chun v gi i - Nu B khng c tin truyn th gi i lnh EOT tr li pha A mt khong thi gian xc nh sau khi gi lnh i m khng c tr li hoc nhn c tr li sai th A s chuyn sang trng thi phc hi (Recovery state). - Mi nhn tin: Gi s trm A mun mi trm B nhn tin, trm A s gi lnh sau y ti B: EOT B ENQ C th b qua lnh EOT. Khi nhn c lnh ny, nu B sn sng nhn tin th n gi lnh ACK tr li, nu khng th gi lnh NAK pha A mt khong thi gian xc nh sau khi gi lnh i m khng c tr li hoc nhn c tr li sai th A s chuyn sang trng thi phc hi (Recovery state). - Yu cu tr li: Khi mt trm cn trm kia tr li mt yu cu no gi i trc th n ch cn gi lnh ENQ n trm kia - Ngng truyn tin (tm thi): Gi lnh EOT - Gii phng lin kt: Gi lnh DLE EOT - Trng thi phc hi: Khi mt trm no i vo trng thi "phc hi" n s thc hin mt trong cc hnh ng sau: - Lp li lnh gi i n ln (n l s nguyn chn trc) hoc - Gi "yu cu tr li" n ln hoc kt thc truyn bng lnh EOT - Ch thng sut (Transparent Mode). Trong trng hp cc m iu khin xut hin trong vn bn (Text) nhng khng mang ngha iu khin m phi c hiu nh l d liu, h thng c chuyn sang ch thng sut bng cch dng k t DLE t trc STX v DLE t trc ETX chm dt ch ny.

6.2.2 Giao thc hng bit.

Giao thc hng bit c thit k tho mn nhiu yu cu trong cch truyn ng b, bao gm : - Truyn gia hai i (trm) (point to point) hay nhiu i (multipoint). - Bn song cng hay song cng. - Lin lc gia trm s cp v trm th cp. - Lin lc vi khong cch ngn (ni trc tip), hoc rt xa (v tinh). Giao thc ny c mt s tnh cht sau : - Ngi s dng c th s dng bt c loi m no. - C kh nng thch hp vi nhiu loi ng truyn. - Hiu sut cao : gim ti thiu t l hao ht. - tin cy cao : cho php kim tra li c hiu qu v c kh nng phc hi d liu. C th ni cc tnh cht ca giao thc hng bit c th hin trng iu khin bi cc t hp bit m ha cc t iu khin. C nhiu giao thc hng bit c ngh bi cc c quan khc nhau v c s dng rng ri : - Th tc iu khin thng tin d liu cao cp (Advanced Data Communication Control Procedure - ADCCP) pht trin bi Vin chun quc gia Hoa K (American National Standard Institute - ANSI) y l chun trong h thng thng tin quc gia.
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- Th tc truy xut ng truyn cn bng (Link Access Procedure, balance - LAP-B) thc hin bi Hi ng T vn in tn v in thoi quc t (International Telegraph & Telephone Consultative Committee - CCITT) y l mt chun v mng. - iu khin lin kt d liu ng b (Synchronous Data Link Control - SDLC) c dng bi hng IBM (International Business Machine Corporation) v ISO ly lm c s pht trin thnh giao thc iu khin lin kt d liu mc cao (High Level Data Link Control, HDLC). Tht ra khng c my khc bit gia cc chun ni trn: HDLC v ADCCP c th xem l mt cn LAP-B v SDLC l nhng tp con ca HDLC. Phn sau y s bn ti chun SDLC.

6.2.2.1 c tnh c bn :
SDLC nh ngha 3 loi trm, 2 dng truyn v 2 ch vn hnh. * 3 loi trm: - Trm s cp: (Primary) c trch nhim iu khin vn hnh ca h thng, nhng khung pht bi trm s cp gi l lnh (command) - Trm th cp: (secondary) vn hnh di s iu khin ca trm s cp, nhng khung pht bi trm th cp l li p (response) Trm s cp duy tr vic ni logic vi tng trm th cp trong h thng mt cch ring r . - Trm hn hp: Cc trm ng thi gi vai tr s v th cp. * 2 dng truyn: - Dng khng cn bng : dng gia 2 trm hoc nhiu trm, gm mt trm s cp v mt hoc nhiu trm th cp, c th truyn song cng v bn song cng. - Dng cn bng : ch dng gia 2 trm hn hp, c th truyn song cng hoc bn song cng. * 2 ch vn hnh : - Ch tr li chun (Normal Response Mode - NRM) : y l mt dng truyn khng cn bng, mt trm s cp c th khi ng truyn d liu n trm th cp v trm th cp ch c th truyn d liu tr li khi trm s cp yu cu. - Ch bnh thng khng kt ni (DISC) : ch ny trm th cp nhn tin nhng khng tc ng c vo bn tin. (H 6.3) m t dng truyn cn bng v khng cn bng.
Primary Commands Responses Secondary Secondary

(a) Dng khng cn bng

Commands --------------------------------------------- Responses

Combined

Combined

b) Dng cn bng (H 6.3)

6.2.2.1 Cu trc ca khung : (H 6.4) __________________________________________________________________________

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Mt khung thng tin trong SDLC gm cc trng sau y : - C : 8 bit - i ch : 1 byte. - iu khin : 8 bit. - Thng tin : thay i theo bn tin. - Chui kim tra khung (Frame Check Sequence - FCS) : 16 bit. - C : 8 bit. Cc trng c, i ch v iu khin t trc trng thng tin gi l u khung (header) v cc trng FCS v c t sau trng thng tin gi l cui khung (Trailer). (H 6.4) cho dng ca khung v cc trng trong khung
A FLAG ADDRESS CONTROL INFORMATION FCS FLAG

8 bit 8 bit

8 bit

variable

16 bit

8 bit

(H 6.4) Dng khung thng tin SDLC

a. Trng c (Flag Field) :

Trng c t u v cui mt khung gii hn khung, gm 8 bit theo qui nh l 01111110 (6 bit 1 lin tip gia 2 bit 0 ). Gia 2 khung c th c mt trong cc trng hp sau y: - Mt c xut hin gia bn tin gi l c n va dng chm dt mt khung ng thi bt u mt khung khc. - Mt c chm dt khung trc v mt c bt u khung sau. Gia 2 c ny c th ch dng mt bit 0. - C th chn vo gia 2 c mt s c khc. : Khung x+1 . . . . 01111110 . . . . . . . . 01111110 : 01111110 . . . . . . . . 011111101111110 . . . . . . . . 01111110 01111110 : 01111110 01111110 . . . . Do SDLC khng c qui nh cht ch v m dng cho d liu nn cc m c dng ca c c th xut hin trong bn tin v gy nn nhm ln my thu. trnh s hiu lm my thu khi nhn d liu, my pht dng k thut nhi bit ngha l khi thy trong chui d liu c 5 bit 1 lin tip th thm vo bit 0 ngay sau 5 bit 1 ny. my thu sau tn hiu c khi gp lin tip 5 bit 1 th t ng b bit 0 theo sau phc hi d liu. Nh vy bo m s chnh xc ca d liu. Th d: Trm B c a ch l C2 pht i vn bn C? - Khung thng tin cha nhi bit: (Vit theo chiu mi tn hng v bn tri) 01111110 01000011 01111110 11111110 11000011 11110110 C /c= C2 TK m =7F m C= C3 m ?= 6F 11111110 FCS 01111110 111111111111. . . . =7F C Bit ngh - Khung thng tin c bit nhi (o): 01111110 01000011 011111o10 11111o110 11000011 111o10110 C /c= C2 TK m =7F m C= C3 m ?= 6F 11111o110 FCS 01111110 111111111111. . . .
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=7F

Bit ngh

b. Trng a ch (Address field)

Trng a ch dng xc nh trm th cp trong h thng. a ch trong bn tin lun lun l a ch ca trm th cp d n do trm s cp hay th cp gi i. Trng ny khng cn thit trong trng hp h thng ch gm hai trm. Trng a ch di 8 bit. Nu tt c cc bit trong trng a ch u =1 c ngha trm s cp yu cu lin lc vi tt c trm th cp. Gi tr 00 khng c xem l mt a ch (gi l void address)

c. Trng iu khin (Control field) (H 6.5)

SDLC nh ngha 3 loi khung ca trng iu khin, mi loi c dng khc nhau Mt hoc hai bit u tin ca trng iu khin dng nh ngha khung : bit th nht = 0 ch khung thng tin, bit th nht v hai = 10 ch khung gim st v = 11 ch khung khng s. Nhng bit cn li c t chc nh nhng tp bit con m ngha ca n s c gii thch c th i vi tng loi khung. Mt frame ca SDLC c coi l bt hp l nu n khng c ng khung bi 2 C hai u hoc c tng kch thc cc vng nm gia 2 C nh hn 32 bit. I : Information S : Supervisory U : Unnumbered 1 (LSB) 2 0 1 0 1 1 3 Ns S M 4 5 P/F P/F P/F 6 7 Nr Nr M 8

Ns = Send sequence number S = Supervisory function bits P/F = Poll/Final bit

Nr = Receive sequence number M = Unnumbered function bits

(H 6.5) Dng trng iu khin

- Khung loi I: (Thng tin, Information frame, I-frame) , y l khung cha bn tin cn pht i ca ngi s dng. Khi khung I c dng th bn vn pht i c nh s th t. Bit 5 trong khung thng tin c tn l bit P/F (Poll/Final). * Nu bn tin pht i t trm s cp n trm th cp th y l bit P, nu P=0 th trm th cp khng cn thit phi tr li ngay, nu P=1 th y l bit thm d v trm th cp phi tr li ngay. * Nu bn tin pht i t trm th cp n trm s cp th y l bit F, nu F=0 th y cha phi l bn tin cui cng v trm s cp khng cn thit phi tr li ngay, nu F=1 c ngha y l bn tin cui cng v trm s cp phi tr li ngay. * Ns ch s th t bn tin ang c pht i. * Nr l s th t nhn, nu pht i t trm s cp th lin h n s Ns pht i t trm th cp v nu pht i t trm th cp th lin h vi Ns pht i t trm s cp. Nr ch s th t bn tin m trm ang ch v ng thi xc nhn nhn tt cc bn tin trc (tc n s Nr-1) Th d, trm th cp pht i Ns=2 v Nr=3 c ngha l n ang pht i bn tin th 2 v nhn tt cc bn tin th 2 tr v trc. Do cc s Ns ch c 3 bit nn s lng ti a mi ln pht ch c 7 bn tin, nh vy buc my thu phi xc nhn trc khi s Ns vt qu 7 (Ns=111). Di y l mt th d, Gi s trm s cp ang pht v cc s Nr v Ns u bt u bng s 0
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S cp Ns P Nr 0 000 0 000 0 100 0 000 0 010 1 000 0 110 0 001 0 101 0 011 0 111 0 000 0 0 0 0 0 1 010 010 010 010 010 010

Th cp Ns F Nr Trm s cp pht 3 khung thng tin. Khung th 3 l khung thm d 0 000 0 110 0 100 1 110 Trm th cp bo nhn vi Nr=3. N gi li 2 khung thng tin. Trm s cp bo nhn tt 2 khung vi Nr=2. Gi tip 6 khung

0 010 0 011 0 110 0 011 0 001 1 011 0 011 0 111 0 000 0 100 0 0 0 1 101 101 101 101 10 00 1 010 0 010 0 110 0 001 0 101 0 011 0 0 0 0 1 101 101 101 101 101 10 00 1 101 (RR) or 10 01 1 101 (REJ)

V Nr=6, Trm th cp bo nhn Nr-1=5 khung v yu cu pht li khung 6. V trm s cp khng bit ch khung 6 hay tt c cc khung theo sau c sai FCS nn n pht li tt c t khung 6 Trm s cp bo nhn tt khung 4 vi Nr=5. Tip tc pht li khung 6. (Lu l s m Ns vt tr cho php nn tr v 0) Trm th cp bo nhn tt c cc khung vi Nr=2. V trm th cp khng cn g gi, khung gim st c dng Trm s cp gi tip 5 khung

Trm th cp xc nhn khung 4 v yu cu pht li t khung 5 (Nr=5)

- Khung loi S: (Gim st , Supervisory frame, S-frame), dng m s khung gi/nhn; mt s lnh v li p bo tnh trng ca my thu (nh sn sng hay bn) kim sot v bo li. Khung gim st bt u bi 2 bit 10. Bit 3 v 4 (v tr S trong khung) xc nh cc lnh ca khung gim st b3b4= 00 : Ready to receive (RR) : Not ready to receive (RNR) b3b4= 10 b3b4= 01 : Reject (REJ) Trm th cp s xa khung RNR bng cch gi mt khung thng tin vi bit F=1 v i vi cc khung RR v REJ th F=0 hay 1. Trm s cp s xa khung RNR bng cch gi mt khung thng tin vi bit P=1 v i vi cc khung RR v REJ th P=0 hay 1. - Khung loi U: (Khng s, Unnumbered frame, U-frame), cung cp nhng chc nng iu khin ph nh khi ng trm thu, kim tra trm, gii phng lin kt khi cn thit . . . . Khung khng s bt u bi 2 bit 11. Khi dng khung U pht th khng cn nh s th t bn tin. Bng 6.2 cho cc lnh trong khung U: M nh phn Lnh Pht i t trm s c p Pht i t trm th cp Cho php pht bn vn
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1100 P/F 000 1110 P 000 1110 F 000 1100 P 001 1111 F 000 1100 F 010 1100 P 010 1100 P/F 110 1110 F 001

UI SIM RIM SNRM DM RD DISC UA FRMR

x x x

x x x x x x x

UI - Unumbered Information (NSI - Nonsequenced Information): Cho php d liu ngi s dng c pht theo kiu khng tun t SIM - Set Initialization Mode: Dng khi to mt cuc lin lc gia trm s v th cp. Lnh ny s reset s m Ns v Nr v trm s cp ch trm th cp tr li vi lnh UA. RIM - Request Initialization Mode (RQI - Request Initialization): Trm th cp yu cu trm s cp pht lnh SIM SNRM - Set Normal Response Mode: t trm th cp vo ch ch tr li. Trong ch ny trm th cp c th tr li vi cc loi khung I, U v S. Trm th cp khng th t t mnh vo mt trong hai ch NRM v DISC DM - Disconnect Mode (ROL - Request On-Line): c pht bi trm th cp bo cho trm s cp bit n ang ch bnh thng khng kt ni. Thng khi c bo th trm s cp s t ch tr li bnh thng cho n (SNRM). RD - Request Disconnect (RQD - Request Disconnect): Dng trm th cp yu cu khng kt ni. DISC - Disconnect: Pht bi trm s cp a trm th cp vo ch bnh thng khng kt ni. ch ny trm th cp nhn tin nhng khng tc ng c vo bn tin. UA - Unumbered Acknowledgement (NSA - Nonsequenced Ack.): Phc v nh mt tn hiu ACK (trm th cp bo nhn) i vi khung SNRM, DISC hoc SIM. FRMR - Frame Reject (CMDR - Command Reject): c dng bi trm th cp t chi mt khung sai FCS. pht lnh FRMR, trm th cp phi ch tr li bnh thng (NRM). Lnh ny bo cho trm s cp bit khung thng tin trm th cp nhn c c mt trong cc li: - Trng iu khin khng c ngha. - Trng thng tin qu di (di hn b m ca my thu). - S Nr pht t trm s cp khng c gi tr (khng tng thch vi s Ns ca trm th cp). Trm th cp sau khi pht lnh ny ch tr v ch bnh thng khi nhn c mt trong cc lnh t ch nh DISC, SIM hoc SNRM t trm s cp. Ta ni cc lnh ny reset lnh FRMR. Khi gi khung FRMR, trm th cp phi dng dng vn bn c nh, trong c ch r l do sai:
Flag Address field FRMR control field control field of rejected frame [ Ns Nr] 0 xxx 0 xxx [ wxyz 0000 ] FCS Flag

- Nr v Ns l s th t hin hnh ca trm th cp. L do sai xc nh bi cc bit wxyz (cc s 0 thm vo sau cc bit wxyz cho 8 bit) - w=1 nu trm th cp nhn c lnh khng c gi tr hay khng th thi hnh c. - x=1 khung thng tin khng ng. - y=1 m thu b trn. - z=1 nu s Nr khng khp vi s Ns.

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Di y l mt th d v mu i thoi trong h thng nhiu im, phng thc truyn song cng hon ton (F/FDX). Trm A khi ng ch NRM v trm B ch DM
_____________________________________________________________________
Flag A RR FCS Flag Trm s cp thm d trm A 7E C 1 11 7E Flag A Text FCS Flag A gi khung thng tin th nht; 7E C 1 00 7E Nr=Ns=0 , F=0 Flag A Text FCS Flag A gi khung thng tin th hai; 7E C 1 02 7E Nr= F =0 , Ns =1 Flag A Text FCS Flag A gi khung thng tin th ba; 7E C 1 14 7E Nr=0 , F=1 , Ns=2 Flag A Text FCS Flag S cp gi vn bn tr li; 7E C 1 60 7E Nr=3 , P=0 , Ns=0 Flag A Text FCS Flag S cp gi khung thng tin th 2; 7E C 1 72 7E Nr=3 , P=1 , Ns=1 Flag A REJ FCS Flag Trm A bo khung th 2 sai FCS; 7E C 1 39 7E Nr=1, F=1 Flag A Text FCS Flag S cp pht li khung th 2; 7E C 1 72 7E Nr=3, P=1, Ns=1 Flag A RR FCS Flag Trm A bo nhn khung th 2; 7E C 1 51 7E Nr=2, F=1 Flag B Text FCS Flag S cp gi khung thng tin trm B; 7E C 2 10 7E Nr=Ns=0, P=1 Flag B DM FCS Flag Trm B bo n ang ch DM; 7E C 2 1F 7E Flag B SNRM FCS Flag S cp t trm B vo ch NRM; 7E C 2 93 7E Nr=Ns=0, P=1 Flag B UA FCS Flag Trm B tr li bng lnh UA; 7E C 2 73 7E Flag B Text FCS Flag S cp gi khung tt 1 ti trm B; 7E C 2 00 7E Nr=Ns=0, P=0 Flag B Text FCS Flag S cp gi khung tt 2 ti trm B; 7E C 2 02 7E Ns=1, Nr=0, P=0 Flag B Text FCS Flag S cp gi khung tt 3 ti trm B; 7E C 2 04 7E Ns=2, Nr=0, P=0 Flag B Text FCS Flag S cp gi khung tt 4 ti trm B; 7E C 2 16 7E Ns=3, Nr=0, P=1 Flag B RR FCS Flag Trm B bo nhn tt c cc khung; 7E C 2 91 7E Nr=4, F=1 Flag B DISC(Text) FCS Flag S cp gi lnh disconnect ti trm 7E C 2 53 7E B ng thi gi theo mt bn tin Flag B FRMR DISC -- -- FCS Flag Trm B tr li vi khung FRMR, 7E C 2 97 53 80 02 7E DISC l trng K ca lnh sai 80 Nr=4, Ns=0 : s m hin thi ca trm B 02: x=1: Bn vn khng c php Flag B DISC FCS Flag S cp gi lnh disconnect ti trm B 7E C 2 53 7E Flag B UA FCS Flag Trm B tr li vi lnh UA; 7E C 2 73 7E ______________________________________________________________________________________

d. Trng thng tin (Information field)

Trng thng tin xut hin trong khung I , i khi trong khung U. Trng thng tin c th cha mt s bit bt k l bao nhiu, chiu di ca n khng xc nh nhng thng l bi ca 8.

e. Trng kim tra khung (Frame check sequence field, FCS)

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Trng kim tra khung FCS cha ni dung ch phng php thc hin vic kim tra. FCS thng dng trong SDLC l loi 16 bt kim tra d tha theo chu k (CRC) do CCITT thit lp (CRC-16).

6.2.2.3 Vn hnh
Vn hnh ca SDLC bao gm vic trao i cc khung I, khung S v khung U gia trm s v th cp hay gia hai trm s cp. Ngoi cc lnh cp trn, ta lu thm vi chi tit sau: - Bn vn bo b: l bn vn cha t 7 n 14 s 1 lin tip (bit nhi khng c thm vo cho on vn bn ny), my thu, sau khi nhn c Flag, nu gp lin tip t 7 n 14 s 1 th hiu rng khng phi quan tm ti tt c nhng g nhn c cho n lc . Xung ng b vn c duy tr khi nhn c bn vn bo b. iu kin b cng dng kt thc mt khung v bt u cho khung khc u tin hn. - Trng thi ngh: H thng vn vn hnh nhng khng c mt khung thng tin hay iu khin c pht i th h thng vo trng thi ngh, lc ny my thu nhn c lin tip t nht 15 bit 1. - M dng trong SDLC: m bo my thu duy tr c ng b phi c mt s thay i thng xuyn dng d liu ti. Do thc hin bin php nhi bit nn khng bao gi c qu 5 bit 1 lin tip vy ch cn trng hp mt lot bit 0 lin tip c th xy ra. gii quyt trng hp ny, ngi ta dng loi m non-return-to-zero inverted (NRZI) cho d liu trong SDLC . Tnh cht ca loi m ny l Khng c s thay i mc tn hiu khi gp bit 1 v mc tn hiu b o khi gp bit 0.

(H 6.6) - Cc bc tin hnh chun b pht mt bn tin:

* To bn vn v trng iu khin: Control field Text * Thm a ch vo: Address Control field Text * To khung FCS: Address Control field Text FCS * Thc hin nhi bit: Bit nhi c thc hin cho khung thng tin k t a ch v khung FCS. * Thm cc c u v cui bn tin. Lu l bit nhi thc hin sau khi tnh ton cho khung FCS nn trong khung FCS cng c th c bit nhi v my thu phi loi bit nhi trc khi dng thut ton kim tra li. Di y thm vi v d v cc lnh trong vn hnh ca SDLC (khng ghi li m)

Dng tng qut ca mt lnh A , C/R

P/F

(0)

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A a ch trm th cp C/R Lnh hi hoc li p Khong trng dng cho s Ns, c th thm du ( ) vo nu cn P/F Poll hoc Final bit (P = On P = Off, tng t cho F) (0) s Nr (nu cn)
1/ Trm th cp c ni vo ng dy v trao i khung I, U
B , RR - P(0) B , SIM - P B , RIM - F B , UA - F A Polls B B Request Initialization A Sets B to initialization mode B Acknowledges B is brought online through system procedures when initialization complete A Set B 's response mode.Nr and Ns counts are reset to 0 B Acknowledges A Polls B for transmission Duplex exchange of numbered I - Frame

B , SNRM - P B , RR - P(0) B , I(0) P (0)

B , UA - F

B , I(1) P (0) B , I(2) P (0)

B , I(0) F (0) B , I(1) F (2)

A Sends frame 1 A Sends frame 2. B confirms frame 0-1 and sends frame 1

B , I(3) P (1) B , RR - P(3)

B , I(2) F(3) B , RR - F(4)

A confirms frame 0 and sends frame 3 B confirms frame 2 and sends frame 2 A confirms frame 1-2 and Poll B B confirms frame 3 ( B remains in NRM)

----------------------------------------------------------------------------------------------------------------2/ Trm th cp bn
B , I(4) P (3) B , I(5) P (3) B , I(6) P (3) B , I(7) P (3) B , I(0) P(3)
B , RR - P(3) B , I(0) P (3) B , I(1) P (3) B , I(2) P(3)
A sends numbered I - Frames

B , RNR - F(0) B , RR - F(0)

B , RR - F(3)

A Polls B B becomes busy, but confirms frame 4-7 A asks if B is still busy B can receive again and expects frame 0 A sends frame 0 again A continues with frame 1 A sends frame 2 and poll B(gi thm d) B confirms frame 0 - 2 (B remains in NRM)

----------------------------------------------------------------------------------------------------------------3/ Trm s cp bn
B , SNRM - P B , RR - P(0) A sets B 's response mode and reset the Nr and Ns counts to 0 B , UA - F B Acknowledges A Polls B B , I(0) F (0) B sends numbered I - frame B , I(1) F (0) B , I(2) F (0) B , I(3) F (0) A becomes busy, but confirms frame 0 - 2 B , RR - F(0) B stops sending

B , RNR - P (3)

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A Polls B B retransmits frame 3 B , I(3) F (0) B sends frame 4 B , I(4) F (0) (CRC error) A has a CRC error on frame 4 B , RR - P(4) A Polls B, confirms frame 3 B , I(4) F(0) B sends frame 4 again A confirms frame 4 (B remains in NRM) B , RR - P (5) ------------------------------------------------------------------------------------------------------------------------------------

4/ Lnh khng c gi tr
A sends frame with an undefined C field. B rejects the frame Higher level at A processes the status reported by B in FRMR response. B ,SNRM - P A resets B 's error condition Nr and Ns counts are reset to 0. B , UA - F B acknowledges (B remains in NRM) ----------------------------------------------------------------------------------------------------------------------------------- B , FRMR - F B ,XXX- P

5/ S th t sai trong trao i song cng

B , RR - P(0) B , I(0) F (0)
B , I(1) F (0) B , I(2) F (0) (CRC error)
B , I(1) P (2)

A polls B for transmission B sends numbered I- frame

B , I(0) P (0)

Duplex exchange of numbered I - Frame

B receives frame 0 with CRC error A ' s frame 1 is out of numerical order (L ra phi pht li khung 0)

B , I(3) F (0) B , I(4) F(0) B , SREJ - F (0)

B , I(0) P (5)

B , I(5) F(0)

B , I(1) P (5)
B , RR - P(6)

B , RR - F(2)

B expects frame 0. A sends frame 0 again and confirms frame 0 - 4 B sends final I--frame A retransmits frame 1
A confirms frame 5 and polls B for confirmation B confirms frame 1 (B remains in NRM)

----------------------------------------------------------------------------------------------------------------Cc th d cho h multipoint

Cc trm th cp online, trm s cp gi tn hiu ti mt trm th v ng thi nhn tn hiu t mt trm khc 6/
B , RR - P B , SIM - P B , RIM - F B , UA - F A Polls B for status B asks for initialization mode A sets B to initalization mode B acknowledges B is brough on line through system procedures when initialization is complete A sets B on line. Nr & Ns counts are reset

B , SNRM - P

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B acknowledges A Polls n for transmission

n sends numbered frames to A while A sends to B

n , I(0) F (0)
B , I(0) P (0)
n , I(1) F (0) n , I(2) F (0) n , I(3) F (0)

B , RR - P(0) B , I(1) - P(0) B , RR - F(2) n , RR - P (4)

n completes its transmission of numbered frames A Polls B for confirmation B confirms 0 - 1 A confirms frames 0-3 (B&n remain in NRM)
A sends numbered frames to n A sends numbered frames to B A concludes sending to n and requests confirmation A continues sending to B, n confirms frame 0 - 1 A concludes sending to B and requests confirmation B confirms (B & n remain in NRM)

7/

n , I(0) P (4) B , I(2) P (0) n , I(1) P(4) B , I(3) P (0) B , I(4) P(0)

n , RR - F(2) B , RR - F(5)

V d 6, cc trm th cp c kt ni, trm s cp gi tn hiu ti mt trm trong khi nhn tn hiu ca trm khc V d 7, trm s cp gi tn hiu ti cc trm th cp.

6.2.2.4 So snh gia Bisynch v SDLC:

Bisynch l giao thc hng k t trong lc SDLC l giao thc hng bit. Bisynch c th dng m ASCII hay EBCDIC trong lc SDLC ch dng EBCDIC. d li, nu l ASCII th dng php kim tra khi (BCC) cn khi dng m EBCDIC th dng kim tra d tha theo chu k (CRC) vi chiu di m kim tra l 2 byte. C hai giao thc u dng chung kch thc khung thng tin l 256 byte. Bisynch c ch thng sut d liu ( trnh nhm ln d liu v k t iu khin) trong lc SDLC th dng phng php nhi bit ( trnh nhm ln vi m C).

6.2.2.5 Giao thc iu khin lin kt d liu cp cao (HDLC)

HDLC c ISO cho ra i nm 1975 nhm b sung mt s chc nng ca SDLC ca IBM. Mt s b sung c th k ra nh sau: - Trng a ch m rng, gm nhiu byte:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8n

------------(H 6.7) Trng a ch m rng

Trong trng a ch m rng, a ch xc nh bi mt s l bi ca 7 bit. Bit LSB trong mt byte l 0 hoc 1 (l 0 khi byte cha phi l byte cui cng v l 1 khi l byte cui cng ca trng a ch) 7 bit cn li hnh thnh a ch ca trm th cp (H 6.7). - Trng iu khin m rng, gm 2 byte (H 6.8): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Information 0 Ns P/F Nr Supervisory 1 0 S 0 0 0 0 P/F Nr Unnumbered 1 1 M 0 M P/F 0 0 0 0 0 0 0 0
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(H 6.8) Trng iu khin m rng

Trong trng iu khin m rng, cc s Ns v Nr gm 7 bit nh vy cho php pht mt ln 127 bn tin. - Dng khung d liu: SDLC ch dng m EBCDIC 8 bit cn HDLC cho php dng bt c loi m no - Dng khung gim st: ngoi cc lnh RR, RNRv REJ, HDLC c thm lnh SREJ (selective reject), lnh ny do th cp yu cu pht li mt khung c s Nr. - HDLC c thm 2 ch vn hnh: * Ch tr li bt ng b (Asynchronous Response Mode - ARM) : y l dng truyn khng cn bng. Trm th cp c th khi ng pht m khng cn lnh ca trm s cp. N c th tr li m khng cn phi nhn c mt khung vi bit P =1. Tuy nhin, khi n nhn c mt khung vi bit P =1 th khung tr li phi c bit F =1. Trong trng hp ny F=1 khng c ngha l khung cui cng ca trm th cp. - Ch khng kt ni bt ng b (Asynchronous Disconnect Mode - ADM) : ADM tng t nh DM ngoi tr mt im l trm th cp c th khi ng ch DM hay RIM bt c lc no.

6.3 Kho st vi IC LSI truyn ng b

Chng ta kho st di y hai IC tiu biu - USART 8251A ca Intel - SSDA 6852 ca Motorola

6.3.1 USART 8251A ca Intel

Bng 6.3 T Control v command
D7 D6 D5 D4 D3 D2 D1 D0 T SYN n SCS (Single character SYN) D t SYN bn ngoi ESD (External SYN Detect) Chn KT chn EP (Even parity Enable) Cho php KT chn l PEN (Parity Enable) Chn chiu di k t L1 L0 Chn h s chia CK B1 B0 1 = n 0 = Kp 1=Chn SYNDET l ng vo 0 = ng ra 1 = Chn 0 = l 1= C KT chn l 0 = Khng 00 = 5 bit 01 = 6 bit 10 = 7 bit 11 = 8 bit D1D0 00= Truyn . b 01 = :1 10 = :16 11 = : 64 Vo ch tm EH (Enter hunt mode) Reset ni IR (Internal Reset) Yu cu pht RTS Error reset ER Pht t break SBRK(Send Break Ch.) Cho php thu RxE DTE sn sng DTR 1 = Cho php tm t SYN 1 = Reset 8251A

1 = Chn RST thp 0 = cao 1 = Reset c li PE, OE, FE to 0 1 = Chn TxD thp 0 = Chn TxD cao 1 = Cho php 0 = Khng 1 = Chn DTR thp 0 = cao 1 = Cho php 0 = Khng

Cho php pht TxE Mode control word bit Command word bit Ghi ch: Reset li phi hon thnh khi RxEnable v Enter hunt c lp trnh

L IC thu pht ng b v bt ng b. Trong chng 4 ta kho st IC ny trong ch bt ng b, by gi chng ta tm hiu thm mt s tnh cht ca IC trong ch ng b. Vn hnh ch ng b 8251A c vn tc truyn ln ti 64 kbps. Chi tit cc thanh ghi iu khin, lnh v trng thi cho bng 6.3 v 6.4 IC hot ng ch ng b bit D0 v D1 trong thanh ghi iu khin = 00, cc bit D2, D3, D4, D5 nh trong phn bt ng b, bit D6 cho php chn thc hin ng b t bn trong hay bn ngoi v bit D7 cho php chn 1 hay 2 t SYNC
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- Chn SYN/BREAK ca IC trong ch ng b c th l ng ra hoc ng vo v ty thuc vo t iu khin trong chng trnh. Khi thc hin ch ng b bn trong th chn ny l ng ra, mc thp khi c reset v ln cao ch rng my thu nhn c t SYNC. Khi my thu thc hin tc v c trng thi th chn ny t ng reset. Khi thc hin ch ng b t bn ngoi th chn ny l ng vo, tn hiu dng n chn ny bo 8251A bt u nhn d liu Bng 6.4 8251A Status Register
D7 D6 D5 D4 D3 D2 D1 D0 Ghi bit TxEN - Bit TxRDY ln 1 khi thanh ghi m pht trng Data set ready 1 = DSR pin is low DSR 0 = high Sync. char. detect 1 = Sync. char. detect SYNDET (Synchronous only) Framing error 1 = Framing error reset by writing ER = 1 FE (Synchronous only) Overrun error OE 1 = Overrun error Parity error PE 1 = Parity error Trans. reg. Empty 1 = Empty Tx Empty 0 = Busy Receiver ready RxD 1 = Ready with new char. Trans. Ready TxD 1 = Ready for next char. ch : - TxRDY c ngha khc vi chn TxRDY . Chn TxRDY ph thuc trng thi chn CTS v

- 82251A ch pht ng b 8251A bt u pht d liu ngay sau khi CPU np t SYNC cho n khi khng cn tn hiu pht, thanh ghi m pht trng m CPU khng np k t k tip th 8251A t ng thm t SYNC vo v pht i - 8251A ch thu ng b - Khi s ng b c thc hin t bn trong, lnh ENTER HUNT phi c lp trnh trong t lnh u tin, vic ny khin 8251A d t SYNC trong dng d liu n, sau khi d ra USART chm dt ch HUNT v my thu trong tnh trng ng b ha, chn SYNDET ln cao bo cho P bit. - Khi s ng b c thc hin t bn ngoi, xung ng h di bit ca my thu c cp vo chn RxC . Xung ny thng c cp t modem v phi ng b vi dng d liu thu c. ch ng b, 8251A lm vic vi mt tn s c nh ca xung ng h (ch khng c chia nh ch bt ng b). Tn s xung ny phi ph hp vi vn tc truyn bit. - Khi ng 8251A Tng t nh ch bt ng b, ngoi tr k t SYNC phi c lp trnh nh sau - Reset chip: a chn RST ln cao (Reset cng) hoc set bt IR trong thanh ghi lnh = 1 (Reset mm) - Ghi m k t SYNC - Ghi t lnh Chn C/ D mc cao trong 3 ln ghi Byte ghi gia t chn mode v t lnh (command) cht vo USART l m k t SYNC - Pht mt k t Cng nh trong ch bt ng b, chn CTS phi mc thp v bit TxEn trong thanh ghi t lnh c set = 1 (cho php pht) - Ch bit TxRDY c set hay chn TxRDY ln cao
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- Ghi k t k tip vo thanh ghi m pht. Khi truyn xong k t cui cng ca khi, chn TxE (trans. empty) s High v bit TxEn c set, USART t ng pht t SYNC trong sut thi gian ngh Cc bit c di ra cng lc vi cnh xung ca tn hiu TxC . - Thu mt k t thu mt k t ch ng b cn thc hin cc bc: - Ghi t ENTER HUNT nh l mt phn ca lnh u tin vo thanh ghi t lnh - Ch chn SYNDET ln cao - Ch chn RxRDY ln cao hay bit trng thi tng ng c set (D1 thanh ghi trng thi = 1) - c k t t thanh ghi m thu - c trng thi li t thanh ghi trng thi Nhng bit li ca thanh ghi trng thi c reset nh t lnh c bit ER c set = 1 (D4 = 1). Cc bit d liu c di vo cng lc vi cnh ln ca xung ng h thu RxC - 8251A giao tip vi modem (H 6.9) l mt mu giao tip gia 8251A v modem, chun giao tip RS-449 c s dng. Xung ng h thu pht c cp t modem

(H 6.9)

6.3.2 SSDA 6852 ca Motorola

6852 ca Motorola l IC iu hp ng b ni tip (Synchronous Serial Data Adaptor, SSDA) loi NMOS 24 chn c ch to giao tip vi h vi x l 6800 ca Motorola trong ch ng b. (H 6.10) l s khi ca 6852

10 11 13 14 7 9 1 12 15

CS RS R/ W E IRQ RST Vss Vcc D7

Tx SHIFT REGISTER

TxD

Tx FIFO

Rx SHIFT REGISTER

RxD

Rx FIFO

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CONT. REG. 1 CONT. REG. 2 CONT. REG. 3 22 D0 SYNC. CODE REG. STATUS REGISTER TUF
8
CD CTS

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SM/ DTR 5

TxCLK RxCLK 4 3

23

24

(H 6.10)

ngha cc chn - CS , RS : Chip select, Register select - E : Data I/O enable & Clocking

- R/ W : Read/Write - IRQ : Interrupt Request

- D7 - D0 : Data bus I/O - RST : Reset - RxCLK, TxCLK : Receive Clock, Transmitter Clock - CTS : Clear to send - CD : Carrier detect - SM/ DTR : Sync. match/Data term ready: iu hp ng b/DTE sn sng - TUF : Trans. underflow - Vcc & Vss : Power & Ground -TxD,RxD : Transmit Data, Receive Data L IC ch c chc nng thu pht ng b, 6852 c mt s chi tit khng ging nh 8251A. c bit n c b m thu pht 3 byte hot ng theo kiu vo trc ra trc (First In, First Out, FIFO) . S dng b m ny 6852 c th vn hnh theo ch byte kp (Double-byte) ngha l CPU c th c hoc ghi ng thi 2 k t m khng phi i Vic chn ch vn hnh v iu khin SSDA u thng qua P bng cch ghi vo 3 thanh ghi iu khin. Cc trng thi li v bt tay c c t thanh ghi trng thi. V tr bit ca cc thanh ghi cho trong bng 6.5 v 6.6 Bng 6.5 Cc t trong thanh ghi iu khin ca 6852
bit 7 bit 6 Khng bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Xa c CTUF CLR CTS 1or2 SYNC char. select 1 / 2 sync Chn Sync trong hay ngoi E/I sync Control 1: Xa TUF 1: Clear CTS 1=1 t sync 0=2 t sync 1=Ngoi 0=Trong PC1 Reg.3 (CR3) Control s dng Cho php ngt khi c li EIE Pht t Sync khi underflow Tx Sync Word length selector WS3 WS2 WS1 Chn pht 1 hay 2 byte Bit iu khin ngoi vi PC2 1 = Cho php ngt PE, RxOvrn, TUF, CTS , CD 1 = Pht t Sync 0 = Pht bit 1 khi underflow 000-6 + parity chn 001-6 + parity l 010-7 bits 011-8 bits 100-7 + parity chn 101-7 + parity l 110-8 + parity chn 111-8 + parity l 1: 1 byte data I/O 0: 2byte Data I//O 00: SM/ DTR = 1 10: SM/ DTR = 0 01: SM/ DTR = xung ng b 11-SM/ DTR = 0 V hiu ha xung ng b Register 2 (CR2) Bit a ch AC2 00: Chn CR2 01: Chn CR3 10: T G m Sync 11: Chn TxFIFO Reg. (khi RS=1v R/ W =0 ) 1: Chn IRQ tc ng 1: Chn IRQ tc ng 1: Xa ng b 1: Loi t Sync t dng d liu thu 1= Reset pht

AC1 Cho php ngt thu RIE Cho php ngt pht TIE CLR sync Loi b t ng b Reset pht TxRS Reset thu RxRS Control

1= Reset thu

Reg.1(CR1)

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i vi P 6852 ch xut hin bng hai cch nh a ch (chn RS High v CS Low- Thng CS c ni vi ng a ch A0). T s khi ta thy c 7 thanh ghi trong 6852 c th c P truy xut. Ngoi tr thanh ghi iu khin 1, tt c cc thanh ghi khc u ch c th c hoc ch c th ghi ty chc nng Trng thi ca ng R/ W c dng chn nhm thanh ghi ch c hay ch ghi T bng 6.5 ta thy 2 bit c trng s ln nht trong thanh ghi iu khin 1 c dng nh a ch cc thanh ghi khc. Vic nh a ch c th tm tt nh sau:
Chn RS R/ W 0 1 0 0 1 1 1 0 1 0 1 0 1 0 Thanh ghi K1 b6 b7 x x x x x x 0 0 0 1 1 0 1 1 Chn thanh ghi Thanh ghi trng thi Thanh ghi K CR1 Thanh ghi Rx FIFO Thanh ghi K CR2 Thanh ghi K CR3 Thanh ghi m SYNC Thanh ghi Tx FIFO

Duyt qua cc bit trong thanh ghi trng thi v iu khin trong bng 6.5 v 6.6 ta thy c nhiu im tng ng vi 8251A. Mi khi my thu d ra t SYNC trong dng d liu n, chn SM xut hin xung c chiu di 1 bit ( ging nh chn SYNDET ca 8251A) Bng 6.6 6852 Status Register Word bits (SR)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Yu cu ngt IRQ Parity error PE Receiver Overrun Rx OVRN Transmitter Underflow TUF Clear to send CTS Carrier Detect CD Transmitter data register available TDRA Receiver data available RDA 1 = Chn IRQ tc ng 1 = C li parity Reset khi c RxFIFO or ghi vo CR1 vi RxRS = 1 1 = C li trn Reset khi c Status Reg. v RxFIFO hay ghi vo CR1 vi RxRS=1 1= C li Underflow Reset khi ghi vo CR3 vi CTUF v/hoc TxRS = 1 1= CTS t ln xa cui cng Reset khi ghi vo CR3 vi CTS v/hoc TxRS = 1 1 = CD t ln xa cui cng Reset khi c Status Reg. v RxFIFO hay ghi vo CR1 vi RxRS=1 1= C hiu lc Reset khi ghi vo TxFIFO 1 = C hiu lc Reset khi c RxFIFO

- Khi ng 6852 Khi ng 6852 bao gm cc bc sau : - Reset chip bng cch ghi t iu khin vo thanh ghi CR1 v xc nh a ch thanh ghi CR3 - Ghi t iu khin mong mun vo thanh ghi CR3 (chn s t SYN v ch ng b) - Ghi t iu khin vo thanh ghi CR1 duy tr iu kin reset v xc nh a ch thanh ghi CR2 - Ghi t iu khin mong mun vo thanh ghi CR2 - Ghi t iu khin vo thanh ghi CR1 duy tr iu kin reset v truy xut thanh ghi m ng b k tip - Ghi m mong mun vo thanh ghi m ng b
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- Ghi t iu khin mong mun vo thanh ghi CR1 (bao gm vic cho php thu v (hoc) pht) - Pht mt k t - CTS phi mc thp v bit TxRS phi c xa - Ch bit TDRA trong thanh ghi trng thi (Trans. Data Register Available) c set -Vit m k t pht vo b m TxFIFO Chu trnh c lp li cho ti khi c khi d liu c pht. Nu CPU khng cung cp Data nhanh my pht pht, ta ni my pht tnh trng underflow v bit TUF ln cao, lc SSDA t ng thm t SYNC vo pht i. Bit TUF l mt c c reset bi bit b3=1 trong CR3 Cc bit c di ra ngoi khi c cnh xung ca xung ng h ti ng vo TxCLK - Thu mt k t thu mt k t ng vo CD phi LOW v bit RxRS phi c xa. Cc bit ti my thu c so snh vi m SYNC trong thanh ghi m ng b n khi c s tng ng (nhn dng t SYNC) - Ch cho ti khi RDA c set - c trng thi li trong thanh ghi trng thi - c m k t t b m RxFIFO Cc bit d liu c ly mu cnh ln ca xung clock thu ti chn RxCLK.

6.4 KIM TRA H THNG THNG TIN

Mt h thng thng tin trc khi a vo vn hnh cng nh trong qu trnh s dng lun cn c kim tra thng xuyn bo m tnh chnh xc v tin cy. - Kim tra tng t thng c thc hin i vi mt h thng chun b a vo s dng - Kim tra s thng c tin hnh thng xuyn nh gi cht lung ca h thng m khng cn phi ngt h thng trong mt thi gian di

6.4.1 K thut tng t - Php o t s PAR

Tn hiu trn mt ng truyn thng b bin dng do hai nguyn nhn: suy gim bin theo tn s v s bin dng do tr pha. Vic o c hai i lng ny rt tn km thi gian v c thc hin trong sut thi gian nghin cu h thng, y khng phi l mt cng vic thng ngy. Php o t s PAR l mt phng php th nhanh v cho php ta nh gi c h thng. y l php o t s tr nh v tr trung bnh ca tn hiu nhn c (Peak to average Ratio) K thut PAR dng mt my pht v mt my thu ni nhau qua h thng truyn trn bng tn m thanh. My pht pht tn hiu kim tra l mt chui xung, my thu nhn tn hiu xung ny, s suy gim bin v bin dng pha trong h thng lm tiu hao nng lng ca tn hiu v do lm gim t s gi tr nh EPK trn tr trung bnh ca tn hiu chnh lu ton k EFWA (Full Wave Average). T s ny l gi tr PAR
2EPK 1) * 100 EFWA Nu tn hiu hon ton khng bin dng, t s ny l 100%

% PAR = (

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Nu c bin dng vi tr s chun ha l 0,75 th gi tr PAR l 50%. y l gi tr chp nhn c vi h thng c vn tc truyn ln ti 2400 bps. Gi tr PAR nhy i vi bin dng do suy gim bin , do tr pha, do nhiu nn cao, do h thng khng tuyn tnh v cc ha tn ca tn hiu . . . ..

6.4.2 Php o bin dng dng biu mt

Mt phng php o bin dng rt hu hiu trong h thng truyn d liu l dng biu mt (Eye pattern). - Biu mt : Dng mt tn hiu xung clock c gi tr br (tc tn s) xc nh, dng kch khi mch qut ngang mt dao ng nghim v tn hiu s cn kim tra l cc tn hiu 1 , 0 thay i mt cch tun t c a vo bn lch dc ca dao ng nghim. Mt biu mt c dng nh (H 6.11) xut hin trn mn nh dao ng nghim

(a)

(H 6.11)

(b)

S hnh thnh biu mt c th hiu l s chng cht ca cc tn hiu 1, 0 thay i lin tc to ra. (H 6.12) minh ha s hnh thnh ny

(H 6.12)

Nu tn hiu xung vo dao ng nghim gn nh l tng th biu mt c dng gn ging nh hnh ch nht, ta ni biu mt hon ton m (H 6.11.a) Trong thc t bin dng khng th no trnh khi hon ton v biu mt ng li (H 6.11.b). Giao im ca cc bin i t 1 xung 0 v ngc li c gi l giao im 1/0. S thay i theo chiu ngang ca giao im 1/0 l s bin ng (jitter). (H 6.13) cho thy cc gi tr bin ng khc nhau ca biu mt. (H 6.13.a) l trng hp khng c bin ng, (H 6.13.b) bin ng khong 5%, (H 6.13.c) khong 10%, (H 6.13.d) khong 20%, (H 6.13.e) khong 50% v (H 6.13.f) > 50%. S bin ng cng ln biu mt cng khp li, vy kch thc ca vng m ti trung tm biu mt cho ta cht lng ca h thng.

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(H 6.13)

Vic nh gi cht lng tn hiu bng biu mt ch cho kt qu tin cy c khi : - Tn hi 1, 0 to bi mch phi i xng. - ng dy phi iu hp tng tr trnh sng phn x. - Thi gian tr ca tn hiu khi chuyn t mc 0 ln 1 hay ngc li phi bng nhau. Nu mt trong cc iu kin trn khng tha th cht lng tn hiu st gim v vic nh gi khng cn chnh xc.

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