DLD-06

1/7

Experiment DLD-06:

A Simple Calculator

1.



( 4-it
adder, 4-bit subtractor, quad 2-to-1 multiplexer
7-segment decoder)
2.

3.



FPGA

CMOS 4000 TTL
74LS00 6.1

178 221 Digital Logic Design Laboratory

DLD-06

2/7

(a) TTL 74LS08

74LS08

(b)

6.1 CMOS TTL

Programmable Logic Device
(PLD)
FPGA
FPGA (Field Programmable Gate Array)
PLD
(Schematic)
Verilog VHDL

178 221 Digital Logic Design Laboratory

DLD-06

3/7

Calculator

6.2 Calculator

178 221 Digital Logic Design Laboratory

DLD-06

4/7

6.3 ALU

1. Project

Calculator ISE WebPACK
2. 4-bit Full
Adder, 4-bit Full Subtractor, Quad 2-to-1 Multiplexer
2-to-1 Multiplexer DLD-04 Binary to 7Segment Decoder BCD to 7-Segment Decoder
DLD-05 Project > Add Copy of Source

( sch sym)

3. Calculator 6.2
ALU 6.3
4. Test Bench WaveForm

truth table

5.

6.4

Calculator Hardware
(FPGA)

6. Project

Calculator ISE WebPACK
7.

Sources

Properties 6.4
178 221 Digital Logic Design Laboratory

DLD-06

5/7

8. Project Properties

Hardware
Family : Sparton3
Device : XC3S200
Package : TQ144
Speed : -4

9.

Calculator
Processes
Run User Constraints > Edit Constrains (Text)
... Hardware

NET "A3"

LOC = "p52";

# Input A3(MSB)

NET "A1"

LOC = "p55";

# Input A1

NET "A2"
NET "A0"
NET "B3"
NET "B2"
NET "B1"
NET "B0"

LOC = "p53";
LOC = "p56";
LOC = "p59";
LOC = "p60";
LOC = "p63";
LOC = "p68";

NET "SEL" LOC = "p44";

# Input A2

# Input A0(LSB)

# Input B3(MSB)
# Input B2
# Input B1

# Input B0(LSB)

# Input Select (Add/Sub)

NET "SEG_A"

LOC = "p40";

# Output Segment A

NET "SEG_C"

LOC = "p32";

# Output Segment C

NET "SEG_B"

NET "SEG_D"
NET "SEG_E"
NET "SEG_F"

NET "SEG_G"

LOC = "p35";
LOC = "p30";
LOC = "p27";
LOC = "p25";
LOC = "p23";

# Output Segment B

# Output Segment D
# Output Segment E
# Output Segment F

# Output Segment G

178 221 Digital Logic Design Laboratory

DLD-06

NET "SEG_DP"
DP

LOC = "p20";

NET "disp1" LOC = "p31";

Output

6/7

Segment

# Output Show DIGIT0

NET I/O Marker LOC =

Hardware;

I/O Marker
I/O Marker

10.
Processes

Synthesize XST Run

Synthesize

XST > View Synthesis Report

11. Implement Design
Processes

+
Implement Design -
Run Implement Design

Implement Design Translate, Map,

Place & Route Implement Design
12. JTAG
JTAG
FPGA D3 XC3S200F

178 221 Digital Logic Design Laboratory

DLD-06

7/7

13.
Processes
+
Generate Programming File
-
Run Generate Programming
File
Programming File

Generate

Programming File Generate

Report
14. Run Generate Programming File > Configure
Device (iMPACT) iMPACT Welcome
to iMPACT Finish Assign New
Configuration File

*.mcs Bypass Assign New
Configuration File *.bit
Open
15. iMPACT

XC3S200
Program OK

16.
17.

..

178 221 Digital Logic Design Laboratory