A Project Report On "Voltage Mode Control of Buck Converter"

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A PROJECT REPORT ON VOLTAGE MODE CONTROL OF BUCK CONVERTER
PROJECT ASSOCIATES Anusha A. N (4NM09EE008) Arpan Chatterjee (4NM09EE009)
Ashutosh Kumar (4NM09EE010)
Manish Kumar (4NM09EE031)
Under the guidance of
Mr. Suryanarayana K. Assistant Professor, Dept. of Electrical and Electronics Engineering NMAMIT, Nitte
Project Report submitted to NMAM Institute of Technology, Nitte An Autonomous Institution affiliated to VTU Belgaum, in partial fulfilment for the award of Bachelor of engineering in Electrical and Electronics Engineering
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
NMAM INSTITUTE OF TECHNOLOGY

(An Autonomous Institution affiliated to VTU, Belgaum) (NBA Accredited, ISO 9001:2008 Certified) Nitte 574110, Karkala, Udupi District, Karnataka, India
Department of Electrical and Electronics Engineering
CERTIFICATE
Certified that the project work entitled Voltage Mode Control of Buck Converter is a bonafide work carried out by Anusha A.N (4NM09EE008), Arpan Chatterjee (4NM09EE009), Ashutosh Kumar (4NM09EE010) and Manish Kumar (4NM09EE031) in partial fulfillment for the award of Degree of Bachelor of Engineering in Electrical and Electronics Engineering of the Visvesvaraya Technological University, Belgaum during the year 2012-2013. It is certified that all corrections / suggestions indicated for Internal Assessment have been incorporated in the report deposited in the departmental library. The project report has been approved as it satisfies the academic requirements in respect of project work prescribed for the Bachelor of Engineering Degree.
Signature of Guide
Signature of HOD
Signature of Principal
Semester End Viva Voce Examination
Name of the Examiners 1. _______________________________
Signature with Date ________________________________
2. _______________________________
________________________________
ABSTRACT
The objective of this project is to design and develop a buck converter circuit using PID Compensator to get a stable output of 5V, 5A from an input of 12V. The Buck-converter converts an input voltage into a lower output voltage, it is also called step-down converter. The buck converter is designed in continuous current conduction mode. To get the regulated output voltage, compensation mechanism using voltage mode control is used. This project involves simulation, design and hardware construction of voltage mode control of buck converter using PID compensator. The simulation of the circuit is done using Orcade (PSpice). MATLab is used to study stability analysis of the closed loop system and to get the desired phase and gain margin. The PID compensator is designed by modifying the open loop buck converter circuit obtained from the simulation in Orcade (PSpice). The error signal is compared with a saw-tooth ramp voltage and desired PWM signal. The compensator and PWM scheme is implemented using NXP LPC1768.
ACKNOWLEDGEMENT
We would like to take the opportunity to appreciate the help and support rendered to us by Mr. Suryanarayana K., Assistant Professor, Dept. of E&E in completing this project successfully under his guidance and for helping us procure some of the components required for this project. We also thank Mr. Pradeep Kumar, Assistant Professor, Dept. of E&E, for his valuable suggestions and help rendered to us. We are grateful to our principal Dr. Niranjan N. Chiplunkar and Prof. K. Vasudev Shettigar, HOD, Dept. of E&E for extending encouragement and providing adequate facilities in carrying out this project. We are grateful to all the teaching and non-teaching staff of the Dept. of E&E, and friends who have helped us through the course of this project.
Nitte April 2013
PROJECT ASSOCIATES:
Anusha A.N (4NM09EE008)
Arpan Chatterjee (4NM09EE009) Ashutosh Kumar (4NM09EE010) Manish Kumar (4NM09EE031)
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TABLE OF CONTENTS
CHAPTERS TITLE ABSTRACT ACKNOWLEDGEMENT TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES 1 INTRODUCTION 1.1 Project Background 1.2 Project Objective 1.3 Project Scope 2 BUCK CONVERTER DESIGN AND OPERATION 2.1 Operation of Buck Converter 2.2 Calculation of L and C 2.3 Converter Power Stage Calculation 2.3.1 Calculation of Unknown Parameters 2.3.2 Calculation for Inductance 2.3.3 Calculation for Capacitance 2.3.4 Buck Converter Diode Selection 2.3.5 Buck Converter MOSFET Selection 2.3.6 Buck Converter Efficiency 3 COMPENSATOR DESIGN AND TRANSFER FUNCTION 3.1 Introduction 3.2 Buck Converter in Voltage Mode Control 4 HARDWARE DESIGN AND SIMULATION 4.1 Pulse Width Modulation 4.2 Buck Converter Simulations 4.3 NXP LPC1768 Microcontrollers PAGE NO. i ii iii v vii 1 1 3 3 5 5 8 9 10 10 11 11 11 12 13 13 14 24 24 24 32
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4.3.1 Overview 4.3.2 Features 4.3.3 Tools and Software 4.3.4 Technical References 4.3.5 Hardware Overview 4.3.6 Major Functional Block 4.3.7 Memory 4.3.8 Implementation 5 CONCLUSION AND FUTURE PROSPECTS 5.1 Conclusion 5.2 Future Prospects REFERENCES APPENDIX- DATA SHEETS
32 33 33 34 35 36 36 37 38 38 38 39 40
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LIST OF FIGURES
FIGURE NO. 1.1 1.2 2.1 2.2 2.3 2.4
TITLE Basic Buck Converter Voltage Mode Control Buck Converter When switch is closed When switch is open Voltage and current waveform of buck converter
PAGE NO. 1 2 5 5 5 6
3.1
Voltage mode control of buck converter
14
3.2
Block diagram of Buck converter
14
3.3 3.4
Type III Compensator open loop control to output transfer function
17 19
3.5 3.6 3.7 3.8
bode diagram bode diagram bode diagram closed loop bode diagram
20 20 21 21
3.9
Output impedance diagram
bode
22
3.10
Closed loop diagram
bode
22
4.1 4.2
PWM Control Simulation of open loop buck converter in PSpice
23 24
4.3
Inductor Current and Output Voltage Waveform
24
4.4
Inductor Current
25
Waveform 4.5 4.6 Output Voltage Waveform Inductor Current Waveform after Zoom area 4.7 4.8 Output Current Waveform Inductor Voltage Waveform 4.9 Gate Pulse for the MOSFET 4.10 4.11 4.12 4.3.1 4.3.2 Voltage across Diode Current across Diode Output Power Waveform NXP LPC1768 Block Diagram of NXP LPC1768 4.3.3 Pin Diagram of NXP LPC1768 32 26 27 27 28 31 26 25 26 25 25
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LIST OF TABLES
TABLE NO. 1.1 TITLE DESIGN SPECIFICATION OF BUCK CONVERTER 2.1 INDUCTOR AND CAPACITOR VALUE (CALCULATED) 2.2 ESTIMATED SYSTEM LOSS 3.1 COMPENSATION COMPONENTS VALUE 19 12 11 PAGE 4
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VOLTAGE MODE CONTROL OF BUCK CONVERTER
CHAPTER 1: INTRODUCTION
This chapter describes the project background, objectives, and the scope. In the project background, a brief description of the buck converter and the voltage-mode controller as well as the objective and the scope of the project are studied.
1.1
Project Background
Direct current to direct current (DC-DC) converters in power electronics circuits are those which convert direct current (DC) voltage input from one level to another. DCDC converters are also known as switching converters, switching power supplies or switches. DC-DC converters are important in portable devices such as cellular phones and laptops [1].
Figure 1.1: Basic Buck Converter The Figure shows a simple buck converter which accepts a dc input and uses pulsewidth modulation (PWM) of switching frequency to control the output of a power MOSFET. A diode together with an inductor and a capacitor produces the regulated dc output. Buck or step down converters produce an average output voltage lower than the input source voltage. The buck converter is the most widely used dc-dc converter topology in power management and microprocessor voltage-regulator (VRM) applications. These applications require fast load and line transient responses and high efficiency over a wide range of load current. They can convert a voltage source into a lower regulated voltage source. For example within a computer system, voltage needs to be stepped
Department of Electrical & Electronics Engineering, NMAMIT, NITTE 1
down and a lower voltage needs to be maintained. For this purpose the Buck Converter can be used. Furthermore buck converters provide longer battery life for mobile systems that spend most of their time in stand -by. Buck regulators are often used as switch-mode power supplies for baseband digital core and the RF power amplifier. Suppose we want to use a device with low voltage level and if devices such as laptop or charger is directly connected to the rectified supplied from the socket at home, the device might not function properly or it might be broken due to over current or overvoltage. Therefore to avoid unnecessary damage to the equipments and devices, we would need to convert the voltage level to suitable voltage level for the equipments to function properly. In this project, the configuration of DC-DC converter chosen for study was buck configuration. Buck converter converts the DC supply voltage to a lower DC output voltage level. The buck converter targeted is suitable for low power application due to the low voltage and current level at the output (25 watts).
Figure 1.2: Voltage Mode Control The control method chosen to maintain the output voltage from the buck converter is voltage-mode control and is shown in figure 1.2. Voltage mode has a single voltage feedback path with pulse width modulation performed by comparing the voltage error signal with a constant ramp waveform. The difference between both the voltages will drive the control element to adjust the output voltage to a desired voltage level. This is called as output voltage regulation. Voltage regulation is very important in electronic circuit to ensure that the load or the connected device can operate properly and to avoid damage to the equipment from overvoltage and over current.
1.2
Project Objective
The main objective of this project is to design a buck converter to convert the input DC voltage to lower DC output voltage level for low power applications to solve the problem of voltage regulation and high power loss of the linear regulator circuit. Basically we design a buck converter circuit using PID Controller to get a stable output of 5V, 5A from an input of 12V. The converter uses switching scheme which operates the switches such as MOSFET in cut-off and saturation region to reduce power loss across the MOSFET. The output voltage level is then regulated by the voltage-mode control circuit to a desired output voltage level as shown in the design specification in the table 1.1 below. The design specification is based on low power applications such as laptop battery charger, hand phone charger etc. The circuit is simulated by using PSpice software to obtain the desired power stage response.
1.3
Project Scope
The scope of this project is: I. II. III. IV. V. VI. Study the operation of buck converter. Study the operation of voltage-mode control circuit. Simulation of buck converter frequency response using PSpice software. Designing the buck converter power stage circuit. Designing the controller and compensator circuit. Testing and calibration of the completed buck converter to confirm the actual response with the theoretical predictions.
Department of Electrical & Electronics Engineering, NMAMIT, NITTE
Table 1.1: Design specification of buck converter power stage
Topology
Buck Converter
Inductance (L)
100 F
Frequency (
10 kHz
Critical inductance (
49.64 H
Output voltage (
5V
Output current (
5A
Output voltage ripple (V)
45 mV
Output current ripple (I)
1.5 A
Equivalent series resistance (ESR)
DC input voltage (Vin)
12 V
Switch selection
IRF520 metal-oxide-semiconductor fieldeffect transistor (MOSFET)
CHAPTER 2: BUCK CONVERTER OPERATION AND DESIGN 2.1 Operation of Buck Converter
The operation of the buck converter is simple, with an inductor and two switches (usually a MOSFET and a diode) that control the inductor. It alternates between connecting the inductor to source voltage to store energy in the inductor and discharging the inductor into the load.
Figure 2.1: Buck Converter Figure 2.1 shows the circuit diagram of a Buck-converter. The MOSFET M1 operates as the switch, which is turned on and off by a pulse width modulated (PWM) control voltage VPWM. The ratio of the on time (ton) when the switch is closed to the entire switching period (Tsw) is defined as the duty cycle . (2.1)
.................................................................
Figure 2.2: When the switch is closed
Figure 2.3: When the switch is open

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The equivalent circuit in Figure 2.2 is valid when the switch is closed. The diode is reverse biased, and the input voltage supplies energy to the inductor, capacitor and the load. When the switch is open as shown in Figure 2.3 the diode conducts and the capacitor supplies energy to the load, and the inductor current flows through the capacitor and the diode. The output voltage is controlled by varying the duty cycle. In steady state, the ratio of output voltage to the input voltage is D, given by Vout/ Vin. Vcont Tsw ton t
V1 Vout=V1 t VL
(Vin-Vout) -Vout t
IL ILmax IL ILoad=IL ILmin t
Figure 2.4: Voltages and Currents Waveform of the Buck Converter

In the figure 2.4 the analysis is assumed that the conducting voltage drop of the MOSFET and the diode is zero. During the on-time of the MOSFET voltage V1 is equal to Vin. When the transistor switches off (blocking phase), the inductor L continues to drive the current through the load in parallel with C and the diode, consequently the voltage V1 becomes zero. The voltage V1 stays at zero during the off-time of the transistor provided that the current IL does not reduce to zero. This mode of operation is called continuous mode. In this mode V1 is a voltage which changes between Vin and zero, corresponding to the duty cycle of Vcont. The low-pass filter formed by L and C, produces an average value of V1 i.e. Vout = V1, therefore for continuous mode ............................................ (2.2) For the continuous mode the output voltage is a function of the duty cycle and the input voltage, and it is independent of the load. The inductor current IL has triangular shape and its average value is determined by the load. The peak-to-peak current ripple IL is dependent on L and can be calculated as: V = Ldi/dt i = Vt/L IL = (Vin-Vout)ton/L = Vout(Tsw-ton)/L For mode: The current ripple IL is independent of the load. The average of the current IL is equal to the output current Iout. the current IL becomes zero in every and a switching frequency Fsw, it follows that for the continuous
At low load current, in case that
switching cycle. This mode is called discontinuous mode and for this mode, these calculations are not valid.
2.2 Calculation of L and C:

To ensure the continuous current mode of conduction, the selected value of inductance should be greater than the critical value of the inductor Lc which acts as a boundary condition for continuous and discontinuous current mode of operations. The critical value of inductance is given by,
( )
........................................ (2.3)
The inductor value must be chosen by considering the fact that the magnitude of the ripple current in the output capacitor as well as the load current is determined by the appropriate inductor value. Hence, normally a ripple current of 10% to 20% of the average output current is assumed for the design to achieve good performance of the converter [7]. The value of inductor is determined by, ( ) ( ) ............................ (2.4)
The capacitor value is determined by assuming the output voltage ripple as 1% to 2% of the output voltage. The capacitor value is determined by, ........................................................................ (2.5) To calculate the value of L , a realistic value of IL has to be selected. If IL is selected at a very low value, the value of L has to be relatively high and this would require a very heavy and expensive inductor. If IL is selected at a very high level, the switch-off current of the MOSFET would be very high which would result in high losses in the MOSFET. A good and usual compromise between these effects is: ............................................................ (2.6) For L it follows: ( ) ( ) ( ).............................. (2.7)
The maximum value of the inductor current is: .................................................. (2.8)

Assuming that the inductor ripple current is small compared to its dc current the RMS value of the current flowing through the inductor is given by:
........................................................ (2.9)
The capacitor C is chosen usually for a cut-off frequency of the LC-low-pass filter, which is approximately 100 to 1000 times lower than the switching frequency. An exact calculation of the capacitor depends on its maximum rating of the AC current and its equivalent series resistance ESR both can be verified from the relevant data sheet. The current ripple IL causes a voltage ripple Vat the output capacitor C. For normal switching frequencies, this voltage ripple is determined by the equivalent series resistance ESR. The output voltage ripple is given by: ....................................................................... (2.10)
2.3 Converter Power Stage Calculation

For a Buck converter, we will calculate the required inductor and output capacitor specifications. We will then determine the input capacitor, diode, and MOSFET characteristics. With the selected components, we will calculate the system efficiency. The conventional buck converters are designed for the following specifications: Input Voltage, Output Voltage, Load Current, Switching Frequency, V
2.3.1 Calculations of Unknown Parameters

Output resistance, =5/5= 1Ohms
Using equation (2.2), Duty Ratio, D =0.416 Peak-Peak ripple current is limited to 30% of load current, Using equation (2.6), Switching period, =100s
Switch ON time, ton=D/Fsw= 0.416/10k= 41.6s
2.3.2 Calculation for Inductance Critical value of inductor:

Using equation (2.3), H
Inductor value (30% ripple current) Using equation (2.7), L=194H Let us choose value of inductor= 100H Inductor peak current (30% ripple current): Using equation (2.8), Inductor RMS current: Using equation (2.9), The power dissipated due to copper losses is: 0.75 Watt
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2.3.3 Calculation for Capacitance

Using equation (2.10), Ripple voltage V= 45mV Using equation (2.5), Capacitance C = 417F Let us choose value of capacitor as 470F. The estimated power dissipation in the capacitor is:
Table 2.1: Inductor and Capacitor Value (calculated)
2.3.4 Buck Converter Diode Selection

Estimate Diode Current: ( Power Dissipation: VFID = 1.168 Watt We have selected schottky diode 1N5826 of 15A, 20-40 volts. Forward voltage drop for selected diode is 0.47V at peak current of 15A. Maximum diode reverse voltage is 20V. )
2.3.5 Buck Converter MOSFET Selection

( )
) (
) = 0.717 Watt = 0.925 Watt
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2.3.6 Buck Converter Efficiency

Output Power =25 Watt
Efficiency = 25/(25+2.9105) = 89.57 % Table 2.2: Estimated System Loss
Components
Value
Units
Output power
25
Watt
MOSFET loss
0.925
Watt
Diode loss
1.168
Watt
Inductor loss
0.75
Watt
Capacitor loss
0.0675
Watt
Total loss
2.9105
Watt
Efficiency
89.57
This Buck converter design example has a calculated efficiency of 89.57%.If the diode forward voltage drop could be lowered, the converters efficiency could be raised. This buck converter design example is called an Asynchronous Buck converter because the diode commutation (switching) is independent of the MOSFET switching.
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CHAPTER 3: COMPENSATOR DESIGN AND TRANSFER FUNCTION

3.1 Introduction
The easiest way to obtain a digital controller is first to design an analog compensator and transpose it in the digital domain using the bilinear transformation. The disadvantages of such a method are the mathematical calculus needed to obtain the values of the passive components for the compensator and the fact that if the designer decides to change the hardware, the calculus must be reevaluated. In this chapter, a type III analog controller with its time domain transfer function and frequency response is given. The analog compensator was designed without any adjustments only by placing the position of the poles and zeros by a first approximation based on the buck converters passive components. The type III digital controller is obtained from the transfer function of an analog type III controller transposed into digital domain using the bilinear transformation. After mathematical calculations, the z-coefficients for the linear difference equation needed to implement the compensator in a microcontroller are obtained. These coefficients are dependent only on the pole-zero placements. The pole-zero placements are obtained from calculation similar to the analog design using only the given values of the converter parameters. The advantage of this digital compensator is that the user does not need to calculate anything if he wants to close the loop for a converter, the only data needed to be transferred to the controller are the parameters of the converter. The control mode used in this project is voltage mode control. The models are first simulated and the results are compared and then the experimental results are presented.
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3.2 Buck Converter in Analog Voltage Mode Control
Figure 3.1: Voltage mode control of buck converter In figure 3.1, a buck converter in voltage mode control is given. In voltage mode control an external signal is compared with the control signal obtained for generating the duty cycle needed to have the wanted output voltage. The output voltage Vout is monitored and subtracted from the reference value V ref and an error signal Vcomp results. This error signal is then used for the resulting control signal. The control signal is then compared with the external ramp voltage Vramp and a pulse width modulated signal is sent to the drivers of the MOSFET so that converter can react in such a way so as to reduce the output error [2], [3], [4], [5].
Figure 3.2: Block diagram of buck converter
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The transfer function of power stage can be calculated as ratio of the output voltage to duty cycle and given as: ( ) ( )
( ) .. ( ) ( ( ) [ { ( ) ) }] (
(3.1)
(3.2)
The (s) indicates that the transfer function varies as a function of the frequency. The transfer function of the PWM modulator is , where is the peak to
peak voltage of modulator. For simplification, we can combine the transfer function of the PWM modulator and the buck converter power stage as: ( ) ( ) ... (3.3)
Therefore, G(s) is usually referred to as the transfer function of the power stage. The roots of the polynomial in the denominator of (3.2) are called the poles of the transfer function of the power stage. Similarly the roots of the numerator of (3.2) are the zeros of the transfer function of the power stage. The transfer function of the power stage is a second order system with a double pole at the resonance frequency (of the LC filter) and a zero produced by the ESR of the capacitor. Line to output transfer function is given as:
( )
( )
.... (3.4)
Open loop transfer function:

( ( )( )( )( )( ) )
( )
. (3.5)
The pole located at
cancels the zero located at FESR and the pole at Fp2 is located
well above crossover frequency. Output impedance is given as: ( )

( )
( )............................................................... (3.6)
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The parameter
is the inductor zero frequency and
( )
Closed loop output impedance is given as: ( )

( )
( )
....................................................................... (3.7)
The closed loop line to output TF: ( )

( )
( )
.... (3.8)
The open loop control to output voltage TF in Laplace domain is given by equation (3.2) .... (3.9)
( )
Frequency of double poles: .. (3.10)
( (
Frequency of zeros: .. (3.11) PWM modulator gain and given by:

( ) ( )
is inversely proportional to the peak to peak ramp voltage
(3.12)
The compensator transfer function from output voltage to COMP node is given as:
( )
( (
)( )(
. (3.13)
(3.14)
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Figure 3.3: Type III compensator The type III compensator produces two zeros and three poles. One pole is located at the origin to realize high DC gain and the relevant components values are given as: Loop gain crossover frequency: .. (3.15) The loop gain crossover frequency is usually selected between to of the
switching frequency. It is the zero crossover frequency defined as frequency when loop gain is unity. Since .. (3.16) So type III-B compensator is suitable for this project. The poles and zeros of the compensator will be placed as follows: .. (3.17) The type III compensator has 3 poles and 2 zeros. ... (3.18)
. (3.19)
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is usually chosen as
and this is about the maximum phase-lead obtained from
a lead compensator. The other zero of the compensator is chosen using the following formula: .. (3.20) .... (3.21) .. (3.22) .... (3.23) .. (3.24)
( )
... (3.25) .. (3.26) Considering = 2.2 nF and using equation from (3.15) to (3.26), we got the
following compensator value as shown in table below.
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Table 3.1: Compensation components values
Components Rc1 Rc2 Cc1 Cc2 Cc3 RFB1 RFB2
Value 33 7.5 32 947 2.2 475 475
Units k k F pF nF k k
Figure 3.4:
Open loop control to Output transfer function
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Figure 3.5:
Bode diagram
Figure 3.6:
Bode diagram
20
Figure 3.7:
Bode Diagram
Figure 3.8: Closed Loop
Bode Diagram
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Figure 3.9: Output impedance
Bode Diagram
Figure 3.10: Closed loop output impedance
Bode Plot
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// Matlab program
clc; clear all; num=[1.69*10^-4 12]; den=[4.7*10^-8 2.17*10^-4 1]; t=0.0001; fs=1/t; [b,a]=bilinear(num,den,fs) x0=1; x1=0; x2=0; y1=0; y2=0; y0 = zeros(40,1); for i=1:40 y0(i) = -a(2)*y1-a(3)*y2 + b*[x0;x1;x2]; y2 = y1; y1 = y0(i); x2=x1;x1=x0;x0=1; end subplot(211); stem(y0); y = filter(b,a,[1;zeros(39,1)]); subplot(212); stem(y);
Figure 3.11: Bode plot
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CHAPTER 4: HARDWARE DESIGN AND SIMULATION

4.1 Pulse Width Modulation
Figure 4.1: PWM control Pulse Width modulation is a way to control the switch as shown in Figure 4.1 above. The control signal is compared to a repetitive reference waveform at the desired frequency. The switch control signal changes according to the output of the comparison. The switch signal can be viewed as a pulse train with two states: on and off. The Pulse Width Modulation is the method where the width of the on-part and off-part of the switch signal are modulated to get the desired behaviour. In other words, the method decides for how long the switch will be turned on [1].
4.2 Buck Converter Simulations

The buck converter power stage shown in Figure 4.2 is simulated using PSpice software to obtain the output voltage and current response. The pulse-width generator equivalent generates the pulse-width modulation to control the N-channel MOSFET to either switch it on or off. TFis the time for the pulse to fall to zero and TR is the time for the pulse to riseto+20 V value. PW is the time for positive pulse-width, PER is the period for one complete cycle, Duty cycle is the positive duty cycle and switching frequency is the desired switching frequency for the MOSFET. The components value of the power stage is selected to be the same with the selected values in Table 2.1. Load is selected to be 1 ohm and the input voltage is set to 12
V. The current probe and voltage probe is used to measure the voltage and current at the inductor and the load respectively. From the waveform shown in the figure (4.2) to (4.3), it is clear that the converter is operating in the continuous conduction mode. The output voltage equals 4.3399 V and output current is 4.3550 A. The output power is 19.107 W. The related waveforms obtained from the simulation are shown as below.
Figure 4.2: Simulation of open loop buck converter in PSpice
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Figure 4.3: Inductor current and output voltage waveform
Figure 4.4: Inductor Current Waveform
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Figure 4.5: Output Voltage Waveform
Figure 4.6: Inductor current waveform after zoom area
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Figure 4.7: Output Current Waveform
Figure 4.8: Inductor Voltage Waveform
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Figure 4.9: Gate Pulses for the MOSFET
Figure 4.10: Voltage across diode
29
Figure 4.11: Current across Diode
Figure 4.12: Output Power Waveform
30
Figure 4.13: Buck converter
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4.3 NXP LPC1768 Microcontroller 4.3.1 Overview

The mbed Microcontrollers are a series of ARM microcontroller development boards designed for rapid prototyping. The mbed NXP LPC1768 Microcontroller in particular is designed for prototyping all sorts of devices, especially those including Ethernet, USB, and the flexibility of lots of peripheral interfaces and FLASH memory. It is packaged as a small DIP form-factor for prototyping with through-hole PCBs, strip board and breadboard, and includes a built-in USB FLASH programmer.
Figure 4.3.1: NXP LPC1768 It is based on the NXP LPC1768, with a 32-bit ARM Cortex-M3 core running at 96MHz. It includes 512KB FLASH, 32KB RAM and lots of interfaces including built-in Ethernet, USB Host and Device, CAN, SPI, I2C, ADC, DAC, PWM and other I/O interfaces. The pin out above shows the commonly used interfaces and their locations. Note that all the numbered pins (p5-p30) can also be used as digital in and digital out interfaces. The mbed Microcontrollers provide experienced embedded developers a powerful and productive platform for building proof-of-concepts. For developers new to 32-bit microcontrollers, mbed provides an accessible prototyping solution to get projects
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built with the backing of libraries, resources and support shared in the mbed community.
4.3.2 Features
A.
NXP LPC1768 MCU

I. II. III.
High performance ARM Cortex-M3 Core 96MHz, 32KB RAM, 512KB FLASH Ethernet, USB Host/Device, 2xSPI, 2xI2C, 3xUART, CAN, 6xPWM, 6xADC, GPIO
B.
Prototyping form-factor
I. II. III.
40-pin 0.1" pitch DIP package, 54x26mm 5V USB or 4.5-9V supply Built-in USB drag 'n' drop FLASH programmer
C.
mbed.org Developer Website

I. II. III.
Lightweight Online Compiler High level C/C++ SDK Cookbook of published libraries and projects
4.3.3 Tools and Software

The mbed Microcontrollers are all supported by the mbed.org developer website, including a lightweight Online Compiler for instant access to your working environment on Windows, Linux or Mac OS X. Also included is a C/C++ SDK for productive high-level programming of peripherals. Combined with the wealth of libraries and code examples being published by the mbed community, the platform provides a productive environment for getting things done.
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The mbed NXP LPC1768 is one of a range of mbed microcontroller packaged as a small 40-pin DIP, 0.1-inch pitch form-factor making it convenient for prototyping with solder less breadboard, strip board, and through-hole PCBs. It includes a built-in USB programming interface that is as simple as using a USB Flash Drive.
4.3.4 Technical references

Power
I. II. III. IV. V. VI. VII. VIII. IX.
Powered by USB or 4.5v - 9.0v applied to VIN Less than 200mA (100mA with Ethernet disabled) Real-time clock battery backup input VB 1.8v - 3.3v Keeps Real-time clock running Requires 27uA, can be supplied by a coin cell 3.3v regulated output on VOUT to power peripherals 5.0v from USB available on VU (only available when USB is connected!) Current limited to 500mA Digital IO pins are 3.3v, 4mA each, 400mA max total
Pins
I.
Vin - External Power supply to the board
4.5v-9v, 100mA + external circuits powered through the Microcontroller
II.
Vb - Battery backup input for Real Time Clock
1.8v-3.3v, 30uA
III. IV. V.
nR - Active-low reset pin with identical functionality to the reset button. Pull up resistor is on the board, so it can be driven with an open collector IF+/- - Reserved for testing
34
The microcontroller I/O is all 3.3v logic, but 5v tolerant. A digital pin can drive 40mA, up to a total of 400mA.
Figure 4.3.2: Block diagram of NXP LPC1768
4.3.5 Hardware Overview

The board used is Keil MCB1700. It uses the NXP LPC 1768 processor, consisting of an ARM core (specifically, the Cortex M3), 512 KB of flash memory and 64 KB of SRAM. The board is connected to the host computer using USB cable. It provides power to the MCB1700. The board itself is relatively simple, and aside from the LPC 1768 itself there are only a few support circuits (mostly RS-232 level converters, Ethernet transceivers, audio amplifiers and so on). The board provides a USB port, two serial (COM) ports, two CAN ports, an Ethernet connector, a micro SD card slot, a potentiometer, a speaker and a set of LEDs and buttons. It also provides a fullcolour LCD display. Pin diagram of NXP LPC1768 is shown in the figure below:
Figure 4.3.3: Pin diagram of NXP LPC1768
4.3.6 Major Functional Block

The LPC 1768 is a system on a chip that combines SRAM and a multichannel ADC onto a single IC.A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. The signal from the phase detector is used to control the oscillator in a feedback loop. The 32-bit peripheral power control register is referenced from C as LPC_SC->PCONP.LPC_SC is a general systemcontrol register block, and PCONP refers to Power CONTROL for Peripherals.
4.3.7 Memory
There are four different blocks of memory on the LPC 1768. There is a block of 512 KB of flash memory, located at the bottom of the address space, which is used for storing your code and data. There is an 8 KB boot ROM, which is hard-coded and unchangeable. There is a block of 32 KB of static RAM for use by the application (its also possible to use this space for code, as an alternative to using the flash memory). And finally, there are two banks of 16 KB of static RAM that are shared
with peripheral devices. All the peripherals are memory-mapped, so they are accessible directly from C.
4.3.8 Implementation
The compensator and PWM scheme is implemented here. The error signal is compared with a saw-tooth ramp voltage and desired PWM signal. The board can withstand a maximum voltage of 3.3V. The pins used here are as follows:Ground, USB(Universal Serial Bus) cable to supply the power to the board through laptop, P 21 is used as the output pin which is connected to the 6th pin the driver UC3715 and P15 is used as the ADC pin where respective pulses are generated for the PWM(Pulse Width Modulator) which in turn is connected to the 10k Potentiometer.
37
CHAPTER 5: CONCLUSION AND FUTURE PROSPECTS

5.1 Conclusion
Designing a voltage-mode controlled buck converter is very challenging. The most difficult part is determining the compensation network and manipulating the poles and zeros to build a robust and balanced system. The PWM is a relatively simple concept, but a real world design of this block would be troublesome. Design and simulation of the circuit is done using Orcade (PSpice). PID controller has been designed and the system operates in closed loop. In other words, feedback stabilizes the system. Phase margin and gain margin has been obtained and stability analysis of the closed loop system has been studied using MATLAB. The PID compensator is designed by modifying the open loop buck converter circuit obtained from the simulation in Orcade (PSpice). The error signal is compared with a saw-tooth ramp voltage and desired PWM signal. The compensator and PWM scheme is implemented using microcontroller NXP LPC1768 using the software Keil Vision4. Improvement in the transient response of the converters through the use of a feedback path with proper compensation has been achieved.
5.2 Future prospects

Technology is still improving over the years. There are many types of configuration for buck converter control available in the market. For instance, there are synchronous buck converter, peak-current control buck converter and etc. Thus, this project could be expanded by implementing peak-current mode control or synchronous buck configuration into the voltage-mode control buck converter for improvement in the controlling of the output voltage. By improving the control method for the buck converter, the complexity of the design will arise, thus it will need more research to be done in the future for such improvement. Finally, even after such improvement, there will be more research that could be done to improve the efficiency and reliability of the converter.
38
REFERENCES
[1] Mohan, Ned, Undeland, T.M., and Robbins, P. W., Power Electronics Converters Applications and Design, Second Edition, John Wiley and Sons. [2] Voltage-mode control and compensation Intricacies for buck regulators by Timothy Hegarty, National Semiconductor - June 30, 2008. [3] Application Note AN-1162- Compensator Design Procedure for Buck Converter with Voltage Mode Error Amplifier By Amir M. Rahimi, Parviz Parto, and PeymanAsadi. [4] International Journal of Computer and Electrical Engineering Vol. 3, No. 2, April, 2011 On Modelling and Simulation of Closed loop controlled buck converter for solar installation by A. Kalirasu and S.S.Dash. [5] AN1452 using the MCP19035 on Synchronous buck converter design tool by SergiuOprea, Microchip technology inc. [6] Rashid, M.H., Power Electronics- Circuits, Devices and Applications, Third Edition, Pearson. [7] SMPS Buck Converter Design Example Web-Seminar, Microchip Technologies.
39
APPENDIX DATA SHEETS
application INFO available
UC1714/5 UC2714/5 UC3714/5
Complementary Switch FET Drivers

FEATURES
Single Input (PWM and TTL Compatible) High Current Power FET Driver, 1.0A Source/2A Sink Auxiliary Output FET Driver, 0.5A Source/1A Sink Time Delays Between Power and Auxiliary Outputs Independently Programmable from 50ns to 500ns Time Delay or True Zero-Voltage Operation Independently Configurable for Each Output Switching Frequency to 1MHz Typical 50ns Propagation Delays ENBL Pin Activates 220A Sleep Mode Power Output is Active Low in Sleep Mode Synchronous Rectifier Driver
DESCRIPTION
These two families of high speed drivers are designed to provide drive waveforms for complementary switches. Complementary switch configurations are commonly used in synchronous rectification circuits and active clamp/reset circuits, which can provide zero voltage switching. In order to facilitate the soft switching transitions, independently programmable delays between the two output waveforms are provided on these drivers. The delay pins also have true zero voltage sensing capability which allows immediate activation of the corresponding switch when zero voltage is applied. These devices require a PWM-type input to operate and can be interfaced with commonly available PWM controllers. In the UC1714 series, the AUX output is inverted to allow driving a p-channel MOSFET. In the UC1715 series, the two outputs are configured in a true complementary fashion.
BLOCK DIAGRAM
2 PWR
50ns 500ns INPUT 6 TIMER S Q R VREF 50ns 500ns TIMER S Q T2 5 R VREF UC1714 ONLY
T1
4 1 VCC 5V LOGIC GATES TIMER REF
AUX VCC
BIAS ENBL 3V GND
3 1.4V ENBL 8 ENABLE
GND
Note: Pin numbers refer to J, N and D packages.
UDG-99028
SLUS170A - FEBRUARY 1999 - REVISED JANUARY 2002
UC1714/5 UC2714/5 UC3714/5 ABSOLUTE MAXIMUM RATINGS

Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Power Driver IOH continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Power Driver IOL continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A Auxiliary Driver IOH continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Auxiliary Driver IOL continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Input Voltage Range (INPUT, ENBL) . . . . . . . . . . 0.3V to 20V Storage Temperature Range . . . . . . . . . . . . . . 65C to 150C Operating Junction Temperature (Note 1) . . . . . . . . . . . . 150C Lead Temperature (Soldering 10 seconds) . . . . . . . . . . . 300C
Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging Section of databook for thermal limitations and specifications of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (Top View) J or N, D Packages SOIC-16 (Top View) DP Package
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL 2V, RT1 = 100k from T1 to GND, RT2 = 100k from T2 to GND, and 55C < TA < 125C for the UC1714/5, 40C < TA < 85C for the UC2714/5, and 0C < TA < 70C for the UC3714/5, TA = TJ.
PARAMETER Overall VCC ICC, nominal ICC, sleep mode Power Driver (PWR) Pre Turn-on PWR Output, Low PWR Output Low, Sat. (VPWR) PWR Output High, Sat. (VCC VPWR) Rise Time Fall Time T1 Delay, AUX to PWR T1 Delay, AUX to PWR PWR Prop Delay VCC = 0V, IOUT = 10mA, ENBL 0.8V INPUT = 0.8V, IOUT = 40mA INPUT = 0.8V, IOUT = 400mA INPUT = 2.0V, IOUT = 20mA INPUT = 2.0V, IOUT = 200mA CL = 2200pF CL = 2200pF INPUT rising edge, RT1 = 10k (Note 4) INPUT rising edge, RT1 = 100k (Note 4) INPUT falling edge, 50% (Note 3) 20 350 0.3 0.3 2.1 2.1 2.3 30 25 35 500 35 1.6 0.8 2.8 3 3 60 60 80 700 100 V V V V V ns ns ns ns ns ENBL = 2.0V ENBL = 0.8V 7 18 200 20 24 300 V mA A TEST CONDITIONS MIN TYP MAX UNITS
UC1714/5 UC2714/5 UC3714/5 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL 2V, RT1 = 100k from T1 to GND, RT2 = 100k from T2 to GND, and 55C < TA < 125C for the UC1714/5, 40C < TA < 85C for the UC2714/5, and 0C < TA < 70C for the UC3714/5, TA = TJ.
PARAMETER Auxiliary Driver (AUX) AUX Output Low, Sat (VAUX) VIN = 2.0V, IOUT = 20mA VIN = 2.0V, IOUT = 200mA AUX Output High, Sat (VCC VAUX) Rise Time Fall Time T2 Delay, PWR to AUX T2 Delay, PWR to AUX AUX Prop Delay Enable (ENBL) Input Threshold Input Current, IIH Input Current, IIL T1 Current Limit Nominal Voltage at T1 Minimum T1 Delay T2 Current Limit Nominal Voltage at T2 Minumum T2 Delay Input (INPUT) Input Threshold Input Current, IIH Input Current, IIL INPUT = 15V INPUT = 0V 0.8 1.4 1
5
TEST CONDITIONS
MIN
TYP 0.3 1.8 2.1 2.3 45 30
MAX UNITS 0.8 2.6 3.0 3.0 60 60 80 550 80 2.0 10 10 2 3.3 70 2 3.3 100 2.0 10 20 V V V V ns ns ns ns ns V A A mA V ns mA V ns V
A
VIN = 0.8V, IOUT = -10mA VIN = 0.8V, IOUT = -100mA CL = 1000pF CL = 1000pF INPUT falling edge, RT2 = 10k (Note 4) INPUT falling edge, RT2 = 100k (Note 4) INPUT rising edge, 50% (Note 3) 0.8 ENBL = 15V ENBL = 0V T1 = 0V 2.7 T1 = 2.5V, (Note 4) T2 = 0V 2.7 T2 = 2.5V, (Note 4) 20 250
50 350 35 1.2 1 1 1.6 3 40 1.2 3 50
Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signals transition with no load on outputs. Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
PIN DESCRIPTIONS
AUX: The AUX switches immediately at INPUTs rising edge but waits through the T2 delay after INPUTs falling edge before switching. AUX is capable of sourcing 0.5A and sinking 1.0A of drive current. See the Time Relationships diagram below for the difference between the UC1714 and UC1715 for INPUT, MAIN, and AUX. During sleep mode, AUX is inactive with a high impedance. ENBL: The ENBL input switches at TTL logic levels (approximately 1.2V), and its input range is from 0V to 20V. 3 The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the sleep mode is typically 220A. GND: This is the reference pin for all input voltages and the return point for all device currents. It carries the full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be damped or clamped such that GND remains the most negative potential.
UC1714/5 UC2714/5 UC3714/5 PIN DESCRIPTIONS (cont.)

INPUT: The input switches at TTL logic levels (approximately 1.4V) but the allowable range is from 0V to 20V, allowing direct connection to most common IC PWM controller outputs. The rising edge immediately switches the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT falling edge immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX output. It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides another option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the delay at the trailing edge. PWR: The PWR output waits for the T1 delay after the INPUTs rising edge before switching on, but switches off immediately at INPUTs falling edge (neglecting propagation delays). This output is capable of sourcing 1A and sinking 2A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this pin active low, when ENBL 0.8V regardless of VCCs voltage. T1: A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on. T2: This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of the AUX switch. T1, T2: The resistor on each of these pins sets the charging current on internal timing capacitors to provide independent time control. The nominal voltage level at each pin is 3V and the current is internally limited to 1mA. The total delay from INPUT to each output includes a propagation delay in addition to the programmable timer but since the propagation delays are approximately equal, the relative time delay between the two outputs can be assumed to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the Typical Characteristics curves. Either or both pins can alternatively be used for voltage sensing in lieu of delay programming. This is done by pulling the timer pins below their nominal voltage level which immediately activates the timer output. VCC: The VCC input range is from 7V to 20V. This pin should be bypassed with a capacitor to GND consistent with peak load current demands.
TYPICAL CHARACTERISTICS
INPUT
PROPAGATION DELAYS PWR OUTPUT

500 T1 vs RT1 T2 vs RT2
400
T1 DELAY UC1714 AUX OUTPUT
T2 DELAY
DELAY (ns)
300
200
100
UC1715 AUX OUTPUT

UDG-99027
10
20
30
40
50 60 RT (kW)
70
80
90
100
Time relationships. (Notes 3, 4)

4
T1 Delay, T2 Delay vs. RT
UC1714/5 UC2714/5 UC3714/5 TYPICAL CHARACTERISTICS (cont.)

21 20
18
Icc (mA)
18
Icc (mA)
16 15
19
17
17 16 0 100 200 300 400 500 600 700 800 900 1000 Switching Frequency (kHz)
10
20
30
40
50
60
70
80
90
100
RT (k)
ICC vs Switching Frequency with No Load and 50% Duty Cycle RT1 = RT2 = 50k
ICC vs RT with Opposite RT = 50k
600
RT1 = 100k
600 500
500
Deadband Delay (ns)
Deadband Delay (ns)
400
400 300 200 100
RT2 = 100k
300
RT1 = 50k
200
RT2 = 50k
100
RT1 = 10k RT1 < 6k
0 -75
-50
-25
0 25 50 Temperature (C)
75
100
125
0 -75
RT2 = 10k RT2 < 6k
-50
-25
25
50
75
100
125
Temperature (C)
T1 Deadband vs. Temperature AUX to PWR
T2 Deadband vs. Temperature PWR to AUX
TYPICAL APPLICATIONS
UDG-94011
UDG-94012
Figure 1. Typical application with timed delays.

5
Figure 2. Using the timer input for zero-voltage sensing.
UC1714/5 UC2714/5 UC3714/5 TYPICAL APPLICATIONS (cont.)
UDG-94013
Figure 3. Self-actuated sleep mode with the absence of an input PWM signal. Wake up occurs with the first pulse while turn-off is determined by the (RTO CTO) time constant.
UDG-94015-2
Figure 4. Using the UC1715 as a complementary synchronous rectifier switch driver with n-channel FETs
UDG-94014-1
Figure 5. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch. VIN is limited to 10V as VCC will rise to approximately 2VIN. 6
UC1714/5 UC2714/5 UC3714/5 TYPICAL APPLICATIONS (cont.)
UDG-94016-1
Figure 6. Typical forward converter topology with active reset provided by the UC1714 driving an N-channel switch (Q1) and a P-channel auxilliary switch (Q2).
UDG-94017-1
Figure 7. Using an N-channel active reset switch with a floating drive command.
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Copyright 2002, Texas Instruments Incorporated
This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.
IRF520
Data Sheet January 2002
9.2A, 100V, 0.270 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power eld effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specied level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA09594.
Features
9.2A, 100V rDS(ON) = 0.270 SOA is Power Dissipation Limited Single Pulse Avalanche Energy Rated Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards
Ordering Information
PART NUMBER IRF520 PACKAGE TO-220AB BRAND IRF520
Symbol
D
NOTE: When ordering, use the entire part number.

G
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (FLANGE)
2002 Fairchild Semiconductor Corporation
IRF520 Rev. B
IRF520
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specied IRF520 100 100 9.2 6.5 37 20 60 0.4 36 -55 to 175 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specications
PARAMETER
TC = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw On Tab To Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances
D LD G LS S
TEST CONDITIONS ID = 250A, VGS = 0V (Figure 10) VGS = VDS, ID = 250A VDS = 95V, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 150oC VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) VGS = 20V ID = 5.6A, VGS = 10V (Figure 8, 9) VDS 50V, ID = 5.6A (Figure 12) VDD = 50V, ID 9.2A, RG = 18, RL = 5.5 MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = 10V, ID = 9.2A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz (Figure 11)
MIN 100 2.0 9.2 2.7 -
TYP 0.25 4.1 9 30 18 20 10 2.5 2.5 350 130 25 3.5
MAX 4.0 250 1000 100 0.27 13 63 70 59 30 -
UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain Miller Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance
4.5
nH
Internal Source Inductance
LS
Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad
7.5
nH
Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
RJC RJA Free Air Operation
2.5 80
oC/W oC/W
IRF520 Rev. B
IRF520
Source to Drain Diode Specications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D
MIN -
TYP -
MAX 9.2 37
UNITS A A
Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES:
VSD trr QRR
TJ = 25oC, ISD = 9.2A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/s TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/s
5.5 0.17
100 0.5
2.5 240 1.1
V ns C
2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 640mH, RG = 25, peak IAS = 9.2A.
Typical Performance Curves

1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25
Unless Otherwise Specied
10
ID, DRAIN CURRENT (A)
125 50 75 100 TC , CASE TEMPERATURE (oC)
150
175
0 25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
10 ZJC, TRANSIENT THERMAL IMPEDANCE (oC/W)
0.5 0.2 0.1 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-4 0.1 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) 1 10
0.1
0.05 0.02 0.01 SINGLE PULSE
0.01 10-5
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
IRF520 Rev. B
IRF520 Typical Performance Curves

100 10s ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10 100s
Unless Otherwise Specied (Continued)

15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 7V 9 VGS = 6V 6
10V
VGS = 8V
12
1ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 1000 10ms
VGS = 5V VGS = 4V 0 20 10 40 30 VDS, DRAIN TO SOURCE VOLTAGE (V) 50
0.1
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
15
VGS = 10V VGS = 8V VGS = 7V
ID, DRAIN CURRENT (A)
12
ID(ON), ON-STATE DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
102
VDS 50V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
10
VGS = 6V
175oC
25oC
3 VGS = 5V 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 4V 5
0.1 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
rDS(ON), DRAIN TO SOURCE ON RESISTANCE
2.5
2.0
NORMALIZED ON RESISTANCE
3.0
2.4
ID = 9.2A, VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5 VGS = 10V
1.8
1.0
1.2
0.5 VGS = 20V 0 0 8 24 16 ID, DRAIN CURRENT (A) 32 40
0.6
0 -60 -40 -20
20
40
60
80
100 120 140 160 180
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
IRF520 Rev. B
IRF520 Typical Performance Curves

1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
Unless Otherwise Specied (Continued)
1000
1.05
C, CAPACITANCE (pF)
1.15
800
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
600
0.95
400
CISS COSS CRSS
0.85
200
0.75 -60
60
120
180
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
102
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
5 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S)
100 TJ = 25oC
10
TJ = 175oC
TJ = 175oC
TJ = 25oC
0 0 3
VDS 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 6 9 ID, DRAIN CURRENT (A) 12 15
0.1 0 0.4 0.8 1.2 1.6 2.0 VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20 VGS, GATE TO SOURCE VOLTAGE (V) ID = 9.2A 16 VDS = 20V VDS = 50V VDS = 80V
12
0 0 3 6 9 12 15 Qg, GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
IRF520 Rev. B
IRF520 Test Circuits and Waveforms

VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
0V
IAS 0.01
0 tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr RL VDS

+
tOFF td(OFF) tf 90%
90%
RG DUT
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k
0.3F
DUT 0
Ig(REF) 0 IG CURRENT SAMPLING RESISTOR
S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0
FIGURE 19. GATE CHARGE TEST CIRCUIT

FIGURE 20. GATE CHARGE WAVEFORMS

IRF520 Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E2CMOSTM EnSignaTM FACT FACT Quiet Series
DISCLAIMER
FAST FASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE
OPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerTrench QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER
SMART START STAR*POWER Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation UHC UltraFET
VCX
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4
This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.
Transys
Electronics
L I M I T E D
1N5826(R) THRU 1N5828(R)
SCHOTTKY DIODES STUD TYPE
15 A
15Amp Rectifier 20-40 Volts
Features
High Surge Capability Types up to 40V V RRM
DO-5
Maximum Ratings
Operating Temperature: -65 C to +150
N
Storage Temperature: -65 C to +175
C J
Part Number 1N5826(R) 1N5827(R) 1N5828(R)
Maximum Recurrent Peak Reverse Voltage 20V 30V 40V
Maximum RMS Voltage 14V 21V 28V
Maximum DC Blocking Voltage 20V 30V 40V
P G F A
Notes: 1.Standard Polarity:Stud is Cathode 2.Reverse Polarity:Stud is Anode

Electrical Characteristics @ 25
Average Forward Current Peak Forward Surge Current NOTE (1) Maximum Instantaneous Forward Voltage Maximum Instantaneous Reverse Current At Rated DC Blocking NOTE (1) Voltage IF(AV) IFSM VF IR
Unless Otherwise Specified

15A 500A
0.44V 0.47V 0.50V
TC =100
DIMENSIONS INCHES MIN MAX 1/4 -28 Threads .669 .687 ----.794 ----1.0 20 .422 .453 .115 .200 ----.460 .----.--------.375 .156 --------.667 ----.080 .140 .175 MM MIN Standard 17.19 --------10.72 2.93 ------------3.96 --------3.56 MAX Polarity 17.44 20.16 25.91 11. 50 5.08 11.68 ----9.52 ----16.94 2.03 4.45 NOTE
8.3ms , half sine

(1N5826) (1N5827) (1N5828) I FM =15 A ; T j = 25
10 mA 250 mA
TJ = 25 TJ = 125
Maximum Thermal Resistance,Junction To Case
R jc
1.8 C/W
DIM A B C D E F G H J K M N P
NOTE : (1) Pulse Test: Pulse Width 300 usec, Duty Cycle < 2%
1N5826( R ) THRU
1N5828(R)
Figure 1 Typical Forward Characteristics
Figure 2 Forward Derating Curve 18

Average ForwArd Rectified Current - AmPeres
100 60 40 125 C 20
15
I nStantaneous Forward Current - Amperes Amps
12
25 C
10 6.0 4.0
Amps
Single Phase, Half Wave 60Hz Resistive or Inductive Load 0 30 60 90 120 150 180
Case Te mperature -
2.0 1.0
0.2
0.4
0.6
Volts
0.8
1.0
1.2
1000 600 400 200
Figure 4 Typical Reverse Characteristics
Instantaneous Forward Voltage - Volts
Tj =150 C
Figure3 Peak Forward Surge Current 600
Instantaneous Reverse Leakage Current - Mill Amperes
100 60 40 20 10 6 4 2 1 .6 .4 .2 .1 .06 .04 .02 .01 0 T J =25 40 50 T J =75 Tj =125 C
Peak Forward Surge Current -Amperes Amps
500 400 300 200 100 0 1 2 4 6 8 10 20 Cycles Number Of Cycles At 60Hz - Cycles 40 60 80 100
m Amps
10
20 Volts
30
Reverse Voltage - Volts

A Project Report On "Voltage Mode Control of Buck Converter"

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A PROJECT REPORT ON VOLTAGE MODE CONTROL OF BUCK CONVERTER

PROJECT ASSOCIATES Anusha A. N (4NM09EE008) Arpan Chatterjee (4NM09EE009)

Ashutosh Kumar (4NM09EE010)

Manish Kumar (4NM09EE031)

Under the guidance of

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

NMAM INSTITUTE OF TECHNOLOGY

Department of Electrical and Electronics Engineering

Semester End Viva Voce Examination

Name of the Examiners 1. _______________________________

Signature with Date ________________________________

Nitte April 2013

Arpan Chatterjee (4NM09EE009) Ashutosh Kumar (4NM09EE010) Manish Kumar (4NM09EE031)

FIGURE NO. 1.1 1.2 2.1 2.2 2.3 2.4

Voltage mode control of buck converter

Block diagram of Buck converter

Type III Compensator open loop control to output transfer function

3.5 3.6 3.7 3.8

Output impedance diagram

Closed loop diagram

PWM Control Simulation of open loop buck converter in PSpice

Inductor Current and Output Voltage Waveform

VOLTAGE MODE CONTROL OF BUCK CONVERTER

VOLTAGE MODE CONTROL OF BUCK CONVERTER

VOLTAGE MODE CONTROL OF BUCK CONVERTER

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

Table 1.1: Design specification of buck converter power stage

Output voltage ripple (V)

Output current ripple (I)

Equivalent series resistance (ESR)

DC input voltage (Vin)

IRF520 metal-oxide-semiconductor fieldeffect transistor (MOSFET)

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

Figure 2.2: When the switch is closed

Figure 2.3: When the switch is open

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

IL ILmax IL ILoad=IL ILmin t

Figure 2.4: Voltages and Currents Waveform of the Buck Converter

VOLTAGE MODE CONTROL OF BUCK CONVERTER

At low load current, in case that

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

2.2 Calculation of L and C:

The maximum value of the inductor current is: .................................................. (2.8)

VOLTAGE MODE CONTROL OF BUCK CONVERTER

2.3 Converter Power Stage Calculation

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

2.3.1 Calculations of Unknown Parameters

Switch ON time, ton=D/Fsw= 0.416/10k= 41.6s

2.3.2 Calculation for Inductance Critical value of inductor:

Department of Electrical & Electronics Engineering, NMAMIT, NITTE

VOLTAGE MODE CONTROL OF BUCK CONVERTER

2.3.3 Calculation for Capacitance

Table 2.1: Inductor and Capacitor Value (calculated)

2.3.4 Buck Converter Diode Selection

2.3.5 Buck Converter MOSFET Selection

) = 0.717 Watt = 0.925 Watt