ackend (Physical Design) Interview Questions and Answers

Below are the sequence of questions asked for a physical design engineer.
In which field are you interested?
Answer to this question depends on your interest, expertise and to the requirement for
which you have been interviewed.
Well..the candidate gave answer: ow power design
Can you talk about low power techniues?
!ow low power and latest "#n$%&'n$ technologies are related?
!efer here and browse for different low power techniques.
Do you know about input vector controlled $ethod of leakage reduction?
eakage current of a gate is dependant on its inputs also. "ence find the set of inputs
which gives least leakage. By applyig this minimum leakage vector to a circuit it is
possible to decrease the leakage current of the circuit when it is in the standby mode.
#his method is known as input vector controlled method of leakage reduction.
!ow can you reduce dyna$ic power?
$!educe switching activity by designing good !#
$%lock gating
$Architectural improvements
$!educe supply voltage
$&se multiple voltage domains$'ulti vdd
(hat are the vectors of dyna$ic power?
(oltage and %urrent
!ow will you do power planning?
!efer here for power planning.
If you have both I) drop and congestion how will you fi* it?
$)pread macros
$)pread standard cells
$*ncrease strap width
$*ncrease number of straps
$&se proper blockage
Is increasing power line width and providing $ore nu$ber of straps are the only
solution to I) drop?
$)pread macros
$)pread standard cells
$&se proper blockage
In a reg to reg path if you have setup proble$ where will you insert buffer+near to
launching flop or capture flop? (hy?
+buffers are inserted for fixing fanout voilations and hence they reduce setup
voilation, otherwise we try to fix setup voilation with the si-ing of cells, now .ust
assume that you must insert buffer /0
1ear to capture path.
Because there may be other paths passing through or originating from the flop nearer
to lauch flop. "ence buffer insertion may affect other paths also. *t may improve all
those paths or degarde. *f all those paths have voilation then you may insert buffer
nearer to launch flop provided it improves slack.
!ow will you decide best floorplan?
!efer here for floor planning.
(hat is the $ost challenging task you handled?
(hat is the $ost challenging ,ob in P-) flow?
$*t may be power planning$ because you found more *! drop
$*t may be low power target$because you had more dynamic and leakage power
$*t may be macro placement$because it had more connection with standard cells or
macros
$*t may be %#)$because you needed to handle multiple clocks and clock domain
crossings
$*t may be timing$because si-ing cells in 2%3 flow is not meeting timing
$*t may be library preparation$because you found some inconsistancy in libraries.
$*t may be 4!%$because you faced thousands of voilations
!ow will you synthesi.e clock tree?
$)ingle clock$normal synthesis and optimi-ation
$'ultiple clocks$)ynthesis each clock seperately
$'ultiple clocks with domain crossing$)ynthesis each clock seperately and balance
the skew
!ow $any clocks were there in this pro,ect?
$*t is specific to your pro.ect
$'ore the clocks more challenging /
!ow did you handle all those clocks?
$'ultiple clocks$$5synthesi-e seperately$$5balance the skew$$5optimi-e the clock
tree
Are they co$e fro$ seperate e*ternal resources or P//?
$*f it is from seperate clock sources +i.e.asynchronous, from different pads or pins0
then balancing skew between these clock sources becomes challenging.
$*f it is from 6 +i.e.synchronous0 then skew balancing is comparatively easy.
(hy buffers are used in clock tree?
#o balance skew +i.e. flop to flop delay0
(hat is cross talk?
)witching of the signal in one net can interfere neigbouring net due to cross coupling
capacitance.#his affect is known as cros talk. %ross talk may lead setup or hold
voilation.
!ow can you avoid cross talk?
$4ouble spacing75more spacing75less capacitance75less cross talk
$'ultiple vias75less resistance75less !% delay
$)hielding75 constant cross coupling capacitance 75known value of crosstalk
$Buffer insertion75boost the victim strength
!ow shielding avoids crosstalk proble$? (hat e*actly happens there?
$"igh frequency noise +or glitch0is coupled to ()) +or (440 since shilded layers are
connected to either (44 or ()).
%oupling capacitance remains constant with (44 or ()).
!ow spacing helps in reducing crosstalk noise?
width is more75more spacing between two conductors75cross coupling capacitance
is less75less cross talk
(hy double spacing and $ultiple vias are used related to clock?
Why clock8$$ because it is the one signal which chages it state regularly and more
compared to any other signal. *f any other signal switches fast then also we can use
double space.
4ouble spacing75width is more75capacitance is less75less cross talk
'ultiple vias75resistance in parellel75less resistance75less !% delay
!ow buffer can be used in victi$ to avoid crosstalk?
Buffer increase victims signal strength, buffers break the net length75victims are
more tolerant to coupled signal from aggressor.
07 July 2008
Co$panywise A0IC%1/0I Interview Questions
Below interview questions are contributed by A)*%9diehard +#hanks a lot /0. Below
questions are asked for senior position in 6hysical 4esign domain. #he questions are also
related to )tatic #iming Analysis and )ynthesis. Answers to some questions are given as link.
!emaining questions will be answered in coming blogs.
Co$$on introductory uestions every interviewer asks are2
Dscuss about the pro|ects worked n the prevous company.
What are physca desgn fows, varous actvtes you are nvoved?
Desgn compexty, capacty, frequency, process technooges, bock sze
you handed.
Intel
Why power stripes routed in the top metal layers?
#he resistivity of top metal layers are less and hence less *! drop is seen in power
distribution network. *f power stripes are routed in lower metal layers this will use good
amount of lower routing resources and therefore it can create routing congestion.
Why do you use alternate routing approach HVH/VHV (Horizontal
VerticalHorizontal/ VerticalHorizontalVertical!?
Answer2
#his approach allows routability of the design and better usage of routing resources.
What are se"eral #actors to impro"e propagation delay o#
standard cell?
Answer2
*mprove the input transition to the cell under consideration by up si-ing the driver.
!educe the load seen by the cell under consideration, either by placement refinement or
buffering.
*f allowed increase the drive strength or replace with (# +low threshold voltage0 cell.
How do you compute net deay (nterconnect deay) / decode RC vaues
present n tech fe?
What are "arious ways o# timing optimization in synthesis tools?
Answer2
ogic optimi-ation: buffer si-ing, cell si-ing, level ad.ustment, dummy buffering etc.
ess number of logics between :lip :lops speedup the design.
3ptimi-e drive strength of the cell , so it is capable of driving more load and hence reducing
the cell delay.
Better selection of design ware component +select timing optimi-ed design ware
components0.
&se (# +ow threshold voltage0 and )(# +standard threshold voltage0 cells if allowed.
What would you do in order to not use certain cells #rom the
li$rary?
Answer2
)et don;t use attribute on those library cells.
How delays are characterized using W%& (Wire %oad &odel!?
'nswer(
For a gven wreoad mode the deay are estmated based on the number of
fanout of the ce drvng the net.
Fanout vs net ength s tabuated n WLMs.
Vaues of unt resstance R and unt capactance C are gven n technoogy fe.
Net ength vares based on the fanout number.
Once the net ength s known deay can be cacuated; Sometmes t s agan
tabuated.
What are "arious techni)ues to resol"e congestion/noise?
Answer2
!outing and placement congestion all depend upon the connectivity in the netlist , a better
floor plan can reduce the congestion.
1oise can be reduced by optimi-ing the overlap of nets in the design.
%et*s say there enough routing resources a"aila$le+ timing is #ine+
can you increase cloc, $u##ers in cloc, networ,? -# so will there $e
any impact on other parameters?
Answer2
1o. <ou should not increase clock buffers in the clock network. *ncrease in clock buffers
cause more area , more power. When everything is fine why you want to touch clock tree88
How do you optimize s,ew/insertion delays in ./0 (.loc, /ree
0ynthesis!?
Answer2
Better skew targets and insertion delay values provided while building the clocks.
%hoose appropriate tree structure = either based on clock buffers or clock inverters or mix of
clock buffers or clock inverters.
:or multi clock domain, group the clocks while building the clock tree so that skew is
balanced across the clocks. +*nter clock skew analysis0.
What are pros/cons o# latch/11 (1lip 1lop!?
'nswer( Pros and cons of atch and fp fop
How you go about fxng tmng voatons for atch- atch paths?
As an engneer, ets say your manager comes to you and asks for next
pro|ect de sze estmaton/pro|ecton, gvng data on RTL sze,
performance requrements. How do you go about the fgurng out and
come up wth de sze consderng physca aspects?
How w you desgn nsertng votage sand scheme between macro pns
crossng core and are at dfferent power wes? What s the optma
resource souton?
What are varous forma verfcaton ssues you faced and how dd you
resove?
How do you cacuate maxmum frequency gven setup, hod, cock and
cock skew?
What are e##ects o# metasta$ility?
'nswer( Metastabty
Consder a tmng path crossng from fast cock doman to sow cock
doman. How do you desgn synchronzer crcut wthout knowng the
source cock frequency?
How to sove cross cock tmng path?
How to determine the depth o# 1-12/ size o# the 1-12?
'nswer( FIFO Depth
03$icroelectronics
What are the chaenges you faced n pace and route, FV (Forma
Verfcaton), ECO (Engneerng Change Order) areas?
How ong the desgn cyce for your desgns?
What part are your areas of nterest n physca desgn?
Expan ECO (Engneerng Change Order) methodoogy.
34plain ./0 (.loc, /ree 0ynthesis! #low5
'nswer( Cock Tree Synthess
What knd of routng ssues you faced?
How does 0/' (0tatic /iming 'nalysis! in 2.V (2n .hip Variation!
conditions done? How do you set 2.V (2n .hip Variation! in -.
compiler? How is timing correlation done $e#ore and a#ter place
and route?
'nswer( Process-Votage-Temperature (PVT) Varatons and Statc Tmng
Anayss (STA)
If there are too many pns of the ogc ces n one pace wthn core, what
knd of ssues woud you face and how w you resove?
Defne hash/ @array n per.
Usng TCL (Too Command Language, Tcke) how do you set varabes?
What s ICC (IC Comper) command for settng derate factor/ command to
perform physca synthess?
What are nanoroute optons for search and repar?
What were your desgn skew/nserton deay targets?
How s IR drop anayss done? What are varous statstcs avaabe n
reports?
Expan pn densty/ ce densty ssues, hotspots?
How w you reate routng grd wth manufacturng grd and |udge f the
routng grd s set correcty?
What s the command for settng mut cyce path?
If hod voaton exsts n desgn, s t OK to sgn off desgn? If not, why?
3e*as Instru$ents (3I)
How are tmng constrants deveoped?
Expan tmng cosure fow/methodoogy/ssues/fxes.
Expan SDF (Standard Deay Format) back annotaton/ SPEF (Standard
Parastc Exchange Format) tmng correaton fow.
Gven a tmng path n mut-mode mut-corner, how s STA (Statc Tmng
Anayss) performed n order to meet tmng n both modes and corners,
how are PVT (Process-Votage-Temperature)/derate factors decded and
set n the Prmetme fow?
Wth respect to cock gate, what are varous ssues you faced at varous
stages n the physca desgn fow?
What are synthess strateges to optmze tmng?
Expan ECO (Engneerng Change Order) mpementaton fow. Gven post
routed database and functona fxes, how w you take t to mpement
ECO (Engneerng Change Order) and what physca and functona checks
you need to perform?
Qualco$$
In budng the tmng constrants, do you need to constran a IO (Input-
Output) ports?
Can a snge port have mut-cocked? How do you set deays for such
ports?
How s scan DEF (Desgn Exchange Format) generated?
What s purpose of ockup atch n scan chan?
34plain short circuit current5
'nswer( Short Crcut Power
What are pros/cons o# using low Vt+ high Vt cells?
'nswer(
Mut Threshod Votage Technque
Issues Wth Mut Heght Ce Pacement n Mut Vt Fow
How do you set inter cloc, uncertainty?
Answer2
set9clock9uncertainty =from clock> $to clock?
In DC (Desgn Comper), how do you constran cocks, IO (Input-Output)
ports, maxcap, max tran?
What are di##erences in cloc, constraints #rom pre ./0 (.loc, /ree
0ynthesis! to post ./0 (.loc, /ree 0ynthesis!?
'nswer(
4ifference in clock uncertainty values, %locks are propagated in post %#).
*n post %#) clock latency constraint is modified to model clock .itter.
How is cloc, gating done?
'nswer( Cock Gatng
What constraints you add in ./0 (.loc, /ree 0ynthesis! #or cloc,
gates?
Answer:
'ake the clock gating cells as through pins.
What is trade o## $etween dynamic power (current! and lea,age
power (current!?
'nswer(
Leakage Power Trends
Dynamc Power
How do you reduce stand$y (lea,age! power?
'nswer( Low Power Desgn Technques
Expan top eve pn pacement fow? What are parameters to decde?
Gven bock eve netsts, tmng constrants, brares, macro LEFs (Layout
Exchange Format/Lbrary Exchange Format), how w you start foor
pannng?
Wth net ength of 1000um how w you compute RC vaues, usng
equatons/tech fe nfo?
What do nose reports represent?
What does gtch reports contan?
What are CTS (Cock Tree Synthess) steps n IC comper?
What do cock constrants fe contan?
How to anayze cock tree reports?
What do IR drop Votagestorm reports represent?
Where /when do you use DCAP (Decoupng Capactor) ces?
What are "arious power reduction techni)ues?
'nswer( Low Power Desgn Technques
!ughes 4etworks
What s setup/hod? What are setup and hod tme mpacts on tmng? How
w you fx setup and hod voatons?
Expan functon of Muxed FF (Mutpexed Fp Fop) /scan FF (Sca Fp
Fop).
What are tested n DFT (Desgn for Testabty)?
In equvaence checkng, how do you hande scanen sgna?
In terms of CMOS (Compmentary Meta Oxde Semconductor), expan
physca parameters that affect the propagaton deay?
What are power dissipation components? How do you reduce
them?
'nswer(
Short Crcut Power
Leakage Power Trends
Dynamc Power
Low Power Desgn Technques
How delay a##ected $y 6V/ (6rocessVoltage/emperature!?
'nswer( Process-Votage-Temperature (PVT) Varatons and Statc Tmng
Anayss (STA)
Why s power sgna routed n top meta ayers?
Avago 3echnologies (for$er !P group)
How do you mnmze cock skew/ baance cock tree?
Gven 11 mnterms and asked to derve the ogc functon.
Gven C1= 10pf, C2=1pf connected n seres wth a swtch n between, at
t=0 swtch s open and one end havng 5v and other end zero votage;
compute the votage across C2 when the swtch s cosed?
Expan the modes of operaton of CMOS (Compmentary Meta Oxde
Semconductor) nverter? Show IO (Input-Output) characterstcs curve.
Impement a rng oscator.
How to sow down rng oscator?
!yni* 0e$iconductor
How do you optmze power at varous stages n the physca desgn fow?
What tmng optmzaton strateges you empoy n pre-ayout /post-ayout
stages?
What are process technoogy chaenges n physca desgn?
Desgn dvde by 2, dvde by 3, and dvde by 1.5 counters. Draw tmng
dagrams.
What are mut-cyce paths, fase paths? How to resove mut-cyce and
fase paths?
Gven a fop to fop path wth combo deay n between and output of the
second fop fed back to combo ogc. Whch path s fastest path to have
hod voaton and how w you resove?
What are RTL (Regster Transfer Leve) codng styes to adapt to yed
optma backend desgn?
Draw tmng dagrams to represent the propagaton deay, set up, hod,
recovery, remova, mnmum puse wdth.
About Contributor
A)*%9diehard has more than @ years of experience in physical design, timing, netlist to A4)
flows of *ntegrated %ircuit development. A)*%9diehardBs fields of interest are backend
design, place and route, timing closure, process technologies.
!eaders are encouraged to discuss answers to these questions. Cust click on the Bpost a
commentB option below and put your comments there. Alternatively you can send your
answersDdiscussions to my mail id: shavakmmEgmail.com
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2 comments Tags: ASIC, Physca Desgn, Statc Tmng Anayss (STA),
Synthess, Tmng Anayss, VLSI
Reacton
s:
87 'pril 2008
Issues with 5ulti !eight Cell Place$ent in 5ulti 1t 6low
.reating the re#erence li$raries
#here are two reference libraries required. 3ne is low (t cell library and another is high (t
cell library. #hese libraries have two different height cells. !eference libraries are created as
per the standard synopsys flow. ibrary creation flow is given in :igure >. !ead9lib
command is used for this purpose. As #: and 2: files are available #:F2: option is
chosen for library creation. After the completion of the physical library preparation steps,
logical libraries are prepared.
1igure 8 %i$rary preparation command window
Different 7nit 3ile Creation
#he unit tile height of lvt cells is ?.@? and hvt cells are >.GH . "ence two separate unit tiles
have to be created and should be added in the technology file. "vt reference library is created
with the unit tile name IunitJ and lvt reference library is created with unit tile name
Ilvt9unitJ. By default IunitJ tile is defined in technology file and the other unit tile Ilvt9unitJ
is also added to the technology file.
6igure 89 3ile height specifications in library preparation
6loor Planning
KLM of the core utili-ation is provided. Aspect ratio is kept at >. !ows are flipped, double
backed and made channel less. 1o #op 4esign :ormat +#4:0 file is selected as default
placement of the *3 pins are considered. )ince we have multi height cells in the reference
library separate placement rows have to be provided for two different unit tiles. #he core area
is divided into two separate unit tile section providing larger area for "vt unit tile as shown in
the :igure N.
6igure :9 Different unit tile place$ent
:irst as per the default floor planning flow rows are constructed with unit tile. ater rows are
deleted from the part of the core area and new rows are inserted with the tile Ilvt9unitJ.
*mproper allotment of area can give rise to congestion. )ome iteration of trial and error
experiments were conducted to find best suitable area for two different unit tiles. #he IunitJ
tile covers OO.NHM of core area while Ilvt9unitJ H@.@NM of the core area. 6! summary report
of the design after the floor planning stage is provided below.
6! )ummary:
1umber of 'odule %ells: KLOOG
1umber of 6ins: NHPGNH
1umber of *3 6ins: ?GP
1umber of 1ets: KLP@P
Average 6ins 6er 1et +)ignal0: N.?L?P>
%hip &tili-ation:
#otal )tandard %ell Area: @@GNHK.KK
%ore )i-e: width GOG.KH, height GOK.PL, area GLL>P?.@N
%hip )i-e: width GGG.KH, height GGP.HO, area GGPOLL.NN
%ellD%ore !atio: H?.>NGOM
%ellD%hip !atio: @H.L?HOM
1umber of %ell !ows: NG?
Place$ent Issues with Different 3ile )ows
egal placement of the standard cells is automatically taken care by Astro tool as two
separate placement area is defined for multi heighten cells. %orresponding tile utili-ation
summary is provided below.
6! )ummary:
Q#ile &tili-ationR
777777777777777777777777777777777777777777777777777777777777
unit ?@KKG? >>ON@N OO.NHM
lvt9unit >LK>PK? KL?O?@ H@.@NM
777777777777777777777777777777777777777777777777777777777777
But this method of placement generates unacceptable congestion around the .unction area of
two separate unit tile sections. #he congestion map is shown in :igure O.
6igure ;9 Congestion
#here are two congestion maps. 3ne is related to the floor planning with aspect ratio > and
core utili-ation of KLM. #his shows hori-ontal congestion over the limited value of one all
over the core area meaning that design can;t be routed at all. "ence core area has to be
increased by specifying height and width. #he other congestion map is generated with the
floor plan wherein core area is set to G@L Sm. "ere we can observe although congestion has
reduced over the core area it is still a concern over the area wherein two different unit tiles
merge as marked by the circle. But design can be routable and can be carried to next stages of
place and route flow provided timing is met in subsequent implementation steps.
#ighter timing constraints and more interrelated connections of standard cells around the
.unction area of different unit tiles have lead to more congestion. *t is observed that
increasing the area isnBt a solution to congestion. *n addition to congestion, situation verses
with the timing optimi-ation effort by the tool. #iming target is not able to meet.
3ptimi-ation process inserts several buffers around the .unction area and some of them are
placed illegally due to the lack of placement area.
%orresponding timing summary is provided below:
#imingD3ptimi-ation *nformation:
Q#*'*1AR
)etup "old 1um 1um
#ype )lack 1um #otal #arget )lack 1um #rans 'ax%ap #ime
77777777777777777777777777777777777777777777777777777777
A.6!2 $N.OG> N?GN $NN@N.G L.>LL >LLLL.LLL L POH> O?H LL:L?:?H
A.*63 $L.OPK G?P $?K>.@ L.>LL >LLLL.LLL L >NL> ?G LL:L>:L?
A.*63 $L.O@O >NPN $N>?.P L.>LL >LLLL.LLL L >KH@ NH LL:L>:@K
A.663 $>.OL@ >HLK $@GL.G L.>LL >LLLL.LLL L ?N?@ N? LL:LL:@P
A.)2#&6 $>.OL@ >@>K $OHH.O L.>LL $L.>HP H@@L ???> N> LL:LO:>L
77777777777777777777777777777777777777777777777777777777
)ince the timing is not possible to meet design has to be abandoned from subsequent steps.
"ence in a multi vt design flow cell library with multi heights are not preferred.
)eferences
Q>R Astro, &ser Auide, (ersion T$?LL@.LG, )eptember ?LL@
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08 'pril 2008
Physical Design <b,ective 3ype of Questions and Answers
8! .hip utilization depends on 9995
a. Ony on standard ces
b. Standard ces and macros
c. Ony on macros
d. Standard ces macros and IO pads
2! -n 0o#t $loc,ages 9999 cells are placed5
a. Ony sequenta ces
b. No ces
c. Ony Buffers and Inverters
d. Any ces
:! Why we ha"e to remo"e scan chains $e#ore placement?
a. Because scan chans are group of fp fop
b. It does not have tmng crtca path
c. It s seres of fp fop connected n FIFO
d. None
;! <elay $etween shortest path and longest path in the cloc, is
called 99995
a. Usefu skew
b. Loca skew
c. Goba skew
d. Sack
=! .ross tal, can $e a"oided $y 9995
a. Decreasng the spacng between the meta ayers
b. Shedng the nets
c. Usng ower meta ayers
d. Usng ong nets
>! 6rerouting means routing o# 999995
a. Cock nets
b. Sgna nets
c. IO nets
d. PG nets
7! Which o# the #ollowing metal layer has &a4imum resistance?
a. Meta1
b. Meta2
c. Meta3
d. Meta4
8! What is the goal o# ./0?
a. Mnmum IR Drop
b. Mnmum EM
c. Mnmum Skew
d. Mnmum Sack
?! @sually Hold is #i4ed 9995
a. Before Pacement
b. After Pacement
c. Before CTS
d. After CTS
80! /o achie"e $etter timing 9999 cells are placed in the critical
path5
a. HVT
b. LVT
c. RVT
d. SVT
88! %ea,age power is in"ersely proportional to 9995
a. Frequency
b. Load Capactance
c. Suppy votage
d. Threshod Votage
82! 1iller cells are added 9995
a. Before Pacement of std ces
b. After Pacement of Std Ces
c. Before Foor pannng
d. Before Deta Routng
8:! 0earch and Aepair is used #or 9995
a. Reducng IR Drop
b. Reducng DRC
c. Reducng EM voatons
d. None
8;! &a4imum current density o# a metal is a"aila$le in 9995
a. .b
b. .v
c. .tf
d. .sdc
8=! &ore -A drop is due to 9995
a. Increase n meta wdth
b. Increase n meta ength
c. Decrease n meta ength
d. Lot of meta ayers
8>! /he minimum height and width a cell can occupy in the design
is called as 9995
a. Unt Te ce
b. Mut heghten ce
c. LVT ce
d. HVT ce
87! .A6A stands #or 9995
a. Ce Convergence Pessmsm Remova
b. Ce Convergence Preset Remova
c. Cock Convergence Pessmsm Remova
d. Cock Convergence Preset Remova
88! -n 2.V timing chec,+ #or setup time+ 9995
a. Max deay s used for aunch path and Mn deay for capture path
b. Mn deay s used for aunch path and Max deay for capture path
c. Both Max deay s used for aunch and Capture path
d. Both Mn deay s used for both Capture and Launch paths
8?! B/otal metal area and(or! perimeter o# conducting layer / gate
to gate areaB is called 9995
a. Utzaton
b. Aspect Rato
c. OCV
d. Antenna Rato
20! /he 0olution #or 'ntenna e##ect is 9995
a. Dode nserton
b. Shedng
c. Buffer nserton
d. Doube spacng
28! /o a"oid cross tal,+ the shielded net is usually connected to
9995
a. VDD
b. VSS
c. Both VDD and VSS
d. Cock
22! -# the data is #aster than the cloc, in Aeg to Aeg path 999
"iolation may come5
a. Setup
b. Hod
c. Both
d. None
2:! Hold "iolations are pre#erred to #i4 9995
a. Before pacement
b. After pacement
c. Before CTS
d. After CTS
2;! Which o# the #ollowing is not present in 0<. 999?
a. Max tran
b. Max cap
c. Max fanout
d. Max current densty
2=! /iming sanity chec, means (with respect to 6<!9995
a. Checkng tmng of routed desgn wth out net deays
b. Checkng Tmng of paced desgn wth net deays
c. Checkng Tmng of unpaced desgn wthout net deays
d. Checkng Tmng of routed desgn wth net deays
2>! Which o# the #ollowing is ha"ing highest priority at #inal stage
(post routed! o# the design 999?
a. Setup voaton
b. Hod voaton
c. Skew
d. None
27! Which o# the #ollowing is $est suited #or ./0?
a. CLKBUF
b. BUF
c. INV
d. CLKINV
28! &a4 "oltage drop will $e there at(with out macros! 9995
a. Left and Rght sdes
b. Bottom and Top sdes
c. Mdde
d. None
2?! Which o# the #ollowing is pre#erred while placing macros 999?
a. Macros paced center of the de
b. Macros paced eft and rght sde of de
c. Macros paced bottom and top sdes of de
d. Macros paced based on connectvty of the I/O
:0! Aouting congestion can $e a"oided $y 9995
a. pacng ces coser
b. Pacng ces at corners
c. Dstrbutng ces
d. None
:8! 6itch o# the wire is 9995
a. Mn wdth
b. Mn spacng
c. Mn wdth - mn spacng
d. Mn wdth + mn spacng
:2! -n 6hysical <esign #ollowing step is not there 9995
a. Foorpanng
b. Pacement
c. Desgn Synthess
d. CTS
::! -n technology #ile i# 7 metals are there then which metals you
will use #or power?
a. Meta1 and meta2
b. Meta3 and meta4
c. Meta5 and meta6
d. Meta6 and meta7
:;! -# metal> and metal7 are used #or the power in 7 metal layer
process design then which metals you will use #or cloc, ?
a. Meta1 and meta2
b. Meta3 and meta4
c. Meta4 and meta5
d. Meta6 and meta7
:=! -n a reg to reg timing path /cloc,to) delay is 05=ns and
/.om$o delay is =ns and /setup is 05=ns then the cloc, period
should $e 9995
a. 1ns
b. 3ns
c. 5ns
d. 6ns
:>! <i##erence $etween .loc, $u##/in"erters and normal
$u##/in"erters is 995
a. Cock buff/nverters are faster than norma buff/nverters
b. Cock buff/nverters are sower than norma buff/nverters
c. Cock buff/nverters are havng equa rse and fa tmes wth hgh drve
strengths compare to norma buff/nverters
d. Norma buff/nverters are havng equa rse and fa tmes wth hgh drve
strengths compare to Cock buff/nverters.
:7! Which con#iguration is more pre#erred during #loorplaning ?
a. Doube back wth fpped rows
b. Doube back wth non fpped rows
c. Wth channe spacng between rows and no doube back
d. Wth channe spacng between rows and doube back
:8! What is the e##ect o# high dri"e strength $u##er when added in
long net ?
a. Deay on the net ncreases
b. Capactance on the net ncreases
c. Deay on the net decreases
d. Resstance on the net ncreases.
:?! <elay o# a cell depends on which #actors ?
a. Output transton and nput oad
b. Input transton and Output oad
c. Input transton and Output transton
d. Input oad and Output Load.
;0! '#ter the #inal routing the "iolations in the design 9995
a. There can be no setup, no hod voatons
b. There can be ony setup voaton but no hod
c. There can be ony hod voaton not Setup voaton
d. There can be both voatons.
;8! @tilisation o# the chip a#ter placement optimisation will $e 9995
a. Constant
b. Decrease
c. Increase
d. None of the above
;2! What is routing congestion in the design?
a. Rato of requred routng tracks to avaabe routng tracks
b. Rato of avaabe routng tracks to requred routng tracks
c. Depends on the routng ayers avaabe
d. None of the above
;:! What are preroutes in your design?
a. Power routng
b. Sgna routng
c. Power and Sgna routng
d. None of the above.
;;! .loc, tree doesnCt contain #ollowing cell 9995
a. Cock buffer
b. Cock Inverter
c. AOI ce
d. None of the above
'nswers(
1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c
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82 &arch 2008
=ackend (Physical Design) Interview Questions and Answers
Beow are the sequence of questons asked for a physca desgn engneer.
-n which #ield are you interested?
Answer to ths queston depends on your nterest, expertse and to the
requrement for whch you have been ntervewed.
We..the canddate gave answer: Low power desgn
.an you tal, a$out low power techni)ues?
How low power and latest ?0nm/>=nm technologies are related?
Refer here and browse for dfferent ow power technques.
<o you ,now a$out input "ector controlled method o# lea,age
reduction?
Leakage current of a gate s dependant on ts nputs aso. Hence fnd the
set of nputs whch gves east eakage. By appyg ths mnmum eakage
vector to a crcut t s possbe to decrease the eakage current of the
crcut when t s n the standby mode. Ths method s known as nput
vector controed method of eakage reducton.
How can you reduce dynamic power?
-Reduce swtchng actvty by desgnng good RTL
-Cock gatng
-Archtectura mprovements
-Reduce suppy votage
-Use mutpe votage domans-Mut vdd
What are the "ectors o# dynamic power?
Votage and Current
How will you do power planning?
Refer here for power pannng.
-# you ha"e $oth -A drop and congestion how will you #i4 it?
-Spread macros
-Spread standard ces
-Increase strap wdth
-Increase number of straps
-Use proper bockage
-s increasing power line width and pro"iding more num$er o# straps are
the only solution to -A drop?
-Spread macros
-Spread standard ces
-Use proper bockage
-n a reg to reg path i# you ha"e setup pro$lem where will you insert
$u##ernear to launching #lop or capture #lop? Why?
(buffers are nserted for fxng fanout voatons and hence they reduce
setup voaton; otherwse we try to fx setup voaton wth the szng of
ces; now |ust assume that you must nsert buffer !)
Near to capture path.
Because there may be other paths passng through or orgnatng from the
fop nearer to auch fop. Hence buffer nserton may affect other paths
aso. It may mprove a those paths or degarde. If a those paths have
voaton then you may nsert buffer nearer to aunch fop provded t
mproves sack.
How will you decide $est #loorplan?
Refer here for foor pannng.
What is the most challenging tas, you handled?
What is the most challenging Do$ in 6EA #low?
-It may be power pannng- because you found more IR drop
-It may be ow power target-because you had more dynamc and eakage
power
-It may be macro pacement-because t had more connecton wth
standard ces or macros
-It may be CTS-because you needed to hande mutpe cocks and cock
doman crossngs
-It may be tmng-because szng ces n ECO fow s not meetng tmng
-It may be brary preparaton-because you found some nconsstancy n
brares.
-It may be DRC-because you faced thousands of voatons
How will you synthesize cloc, tree?
-Snge cock-norma synthess and optmzaton
-Mutpe cocks-Synthess each cock seperatey
-Mutpe cocks wth doman crossng-Synthess each cock seperatey and
baance the skew
How many cloc,s were there in this proDect?
-It s specfc to your pro|ect
-More the cocks more chaengng !
How did you handle all those cloc,s?
-Mutpe cocks-->synthesze seperatey-->baance the skew-->optmze
the cock tree
're they come #rom seperate e4ternal resources or 6%%?
-If t s from seperate cock sources (.e.asynchronous; from dfferent pads
or pns) then baancng skew between these cock sources becomes
chaengng.
-If t s from PLL (.e.synchronous) then skew baancng s comparatvey
easy.
Why $u##ers are used in cloc, tree?
To baance skew (.e. fop to fop deay)
What is cross tal,?
Swtchng of the sgna n one net can nterfere negbourng net due to
cross coupng capactance.Ths affect s known as cros tak. Cross tak
may ead setup or hod voaton.
How can you a"oid cross tal,?
-Doube spacng=>more spacng=>ess capactance=>ess cross tak
-Mutpe vas=>ess resstance=>ess RC deay
-Shedng=> constant cross coupng capactance =>known vaue of
crosstak
-Buffer nserton=>boost the vctm strength
How shielding a"oids crosstal, pro$lem? What e4actly happens there?
-Hgh frequency nose (or gtch)s couped to VSS (or VDD) snce shded
ayers are connected to ether VDD or VSS.
Coupng capactance remans constant wth VDD or VSS.
How spacing helps in reducing crosstal, noise?
wdth s more=>more spacng between two conductors=>cross coupng
capactance s ess=>ess cross tak
Why dou$le spacing and multiple "ias are used related to cloc,?
Why cock?-- because t s the one sgna whch chages t state reguary
and more compared to any other sgna. If any other sgna swtches fast
then aso we can use doube space.
Doube spacng=>wdth s more=>capactance s ess=>ess cross tak
Mutpe vas=>resstance n paree=>ess resstance=>ess RC deay
How $u##er can $e used in "ictim to a"oid crosstal,?
Buffer ncrease vctms sgna strength; buffers break the net
ength=>vctms are more toerant to couped sgna from aggressor.
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8> 1e$ruary 2008
Physical Design Questions and Answers
I am gettng severa emas requestng answers to the questons posted n
ths bog. But t s very dffcut to provde detaed answer to a questons
n my avaabe spare tme. Hence decded to gve "short and sweet" one
ne answers to the questons so that readers can mmedatey benefted.
Detaed answers w be posted n ater stage.I have gven answers to
some of the physca desgn questons here. En|oy !
What parameters (or aspects! di##erentiate .hip <esign and Floc, le"el
design?
Chp desgn has I/O pads; bock desgn has pns.
Chp desgn uses a meta ayes avaabe; bock desgn may not use a
meta ayers.
Chp s generay rectanguar n shape; bocks can be rectanguar,
rectnear.
Chp desgn requres severa packagng; bock desgn ends n a macro.
How do you place macros in a #ull chip design?
Frst check fynes .e. check net connectons from macro to macro and
macro to standard ces.
If there s more connecton from macro to macro pace those macros
nearer to each other preferaby nearer to core boundares.
If nput pn s connected to macro better to pace nearer to that pn or pad.
If macro has more connecton to standard ces spread the macros nsde
core.
Avod crscross pacement of macros.
Use soft or hard bockages to gude pacement engne.
<i##erentiate $etween a Hierarchical <esign and #lat design?
Herarcha desgn has bocks, subbocks n an herarchy; Fattened desgn
has no subbocks and t has ony eaf ces.
Herarchca desgn takes more run tme; Fattened desgn takes ess run
tme.
Which is more complicated when u ha"e a ;8 &Hz and =00 &Hz cloc,
design?
500 MHz; because t s more constraned (.e.esser cock perod) than 48
MHz desgn.
Game #ew tools which you used #or physical "eri#ication?
Hercus from Synopsys, Caber from Mentor Graphcs.
What are the input #iles will you gi"e #or primetime correlation?
Netst, Technoogy brary, Constrants, SPEF or SDF fe.
-# the routing congestion e4ists $etween two macros+ then what will you
do?
Provde soft or hard bockage
How will you decide the die size?
By checkng the tota area of the desgn you can decde de sze.
-# lengthy metal layer is connected to di##usion and poly+ then which
one will a##ect $y antenna pro$lem?
Poy
-# the #ull chip design is routed $y 7 layer metal+ why macros are
designed using =%& instead o# using 7%&?
Because top two meta ayers are requred for goba routng n chp
desgn. If top meta ayers are aso used n bock eve t w create routng
bockage.
-n your proDect what is die size+ num$er o# metal layers+ technology+
#oundry+ num$er o# cloc,s?
De sze: te n mm eg. 1mm x 1mm ; remeber 1mm=1000mcron whch s
a bg sze !!
Meta ayers: See your tech fe. generay for 90nm t s 7 to 9.
Technoogy: Agan ook nto tech fes.
Foundry:Agan ook nto tech fes; eg. TSMC, IBM, ARTISAN etc
Cocks: Look nto your desgn and SDC fe !
How many macros in your design?
You know t we as you have desgned t ! A SoC (System On Chp) desgn
may have 100 macros aso !!!!
What is each macro size and num$er o# standard cell count?
Depends on your desgn.
What are the input needs #or your design?
For synthess: RTL, Technoogy brary, Standard ce brary, Constrants
For Physca desgn: Netst, Technoogy brary, Constrants, Standard ce
brary
What is 0<. constraint #ile contains?
Cock defntons
Tmng excepton-mutcyce path, fase path
Input and Output deays
How did you do power planning?
How to calculate core ring width+ macro ring width and strap or trun,
width?
How to #ind num$er o# power pad and -2 power pads?
How the width o# metal and num$er o# straps calculated #or power and
ground?
Get the tota core power consumpton; get the meta ayer current densty
vaue from the tech fe; Dvde tota power by number sdes of the chp;
Dvde the obtaned vaue from the current densty to get core power rng
wdth. Then cacuate number of straps usng some more equatons. W
be expaned n deta ater.
How to #ind total chip power?
Tota chp power=standard ce power consumpton,Macro power
consumpton pad power consumpton.
What are the pro$lems #aced related to timing?
Preayout: Setup, Max transton, max capactance
Post ayout: Hod
How did you resol"e the setup and hold pro$lem?
Setup: upsze the ces
Hod: nsert buffers
-n which layer do you pre#er #or cloc, routing and why?
Next ower ayer to the top two meta ayers(goba routng ayers).
Because t has ess resstance hence ess RC deay.
-# in your design has reset pin+ then it*ll a##ect input pin or output pin or
$oth?
Output pn.
<uring power analysis+ i# you are #acing -A drop pro$lem+ then how did
you a"oid?
Increase power meta ayer wdth.
Go for hgher meta ayer.
Spread macros or standard ces.
Provde more straps.
<e#ine antenna pro$lem and how did you resol"e these pro$lem?
Increased net ength can accumuate more charges whe manufacturng
of the devce due to onsaton process. If ths net s connected to gate of
the MOSFET t can damage deectrc property of the gate and gate may
conduct causng damage to the MOSFET. Ths s antenna probem.
Decrease the ength of the net by provdng more vas and ayer |umpng.
Insert antenna dode.
How delays "ary with di##erent 6V/ conditions? 0how the graph5
P ncrease->deay ncrease
P decrease->deay decrease
V ncrease->deay decrease
V decrease->deay ncrease
T ncrease->deay ncrease
T decrease->deay decrease
34plain the #low o# physical design and inputs and outputs #or each step
in #low5
Cck here to see the fow dagram
What is cell delay and net delay?
Hate delay
Transstors wthn a gate take a fnte tme to swtch. Ths means that a
change on the nput of a gate takes a fnte tme to cause a change on the
output.|Magma|
Gate deay =functon of(/p transton tme, Cnet+Cpn).
Ce deay s aso same as Gate deay.
.ell delay
For any gate t s measured between 50% of nput transton to the
correspondng 50% of output transton.
Intrnsc deay
Intrnsc deay s the deay nterna to the gate. Input pn of the ce to
output pn of the ce.
It s defned as the deay between an nput and output par of a ce, when
a near zero sew s apped to the nput pn and the output does not see
any oad condton.It s predomnanty caused by the nterna capactance
assocated wth ts transstor.
Ths deay s argey ndependent of the sze of the transstors formng the
gate because ncreasng sze of transstors ncrease nterna capactors.
Get <elay (or wire delay!
The dfference between the tme a sgna s frst apped to the net and the
tme t reaches other devces connected to that net.
It s due to the fnte resstance and capactance of the net.It s aso known
as wre deay.
Wre deay =fn(Rnet , Cnet+Cpn)
What are delay models and what is the di##erence $etween them?
Lnear Deay Mode (LDM)
Non Lnear Deay Mode (NLDM)
What is wire load model?
Wre oad mode s NLDM whch has estmated R and C of the net.
Why higher metal layers are pre#erred #or Vdd and Vss?
Because t has ess resstance and hence eads to ess IR drop.
What is logic optimization and gi"e some methods o# logic optimization5
Upszng
Downszng
Buffer nserton
Buffer reocaton
Dummy buffer pacement
What is the signi#icance o# negati"e slac,?
negatve sack==> there s setup voaton==> desgn can fa
What is signal integrity? How it a##ects /iming?
IR drop, Eectro Mgraton (EM), Crosstak, Ground bounce are sgna
ntegrty ssues.
If Idrop s more==>deay ncreases.
crosstak==>there can be setup as we as hod voaton.
What is -A drop? How to a"oid? How it a##ects timing?
There s a resstance assocated wth each meta ayer. Ths resstance
consumes power causng votage drop .e.IR drop.
If IR drop s more==>deay ncreases.
What is 3& and it e##ects?
Due to hgh current fow n the meta atoms of the meta can dspaced
from ts orga pace. When t happens n arger amount the meta can
open or bugng of meta ayer can happen. Ths effect s known as Eectro
Mgraton.
Affects: Ether short or open of the sgna ne or power ne.
What are types o# routing?
Goba Routng
Track Assgnment
Deta Routng
What is latency? Hi"e the types?
0ource %atency
It s known as source atency aso. It s defned as "the deay from the
cock orgn pont to the cock defnton pont n the desgn".
Deay from cock source to begnnng of cock tree (.e. cock defnton
pont).
The tme a cock sgna takes to propagate from ts dea waveform orgn
pont to the cock defnton pont n the desgn.
Getwor, latency
It s aso known as Inserton deay or Network atency. It s defned as "the
deay from the cock defnton pont to the cock pn of the regster".
The tme cock sgna (rse or fa) takes to propagate from the cock
defnton pont to a regster cock pn.
What is trac, assignment?
Second stage of the routng wheren partcuar meta tracks (or ayers) are
assgned to the sgna nets.
What is congestion?
If the number of routng tracks avaabe for routng s ess than the
requred tracks then t s known as congeston.
Whether congestion is related to placement or routing?
Routng
What are cloc, trees?
Dstrbuton of cock from the cock source to the sync pn of the regsters.
What are cloc, tree types?
H tree, Baanced tree, X tree, Custerng tree, Fsh bone
What is cloning and $u##ering?
Conng s a method of optmzaton that decreases the oad of a heavy
oaded ce by repcatng the ce.
Bufferng s a method of optmzaton that s used to nsert beffers n hgh
fanout nets to decrease the deay.
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Physca Desgn Intervew Ouestons
Net Deay or Interconnect Deay or Wre Deay or Extrnsc Deay or Fght Tme
What are the dfferent types of deays n ASIC or VLSI desgn?
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:0 Go"em$er 2007
(hat is the difference between soft $acro and hard $acro?
What is the di##erence $etween hard macro+ #irm macro and so#t
macro?
or
What are -6s?
Hard macro, frm macro and soft macro are a known as IP (Inteectua
property). They are optmzed for power, area and performance. They can
be purchased and used n your ASIC or FPGA desgn mpementaton fow.
Soft macro s fexbe for a type of ASIC mpementaton. Hard macro can
be used n pure ASIC desgn fow, not n FPGA fow. Before byng any IP t
s very mportant to evauate ts advantages and dsadvantages over each
other, hardware compatbty such as I/O standards wth your desgn
bocks, reusabty for other desgns.
0o#t macros
Soft macros are n syntheszabe RTL.
Soft macros are more fexbe than frm or hard macros.
Soft macros are not specfc to any manufacturng process.
Soft macros have the dsadvantage of beng somewhat unpredctabe n
terms of performance, tmng, area, or power.
Soft macros carry greater IP protecton rsks because RTL source code s
more portabe and therefore, ess easy protected than ether a netst or
physca ayout data.
From the physca desgn perspectve, soft macro s any ce that has been
paced and routed n a pacement and routng too such as Astro. (Ths s
the defnton gven n Astro Ra user manua !)
Soft macros are edtabe and can contan standard ces, hard macros, or
other soft macros.
1irm macros
Frm macros are n netst format.
Frm macros are optmzed for performance/area/power usng a specfc
fabrcaton technoogy.
Frm macros are more fexbe and portabe than hard macros.
Frm macros are predctve of performance and area than soft macros.
Hard macro
Hard macros are generay n the form of hardware IPs (or we termed t as
hardwre IPs !).
Hard macos are targeted for specfc IC manufacturng technoogy.
Hard macros are bock eve desgns whch are scon tested and proved.
Hard macros have been optmzed for power or area or tmng.
In physca desgn you can ony access pns of hard macros unke soft
macros whch aows us to manpuate n dfferent way.
You have freedom to move, rotate, fp but you can't touch anythng nsde
hard macros.
Very common exampe of hard macro s memory. It can be any desgn
whch carres dedcated snge functonaty (n genera).. for exampe t
can be a MP4 decoder.
Be aware of features and characterstcs of hard macro before you use t n
your desgn... other than power, tmng and area you aso shoud know pn
propertes ke sync pn, I/O standards etc
LEF, GDS2 fe format aows easy usage of macros n dfferent toos.
From the physca desgn (backend) perspectve:
Hard macro s a bock that s generated n a methodoogy other than pace
and route (.e. usng fu custom desgn methodoogy) and s brought nto
the physca desgn database (eg. Mkyway n Synopsys; Vocano n
Magma) as a GDS2 fe.
Here s one artce pubshed n embedded magazne about IPs. Cck here
to read.
Synthess and pacement of macros n modern SoC desgns are chaengng. EDA
toos empoy dfferent agorthms accompsh ths task aong wth the target of
power and area. There are severa research papers avaabe on these sub|ects.
Some of them can be downoaded from the gven nk beow.
"Hard Macro Pacement n Compex SoC Desgn" - vew and read artce
from soccentra
"Hard Macro Pacement n Compex SoC Desgn" - downoad whte paper
-333/@ni"erity research papers
"Loca Search for Fna Pacement n VLSI Desgn" - downoad
"Consstent Pacement of Macro-Bocks Usng Foorpannng and standard
ce pacement" - downoad
"A Tmng-Drven Soft-Macro Pacement And Resynthess Method In
Interacton wth Chp Foorpannng" - downoad
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2? 2cto$er 2007
(hat is difference between nor$al buffer and clock buffer?
Answer:
%lock net is one of the "igh :anout 1et+":10s. #he clock buffers are designed with some
special property like high drive strength and less delay. %lock buffers have equal rise and fall
time. #his prevents duty cycle of clock signal from changing when it passes through a chain
of clock buffers.
1ormal buffers are designed with WD ratio such that sum of rise time and fall time is
minimum. #hey too are designed for higher drive strength.
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Physca Desgn Intervew Ouestons
Synthess Intervew Ouestons
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(hat is difference between !64 synthesis and C30?
Answer2
!64s are synthesi-ed in front end also.... but at that moment no placement information of
standard cells are available... hence backend tool collapses synthesi-ed ":1s. *t
resenthesi-es ":1s based on placement information and appropriately inserts buffer. #arget
of this synthesis is to meet delay requirements i.e. setup and hold.
:or clock no synthesis is carried out in front end +why.....8888..because no placement
information of flip$flops / )o synthesis wonBt meet true skew targets //0 ... in backend clock
tree synthesis tries to meet UskewU targets...*t inserts clock buffers +which have equal rise and
fall time, unlike normal buffers /0... #here is no skew information for any ":1s.
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Cock Tree Synthess (CTS)
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Is it possible to have a .ero skew in the design?
Answer2
#heoretically it is possible..../
6ractically it is impossible....//
6ractically we cant reduce any delay to -ero.... delay will exist... hence we try to make skew
UequalU +or same0 rather than U-eroU......now with this optimi-ation all flops get the clock
edge with same delay relative to each other.... so virtually we can say they are having U-ero
skew U or skew is UbalancedU.
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Physca Desgn Ouestons and Answers
Cock Defntons
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88 2cto$er 2007
Physical Design Interview Questions
Below are the important interview questions for ()* physical design aspirants. *nterview
starts with flow of physical design and goes on.....on....on..... * am trying to make your life
easy..... let me prepare answers to all these if soft form.... as soon as it happens those answers
will be posted in coming blogs.
What parameters (or aspects) differentiate Chip Design & Block level design??
How do yo place macros in a fll chip design?
Differentiate !etween a Hierarchical Design and flat design?
Which is more complicated when have a "# $H% and &'' $H% clock design?
(ame few tools which yo sed for physical verification?
What are the inpt files will yo give for primetime correlation?
What are the algorithms sed while roting? Will it optimi%e wire length?
How will yo decide the )in location in !lock level design?
*f the roting congestion e+ists !etween two macros, then what will yo do?
How will yo place the macros?
How will yo decide the die si%e?
*f lengthy metal layer is connected to diffsion and poly, then which one will affect !y
antenna pro!lem?
*f the fll chip design is roted !y - layer metal, why macros are designed sing &.$
instead of sing -.$?
*n yor pro/ect what is die si%e, nm!er of metal layers, technology, fondry, nm!er
of clocks?
How many macros in yor design?
What is each macro si%e and no0 of standard cell cont?
How did handle the Clock in yor design?
What are the *npt needs for yor design?
What is 1DC constraint file contains?
How did yo do power planning?
How to find total chip power?
How to calclate core ring width, macro ring width and strap or trnk width?
How to find nm!er of power pad and *2 power pads?
What are the pro!lems faced related to timing?
How did resolve the setp and hold pro!lem?
*f in yor design 3'''' and more nm!ers of pro!lems come, then what yo will do?
*n which layer do yo prefer for clock roting and why?
*f in yor design has reset pin, then it4ll affect inpt pin or otpt pin or !oth?
Dring power analysis, if yo are facing *5 drop pro!lem, then how did avoid?
Define antenna pro!lem and how did resolve these pro!lem?
How delays vary with different )67 conditions? 1how the graph0
8+plain the flow of physical design and inpts and otpts for each step in flow0
What is cell delay and net delay?
What are delay models and what is the difference !etween them?
What is wire load model?
What does 1DC constraints has?
Why higher metal layers are preferred for 6dd and 6ss?
What is logic optimi%ation and give some methods of logic optimi%ation0
What is the significance of negative slack?
What is signal integrity? How it affects 7iming?
What is *5 drop? How to avoid 0how it affects timing?
What is 8$ and it effects?
What is floor plan and power plan?
What are types of roting?
What is a grid 0why we need and different types of grids?
What is core and how will decide w9h ratio for core?
What is effective tili%ation and chip tili%ation?
What is latency? :ive the types?
How the width of metal and nm!er of straps calclated for power and grond?
What is negative slack ? How it affects timing?
What is track assignment?
What is grided and gridless roting?
What is a macro and standard cell?
What is congestion?
Whether congestion is related to placement or roting?
What are clock trees?
What are clock tree types?
Which layer is sed for clock roting and why?
What is cloning and !ffering?
What are placement !lockages?
How slow and fast transition at inpts effect timing for gates?
What is antenna effect?
What are D;$ isses?
What is 0li!, .8;, D8;, 0tf?
What is the difference !etween synthesis and simlation?
What is metal density, metal slotting rle?
What is 2)C, )1$?
Why clock is not synthesi%ed in DC?
What are high<6t and low<6t cells?
What corner cells contains?
What is the difference !etween core filler cells and metal fillers?
How to decide nm!er of pads in chip level design?
What is tie<high and tie<low cells and where it is sed
What is .8;?
What is D8;?
What are the steps involved in designing an optimal pad ring?
What are the steps that you have done n the desgn fow?
What are the ssues n foor pan?
How can you estmate area of bock?
How much aspect rato shoud be kept (or have you kept) and what s the
utzaton?
How to cacuate core rng and strpe wdths?
What f hot spot found n some area of bock? How you tacke ths?
After addng strpes aso f you have hot spot what to do?
What s threshod votage? How t affect tmng?
What s content of b, ef, sdc?
What s meant my 9 track, 12 track standard ces?
What s scan chan? What f scan chan not detached and reordered? Is t
compusory?
What s setup and hod? Why there are ? What f setup and hod voates?
In a crcut, for reg to reg path ...Tcktoq s 50 ps, Tcombo 50ps, Tsetup
50ps, tskew s 100ps. Then what s the maxmum operatng frequency?
How R and C vaues are affectng tme?
How ohm (R), fared (C) s reated to second (T)?
What s transton? What f transton tme s more?
What s dfference between norma buffer and cock buffer?
What s antenna effect? How t s avoded?
What s ESD?
What s cross tak? How can you avod?
How doube spacng w avod cross tak?
What s dfference between HFN synthess and CTS?
What s hod probem? How can you avod t?
For an teraton we have 0.5ns of nserton deay and 0.1 skew and for
other teraton 0.29ns nserton deay and 0.25 skew for the same crcut
then whch one you w seect? Why?
What s parta foor pan?
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Physca Desgn Ouestons and Answers
Synthess Intervew Ouestons
Companywse ASIC/VLSI Intervew Ouestons
CMOS Desgn Intervew Ouestons
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