1.3.

OVERLOADED OPERATORS
Description bitwise-and bitwise-or bitwise-xor bitwise-not Left u/l,uv,lv u/l,uv,lv u/l,uv,lv Operator and, nand or, nor xor, xnor not Right u/l,uv,lv u/l,uv,lv u/l,uv,lv u/l,uv,lv

2.4. CONVERSION FUNCTIONS

From un,lv sg,lv un,sg un,sg na in To sg un lv in un sg Function SIGNED(from) UNSIGNED(from) STD_LOGIC_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from, size) TO_SIGNED(from, size)

1.4. CONVERSION FUNCTIONS

From To b bv u/l lv uv Function TO_BIT(from[, xmap]) TO_BITVECTOR(from[, xmap]) TO_STDULOGIC(from) TO_STDLOGICVECTOR(from) TO_STDULOGICVECTOR(from)

3. IEEES NUMERIC_BIT
3.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) SIGNED(na to | downto na) Array of BIT Array of BIT

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Revision 2.1 () {} bold italic b bv u/l uv lv un sg in na sm ::= ::= ::= ::= ::= ::= ::= ::= ::= ::= Grouping Repeated As is VHDL-93 [] | CAPS
c

u/l uv,lv b bv,uv bv,lv

3.2. OVERLOADED OPERATORS

Left Op Right Return abs sg sg sg sg +,-,*,/,rem,mod un un +,-,*,/,rem,mod sg sg +,-,*,/,rem,mod c na un +,-,*,/,rem,mod c in sg <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c na bool <,>,<=,>=,=,/= c in bool

Optional Alternative User Identifier commutative

2. IEEES NUMERIC_STD
2.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of STD_LOGIC SIGNED(na to | downto na) Array of STD_LOGIC

BIT BIT_VECTOR STD_ULOGIC/STD_LOGIC STD_ULOGIC_VECTOR STD_LOGIC_VECTOR UNSIGNED SIGNED INTEGER NATURAL SMALL_INT (subtype INTEGER range 0 to 1)

2.2. OVERLOADED OPERATORS

Left Op Right abs sg sg +,-,*,/,rem,mod un +,-,*,/,rem,mod sg +,-,*,/,rem,mod c na +,-,*,/,rem,mod c in <,>,<=,>=,=,/= un <,>,<=,>=,=,/= sg <,>,<=,>=,=,/= c na <,>,<=,>=,=,/= c In Return sg sg un sg un sg bool bool bool bool

un sg un sg un sg un sg

1. IEEES STD_LOGIC_1164
1.1. LOGIC VALUES
U X/W 0/L 1/H Z - Uninitialized Strong/Weak unknown Strong/Weak 0 Strong/Weak 1 High Impedance Dont care

un sg un sg un sg un sg

3.3. PREDEFINED FUNCTIONS

SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) un un sg sg un un sg sg sg un

2.3. PREDEFINED FUNCTIONS

SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) STD_MATCH(u/l, u/l) STD_MATCH(ul, ul) STD_MATCH(lv, lv) STD_MATCH(un, un) STD_MATCH(sg, sg) un un sg sg un un sg sg sg un bool bool bool bool bool

3.4. CONVERSION FUNCTIONS

From un,bv sg,bv un,sg un,sg na in To sg un bv in un sg Function SIGNED(from) UNSIGNED(from) BIT_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from) TO_SIGNED(from)

1.2. PREDEFINED TYPES

STD_ULOGIC Subtypes: STD_LOGIC X01 X01Z UX01 UX01Z Base type Resolved STD_ULOGIC Resolved X, 0 & 1 Resolved X, 0, 1 & Z Resolved U, X, 0 & 1 Resolved U, X, 0, 1 & Z

STD_ULOGIC_VECTOR(na to | downto na) Array of STD_ULOGIC STD_LOGIC_VECTOR(na to | downto na) Array of STD_LOGIC 1995-1998 Qualis Design Corporation

1995-1998 Qualis Design Corporation. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted. See reverse side for additional information.

1995-1998 Qualis Design Corporation

4. SYNOPSYS STD_LOGIC_ARITH
4.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of STD_LOGIC SIGNED(na to | downto na) Array of STD_LOGIC SMALL_INT Integer subtype, 0 or 1

6. SYNOPSYS STD_LOGIC_SIGNED
6.1. OVERLOADED OPERATORS
Left Op abs +,+,-,* +,-c +,- c <,>,<=,>=,=,/= <,>,<=,>=,=,/= c Right Return lv lv lv lv lv lv in lv u/l lv lv bool in bool

9. MENTORS STD_LOGIC_ARITH
9.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of STD_LOGIC SIGNED(na to | downto na) Array of STD_LOGIC

4.2. OVERLOADED OPERATORS

Left Op abs +,-,*,/ +,-,*,/ +,-,*,/ c +,- c +,- c +,- c +,- c <,>,<=,>=,=,/= <,>,<=,>=,=,/= <,>,<=,>=,=,/= c <,>,<=,>=,=,/= c Right sg sg un sg un in in u/l u/l un sg in in Return sg,lv sg,lv un,lv sg,lv sg,lv un,lv sg,lv un,lv sg,lv bool bool bool bool

lv lv lv lv lv

9.2. OVERLOADED OPERATORS

Left Op abs +,+,-,*,/,mod,rem,** +,-,*,/,mod,rem,** +,-,*,/,mod,rem,** +,-,*,/,mod,rem,** <,>,<=,>=,=,/= <,>,<=,>=,=,/= not not and,nand,or,nor,xor and,nand,or,nor,xor,xnor sla,sra,sll,srl,rol,ror sla,sra,sll,srl,rol,ror sla,sra,sll,srl,rol,ror sla,sra,sll,srl,rol,ror Right Return sg sg sg sg u/l u/l uv uv lv lv un un sg sg un bool sg bool un un sg sg un un sg sg uv uv lv lv un un sg sg

un sg sg un sg un sg un sg un sg

6.2. CONVERSION FUNCTIONS

From lv To in Function CONV_INTEGER(from)

7. SYNOPSYS STD_LOGIC_MISC
7.1. PREDEFINED FUNCTIONS
AND_REDUCE(lv | uv) OR_REDUCE(lv | uv) XOR_REDUCE(lv | uv) un sg u/l u/l u/l

u/l uv lv un sg un sg

4.3. PREDEFINED FUNCTIONS

SHL(un, un) SHL(sg, un) EXT(lv, in) SEXT(lv, in) un sg lv lv SHR(un, un) SHR(sg, un) zero-extend sign-extend

8. CADENCES STD_LOGIC_ARITH
8.1. OVERLOADED OPERATORS
Left u/l lv lv lv uv uv uv lv uv Op +,-,*,/ +,-,*,/ +,-,*,/c +,-c +,-,* +,-,*c +,-c <,>,<=,>=,=,/= c <,>,<=,>=,=,/= c Right Return u/l u/l lv lv u/l lv in lv uv uv u/l uv in uv in bool in bool

un sg uv lv un sg

9.3. PREDEFINED FUNCTIONS

ZERO_EXTEND(uv | lv | un, na) ZERO_EXTEND(u/l, na) SIGN_EXTEND(sg, na) AND_REDUCE(uv | lv | un | sg) OR_REDUCE(uv | lv | un | sg) XOR_REDUCE(uv | lv | un | sg) same lv sg u/l u/l u/l

4.4. CONVERSION FUNCTIONS

From un,lv sg,lv sg,un un,sg in,un,sg,u in,un,sg,u in,un,sg,u To Function sg SIGNED(from) un UNSIGNED(from) lv STD_LOGIC_VECTOR(from) in CONV_INTEGER(from) un CONV_UNSIGNED(from, size) sg CONV_SIGNED(from, size) lv CONV_STD_LOGIC_VECTOR(from, size)

9.4. CONVERSION FUNCTIONS

From To Function u/l,uv,lv,un,sg in TO_INTEGER(from) u/l,uv,lv,un,sg in CONV_INTEGER(from) bool u/l TO_STDLOGIC(from) na un TO_UNSIGNED(from,size) na un CONV_UNSIGNED(from,size) in sg TO_SIGNED(from,size) in sg CONV_SIGNED(from,size) na lv TO_STDLOGICVECTOR(from,size) na uv TO_STDULOGICVECTOR(from,size) 1995-1998 Qualis Design Corporation. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted.

8.2. PREDEFINED FUNCTIONS

SH_LEFT(lv, na) SH_LEFT(uv, na) SH_RIGHT(lv, na) SH_RIGHT(uv, na) ALIGN_SIZE(lv, na) ALIGN_SIZE(uv, na) ALIGN_SIZE(u/l, na) C-like ?: replacements: COND_OP(bool, lv, lv) COND_OP(bool, uv, uv) COND(bool, u/l, u/l) lv uv lv uv lv uv lv,uv lv uv u/l

5. SYNOPSYS STD_LOGIC_UNSIGNED
5.1. OVERLOADED OPERATORS
Left lv lv lv lv lv Op Right Return + lv lv +,-,* lv lv +,-c in lv +,- c u/l lv <,>,<=,>=,=,/= lv bool <,>,<=,>=,=,/= c in bool

5.2. CONVERSION FUNCTIONS

From lv To in Function CONV_INTEGER(from)

8.3. CONVERSION FUNCTIONS

From lv,uv,u/l in in To in lv uv Function TO_INTEGER(from) TO_STDLOGICVECTOR(from, size) TO_STDULOGICVECTOR(from, size)

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1995-1998 Qualis Design Corporation

1995-1998 Qualis Design Corporation