FET AC Analysis

Input Impedance:
Z IN = RG Self Biased

Z IN = RG1 RG 2 Voltage Divider Biased

Output Impedance: Z OUT = RD Voltage Gain: AV = gm( RD RL ) 1 + gm( RS ) If there is a bypass capacitor around RS .

RS = 0

equivalent circuit for FET

RG RS

gm(V gs)

RD

RL