K THUT S 2- BI TP VHDL SVTH: HUNH NGUYN LC MSSV: 12086701 LP: HT8ALT BI 1: THIT K B GII M T 3 SANG 8 S DNG CU TRC WHENELSE

CODE VHDL
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY GIAIMA_3_TO_8 IS PORT ( ENABLE: IN STD_LOGIC; X: IN STD_LOGIC_VECTOR(2 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END GIAIMA_3_TO_8; ARCHITECTURE BAI_1 OF GIAIMA_3_TO_8 IS BEGIN Y <= "00000001" WHEN X = "000" AND ENABLE='0' ELSE "00000010" WHEN X = "001" AND ENABLE='0' ELSE "00000100" WHEN X = "010" AND ENABLE='0' ELSE "00001000" WHEN X = "011" AND ENABLE='0' ELSE "00010000" WHEN X = "100" AND ENABLE='0' ELSE "00100000" WHEN X = "101" AND ENABLE='0' ELSE "01000000" WHEN X = "110" AND ENABLE='0' ELSE "10000000" WHEN X = "111" AND ENABLE='0' ELSE "00000000"; END BAI_1;

BI 2: THIT K B GII M NH PHN CHO MT LED ANODE CHUNG. CODE VHDL

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY BCD_LED IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 downto 0); segs : OUT STD_LOGIC_VECTOR(6 downto 0)); END BCD_LED; ARCHITECTURE BAI_2 OF BCD_LED IS BEGIN PROCESS(bcd) BEGIN CASE bcd IS WHEN "0000" => segs <= "0000001"; WHEN "0001" => segs <= "1001111"; WHEN "0010" => segs <= "0010010"; WHEN "0011" => segs <= "0000110"; WHEN "0100" => segs <= "1001100"; WHEN "0101" => segs <= "0100100"; WHEN "0110" => segs <= "0100000"; WHEN "0111" => segs <= "0001111"; WHEN "1000" => segs <= "0000000"; WHEN "1001" => segs <= "0000100"; WHEN OTHERS => segs <= "0000000"; END CASE; END PROCESS; END BAI_2;

BI 3: THIT K MT ALU 4BIT THC HIN CC PHP TON: S2 0 0 0 0 1 1 1 S1 S0 PHP TON 0 0 A+B 0 1 A+1 1 0 B+1 1 1 A 0 0 A-B 0 1 A XOR B 1 0 A AND B CODE VHDL

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ALU_4BIT IS PORT( S: IN STD_LOGIC_VECTOR (2 DOWNTO 0); A,B: IN STD_LOGIC_VECTOR (3 DOWNTO 0); F: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END ALU_4BIT; ARCHITECTURE BAI_3 OF ALU_4BIT IS BEGIN PROCESS(S,A,B) BEGIN CASE S IS WHEN "000"=> F<= A + B; WHEN "001"=> F<=A + 1; WHEN "010"=> F<=B + 1;

WHEN "011"=> F<= A; WHEN "100"=> F<=A - B; WHEN "101"=> F<=A XOR B; WHEN "110"=> F<=A AND B; WHEN OTHERS=> F<= "0000"; END CASE; END PROCESS; END BAI_3;

BI 4: THIT K MT B M THP PHN T 0 N 9 CODE VHDL

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY COUNTER_THAPPHAN IS PORT ( Clk, Rst : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 downto 0)); END COUNTER_THAPPHAN; ARCHITECTURE BAI_4 OF COUNTER_THAPPHAN IS BEGIN PROCESS (Clk, Rst) VARIABLE count: STD_LOGIC_VECTOR (3 downto 0); BEGIN IF Rst ='1' THEN count := (others=>'0'); ELSIF rising_edge(clk) THEN

IF count = "1001" then count := (others=>'0'); ELSE count := count + "0001"; END IF; END IF; Q <= count; END PROCESS; END BAI_4;

BI 1(BI TP LN S 2): THIT K FSM C GRAP TRNG THI NH SAU:

CODE VHDL
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BAI_1 IS PORT( clock : IN STD_LOGIC; reset : IN STD_LOGIC; C : IN STD_LOGIC; a,b : OUT STD_LOGIC); END BAI_1; ARCHITECTURE Behavioral OF BAI_1 IS TYPE state_type IS (s0,s1,s2,s3);

SIGNAL state : state_type; BEGIN Next_state_logic : PROCESS (clock,reset) BEGIN IF(reset='1')THEN state <= s0; ELSIF(clock'EVENT AND clock = '1')THEN CASE state IS WHEN s0=> IF C='1' THEN state <=s3; ELSE state <=s1; END IF; WHEN s1=> IF C='1' THEN State <= s0; ELSE State <=s2; END IF; WHEN s2=> IF C='1' THEN state <=s1; ELSE state <=s0; END IF; WHEN s3=> state <=s0; END CASE; END IF;

END PROCESS; Out_logic: PROCESS (state) BEGIN CASE state IS WHEN s0=> a<='0'; b<='0'; WHEN s1=> a<='1'; b<='0'; WHEN s2=> a<='0'; b<='0'; WHEN s3=> a<='0'; b<='1'; END CASE; END PROCESS; END Behavioral;

BI 2 (BI TP LN S 2): THIT K FSM C GRAP TRNG THI NH SAU:

CODE VHDL
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BAI_2 IS PORT( Clock : IN STD_LOGIC; reset : IN STD_LOGIC; A,B : IN STD_LOGIC; X,Y: OUT STD_LOGIC); END BAI_2; ARCHITECTURE Behavioral OF BAI_2 IS TYPE state_type IS (s0,s1,s2,s3); SIGNAL state : state_type; BEGIN Next_state_logic : PROCESS (clock,reset) BEGIN IF (reset='1') THEN state <= s0; ELSIF (clock'EVENT AND clock ='1')THEN CASE state IS WHEN s0=> IF A='0' THEN state <=s1; ELSE state <=s0; END IF; WHEN s1=> IF A='0' AND B='0' THEN State <= s0; ELSIF A='0' AND B='1' THEN State <= s2;

ELSIF A='1' AND B='0' THEN State <= s1; ELSE State <=s3; END IF; WHEN s2=> IF A='0' THEN state <=s1; ELSE state <=s2; END IF; WHEN s3=> IF A='0' THEN state <=s0; ELSE state <=s3; END IF; END CASE; END IF; END PROCESS; Out_logic: PROCESS (state) BEGIN CASE state IS WHEN s0=> X<='1'; Y<='1'; WHEN s1=> X<='0'; Y<='0'; WHEN s2=>

X<='1'; Y<='1'; WHEN s3=> X<='1'; Y<='1'; END CASE; END PROCESS; END Behavioral;

BI 3 (BI TP LN S 2): THIT K FSM C S MCH NH SAU:

CODE VHDL
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BAI_3 IS PORT( Clock : IN STD_LOGIC; reset : IN STD_LOGIC; start : IN STD_LOGIC;

LoadN, LoadM: OUT STD_LOGIC); END BAI_3; ARCHITECTURE Behavioral OF BAI_3 IS TYPE state_type IS (s0,s1,s2,s3,s4,s5,s6,s7); SIGNAL state : state_type; BEGIN Next_state_logic : PROCESS (clock,reset) BEGIN IF (reset='1') THEN state <= s0; ELSIF (clock'EVENT AND clock='1') THEN CASE state IS WHEN s0=> IF start='1' THEN state <=s6; ELSE state <=s7; END IF; WHEN s1=> state <=s6; WHEN s2=> State <=s3; WHEN s3=> State<=s4; WHEN s4=> IF start='1' THEN state <=s4; ELSE state <=s7; END IF;

WHEN s5=> IF start='1' THEN state <=s5; ELSE state <=s4; END IF; WHEN s6=> state<=s1; WHEN s7=> IF start='1' THEN state <=s1; ELSE state <=s0; END IF; END CASE; END IF; END PROCESS; Out_logic: PROCESS (state) BEGIN CASE state IS WHEN s0=> LoadN<='0'; LoadM<='0'; WHEN s1=> LoadN<='0'; LoadM<='0'; WHEN s2=> LoadN<='0'; LoadM<='1'; WHEN s3=>

LoadN<='0'; LoadM<='0'; WHEN s4=> LoadN<='0'; LoadM<='0'; WHEN s5=> LoadN<='0'; LoadM<='0'; WHEN s6=> LoadN<='0'; LoadM<='0'; WHEN s7=> LoadN<='1'; LoadM<='0'; END CASE; END PROCESS; END Behavioral;

BI 4 (BI TP LN S 2): THIT K FSM M T HOT NG CA N GIAO THNG 1 TR, C TH: N XANH: 12s, N VNG: 3s, N : 15s - Nu reset chu k bt u li vi n xanh sng. - Chn STOP c tc dng reset v n LP GRAP NH SAU:

CODE VHDL
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BAI_4_DEN_GIAO_THONG IS PORT( Clock : IN STD_LOGIC; reset : IN STD_LOGIC; s : IN STD_LOGIC; light: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END BAI_4_DEN_GIAO_THONG; ARCHITECTURE Behavioral OF BAI_4_DEN_GIAO_THONG IS TYPE state_type IS (s0,s1,s2,s3); SIGNAL state : state_type; SIGNAL count: STD_LOGIC_VECTOR (3 DOWNTO 0); CONSTANT SEC12: STD_LOGIC_VECTOR (3 DOWNTO 0):= "1100"; CONSTANT SEC3: STD_LOGIC_VECTOR (3 DOWNTO 0):= "0011"; BEGIN Next_state_logic : PROCESS (clock,reset,s) BEGIN

IF (reset='1') THEN state<= s0; count<= X"0"; ELSIF (clock'EVENT AND clock ='1')THEN CASE state IS WHEN s0=> IF s='0' THEN state<=s3; count<= X"0"; ELSIF count>=SEC12 AND s='1' THEN state<=s1; count<= X"0"; ELSE state<=s0; count<= count + 1; END IF; WHEN s1=> if s='0' then state<=s3; count<= X"0"; elsif count>=SEC3 AND s='1' then state<=s2; count<= X"0"; ELSE state<=s1; count<= count + 1; END IF; WHEN s2=> IF count<SEC12 THEN state<=s2;

count<= count + 1; ELSE state<=s3; count<= X"0"; END IF; WHEN s3=> IF count<SEC3 or s='0'THEN state<=s3; count<= count + 1; ELSE state<=s0; count<= X"0"; end if; END CASE; END IF; END PROCESS; Out_logic: PROCESS (state) BEGIN CASE state IS WHEN s0=> light<="100"; WHEN s1=> light<="010"; WHEN s2=> light<="001"; WHEN s3=> light<="001"; END CASE; END PROCESS; END Behavioral;

BI 5 (BI TP LN S 2): THIT K FSM M T HOT NG B M LN/XUNG CA S BCD 1 DIGIT, HIN TH RA LED 7 ON ANODE CHUNG. CODE VHDL
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity BAI_5 is port ( clk: in std_logic; reset: in std_logic; s: in std_logic; q: out std_logic_vector(3 downto 0)); end BAI_5; architecture behavioral of BAI_5 is signal value: std_logic_vector(3 downto 0); begin process(clk,reset,s,value) begin if reset ='1' then value<= "0000"; elsif clk='1' and clk'event then if s='1' then if value<="1000" then value<= value + "0001"; else value<= "0000"; end if; elsif s='0'then if value<"1010" and value>"0000" then

value<= value - "0001"; else value<="1001"; end if; end if; end if; end process; q<=value; end behavioral;

BI 6 (BI TP LN S 2): THIT K FSM M T HOT NG B M LN/XUNG CA S BCD 2 DIGIT(00-12), HIN TH RA LED 7 ON ANODE CHUNG. CODE VHDL
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY BAI_6 IS PORT ( clk, reset: IN STD_LOGIC; count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END BAI_6; ARCHITECTURE BO_DEM_BCD OF BAI_6 IS TYPE state IS (zero, one, two, three, four,five, six, seven, eight, nine,ten,eleven,twelve); SIGNAL pr_state, nx_state: state; BEGIN PROCESS (reset, clk) BEGIN IF (reset='1') THEN pr_state <= zero; ELSIF (clk'EVENT AND clk='1') THEN pr_state <= nx_state; END IF;

END PROCESS; PROCESS (pr_state) BEGIN CASE pr_state IS WHEN zero => count<= "0000"; nx_state <= one; WHEN one => count<= "0001"; nx_state <= two; WHEN two => count<= "0010"; nx_state <= three; WHEN three => count<= "0011"; nx_state <= four; WHEN four => count<= "0100"; nx_state <= five; WHEN five => count<= "0101"; nx_state <= six; WHEN six => count<= "0110"; nx_state <= seven; WHEN seven => count<= "0111"; nx_state <= eight; WHEN eight => count<= "1000";

nx_state <= nine; WHEN nine => count<= "1001"; nx_state <= ten; WHEN ten => count<= "1010"; nx_state <= eleven; WHEN eleven => count<= "1011"; nx_state <= twelve; WHEN twelve => count<= "1100"; nx_state <= zero; END CASE; END PROCESS; END BO_DEM_BCD;