//Verilog para la maquina de estados

module controlador (input clk,

input reset,
input C,
output y);
reg [3:0] state, nexstate;
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter

S0=4'b0000;
S1=4'b0011;
S2=4'b0010;
S3=4'b0101;
S4=4'b0100;
S5=4'b0111;
S6=4'b0110;
S7=4'b1000;

//Registro de estados
always @ (posedge clk, posegde reset)
if(reset) state<=S0;
else
state<=nextstate;
always @(*)
case(state)
S0: if(C=0) nextstate=S0;
S0: if(C=1) nextstate=S1;
S1:
nextstate=S2;
S2: if(C=0) nextstate=S2;
S2: if(C=1) nextstate=S3;
S3:
nextstate=S4;
S4: if(C=0) nextstate=S4;
S4: if(C=1) nextstate=S5;
S5:
nextstate=S6;
S6: if(C=0) nextstate=S6;
S6: if(C=1) nextstate=S7;
S7:
nextstate=S7;
default: nextstate=S0;
endcase
assing D=(state==SO[3:1]);
assign y=(state==S0[0]);
endmodule

module juego (input [3:0] j1,

input [3:0] j2,
output C)
reg
reg
reg
reg

[3:0]
[3:0]
[3:0]
[3:0]

wire sum;
wire data;

A;
B;
Add;
add1;

parameter
parameter
parameter
parameter

Add0=4'b0000;
A0=4'b0000;
B0=4'b0000;
add10=4'b0000;

assign sum=add1+Y;
always @ (posedge clk,posedge reset)
if(reset) add1<=add10;
else add1<=sum;
always @ (posedge clk,posedge reset)
if(reset) A<=A0;
else A<=j2;
always @ (posedge clk,posedge reset)
if(reset) B<=B0;
else B<=data;
always @ (posedge clk,posedge reset)
if(reset) Add<=Add0;
else Add<=j1;
always @ (*)
if(A==B) C=1;
else C=0;
end module

module sevenseg(input [3:0] data,

output reg [6:0] segments);
always @(*)
case (data)
0: segments = 7'b000_0001;
1: segments = 7'b100_1111;
2: segments = 7'b001_0010;
3: segments = 7'b000_0110;
4: segments = 7'b100_1100;
5: segments = 7'b010_0100;
6: segments = 7'b010_0000;
7: segments = 7'b000_1111;
8: segments = 7'b000_0000;
9: segments = 7'b000_0100;
default: segments = 7'b111_1111; // required endcase
endmodule

//todo
module juego (input [3:0] j1,
input [3:0] j2,

output reg [6:0] segmentos);

reg [3:0] A;
reg [3:0] B;
reg [3:0] Add;
reg [3:0] add1;
reg [3:0] state, nexstate;
wire sum;
wire data;
wire y;
wire segm;
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter

S0=4'b0000;
S1=4'b0011;
S2=4'b0010;
S3=4'b0101;
S4=4'b0100;
S5=4'b0111;
S6=4'b0110;
S7=4'b1000;
Add0=4'b0000;
A0=4'b0000;
B0=4'b0000;
add10=4'b0000;

always @ (posedge clk,posedge reset)

if(reset) add1<=add10;
else add1<=sum;
always @ (posedge clk,posedge reset)
if(reset) A<=A0;
else A<=j2;
always @ (posedge clk,posedge reset)
if(reset) B<=B0;
else B<=data;
always @ (posedge clk,posedge reset)
if(reset) Add<=Add0;
else Add<=j1;
always @ (*)
if(A==B) C=1;
else C=0;
always @ (posedge clk, posegde reset)
if(reset) state<=S0;
else
state<=nextstate;
always @(*)
case(state)
S0:
S0:
S1:
S2:
S2:
S3:
S4:
S4:
S5:
S6:

if(C=0) nextstate=S0;
if(C=1) nextstate=S1;
nextstate=S2;
if(C=0) nextstate=S2;
if(C=1) nextstate=S3;
nextstate=S4;
if(C=0) nextstate=S4;
if(C=1) nextstate=S5;
nextstate=S6;
if(C=0) nextstate=S6;

S6: if(C=1) nextstate=S7;

default: nextstate=S0;
endcase
assign segm==(state==S0[3:1]);
assign y=(state==S0[0]);
assign sum=add1+y;
always @(*)
case (segm)
0: segments = 7'b111_1110;
1: segments = 7'b011_0000;
2: segments = 7'b110_1101;
3: segments = 7'b111_1001;
4: segments = 7'b011_0011;
5: segments = 7'b101_1011;
6: segments = 7'b101_1111;
7: segments = 7'b111_0000;
8: segments = 7'b111_1111;
9: segments = 7'b111_1011;
default: segments = 7'b000_0000; // required endcase
end case
end module

module juego (

input clk,
input reset,
input [3:0] j1,
input [3:0] j2,
input [3:0] salmem;
output [3:0] enmem;
output reg [6:0] segmentos);

reg [3:0] A;
reg [3:0] B;
reg [3:0] Add;
reg [3:0] add1;
reg [3:0] state, nexstate;
wire sum;
wire y;
wire segm;
parameter S0=4'b0000;
parameter S1=4'b0011;
parameter S2=4'b0010;

parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter

S3=4'b0101;
S4=4'b0100;
S5=4'b0111;
S6=4'b0110;
S7=4'b1000;
Add0=4'b0000;
A0=4'b0000;
B0=4'b0000;
add10=4'b0000;

always @ (posedge clk,posedge reset)

if(reset) add1<=add10;
else add1<=sum;
always @ (posedge clk,posedge reset)
if(reset) A<=A0;
else A<=j2;
always @ (posedge clk,posedge reset)
if(reset) B<=B0;
else B<=salmem;
always @ (posedge clk,posedge reset)
if(reset) Add<=Add0;
else Add<=j1;
always @ (*)
if(A==B) C=1;
else C=0;
always @ (posedge clk, posegde reset)
if(reset) state<=S0;
else
state<=nextstate;
always @(*)
case(state)
S0: if(C=0) nextstate=S0;
S0: if(C=1) nextstate=S1;
S1:
nextstate=S2;
S2: if(C=0) nextstate=S2;
S2: if(C=1) nextstate=S3;
S3:
nextstate=S4;
S4: if(C=0) nextstate=S4;
S4: if(C=1) nextstate=S5;
S5:
nextstate=S6;
S6: if(C=0) nextstate=S6;
S6: if(C=1) nextstate=S7;
default: nextstate=S0;
endcase
assign
assign
assign
assign

segm==(state==S0[3:1]);
y=(state==S0[0]);
sum=add1+y;
enmem=add1;

always @(*)
case (segm)
0:
1:
2:

segments = 7'b111_1110;
segments = 7'b011_0000;
segments = 7'b110_1101;

3:
segments = 7'b111_1001;
4:
segments = 7'b011_0011;
5:
segments = 7'b101_1011;
6:
segments = 7'b101_1111;
7:
segments = 7'b111_0000;
8:
segments = 7'b111_1111;
9:
segments = 7'b111_1011;
default: segments = 7'b000_0000; // required endcase
end case
end module