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Agenda: © Synopsys 2013 1
Agenda: © Synopsys 2013 1
Synopsys 2013
Workshop Goal
Obtain a basic understanding of ASIC design Flow Frequently used terminology in the ASIC flow. Understanding the Synthesis flow . Importance of Timing Analysis (STA) . Understanding Physical aware Synthesis Place and Route Flow
Synopsys 2013
Agenda DAY
1
i 1
Applying Constraints
Synopsys 2013
Agenda
DAY 2 6
ii
Analyze results
Conclusion
Synopsys 2013
Agenda
DAY 3 6
ii
Computing Delays
Analyze results
Conclusion
Synopsys 2013
Agenda
DAY 4 1 I
Data Setup
Logic Libraries
5
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Agenda
DAY 4 1 II
DESIGN PLANNING: Objectives & Assumptions Creating a Rectangular & Rectilinear Block.
Manual Placement
5
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Agenda
DAY 4 6 II
Template Based Power Network Synthesis (TPNS) Analyzing the Power Network Analyzing Congestion, Timing & IR Drop
10
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Agenda
DAY 4 1 III
5
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Agenda
DAY 5 1 IV
5
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Agenda
DAY 5 1 V
ROUTING:
5
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Agenda
DAY 5 1 VI
5
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