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Agenda

Synopsys 2013

Workshop Goal

Obtain a basic understanding of ASIC design Flow Frequently used terminology in the ASIC flow. Understanding the Synthesis flow . Importance of Timing Analysis (STA) . Understanding Physical aware Synthesis Place and Route Flow

Synopsys 2013

Agenda DAY
1
i 1

TITLE Introduction to Design Flow

Overview Of Integrated Circuits High Level Synthesis

Loading Design Data

Applying Constraints

Synopsys 2013

Agenda
DAY 2 6

ii

High level Synthesis

Synthesis and Optimization

Placement aware Synthesis

Analyze results

Conclusion

Synopsys 2013

Agenda
DAY 3 6

ii

Static Timing Analysis

Overview of STA Flow

Computing Delays

Analyze results

Conclusion

Synopsys 2013

Agenda
DAY 4 1 I

DATA SETUP: Setup Objectives

Data Setup

Logic Libraries

Physical or Reference Libraries

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Technology File and Mapping File

Agenda
DAY 4 1 II

DESIGN PLANNING: Objectives & Assumptions Creating a Rectangular & Rectilinear Block.

Placing of I/O Pins

Manual Placement

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Virtual Flat Placement

Agenda
DAY 4 6 II

DESIGN PLANNING: Creating Power Network

Power Planning Challenges

Template Based Power Network Synthesis (TPNS) Analyzing the Power Network Analyzing Congestion, Timing & IR Drop

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Agenda
DAY 4 1 III

PLACEMENT: Pre placement Setup & Checks

Scan Chain Reordering

Leakage Power Optimization

Insertion of Spare cells Incremental Optimization & Refine Placement

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Agenda
DAY 5 1 IV

CLOCK TREE SYNTHESIS:

Goals & Pre CTS Setup

Defining Clock Trees

Clock Tree Synthesis


Clock Tree Optimization & Inter Clock Delay Balancing Analyzing Timing & Clock Specifications post CTS

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Agenda
DAY 5 1 V

ROUTING:

Pre Routing Check & Setup

Global Route, Track Assignment & Detail Routing


Routing Of Clock & Signal Nets and Optimization Checking for DRC Violations & Fixing Performing Functional ECOs

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Agenda
DAY 5 1 VI

DESIGN FOR MANUFACTURABILITY:

Random Particle Defects

Wire Spreading & Wire Widening

Antenna Violations and their Fixing

Filler Cell & Metal Fill Insertion

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Final Validation & Tape out Flow

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