EC 310 (A) - VLSI IC Design: Course Project

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EC 310 (a) VLSI IC Design

Course Project

Submitted by: Amit Choubey 2010018 Rishi Jain 2010153

Sarbjeet Singh 2010171

1. Half Adder Circuit using CMOS Logic


Circuit Netlist Half Adder .options list post .param L = 180n

*ANALYSIS .tran 1m 1

*TRANSISTORS m1 n1 ina vd vd pmos w='L' l='L' m2 n1 inb vd vd pmos w='L' l='L' m3 n1 ina n2 n2 nmos w='L' l='L' m4 n2 inb gnd gnd nmos w='L' l='L' m5 n3 n1 vd vd pmos w='L' l='L' m6 n3 n1 gnd gnd nmos w='L' l='L' m7 n4 inac vd vd pmos w='L' l='L' m8 n4 inbc vd vd pmos w='L' l='L' m9 s n3 n4 n4 pmos w='L' l='L' m10 s n3 gnd gnd nmos w='L' l='L' m11 s inac n5 n5 nmos w='L' l='L' m12 n5 inbc gnd gnd nmos w='L' l='L'

*SOURCES vina ina gnd pulse ( 0 1 0 0 0 100m 200m ) vinac inac gnd pulse ( 1 0 0 0 0 100m 200m ) vinb inb gnd pulse ( 0 1 0 0 0 50m 200m )

vinbc inbc gnd pulse ( 1 0 0 0 0 50m 200m ) vdd vd gnd 1

*FILES Desktop\tsmc_180nm.txt' .include 'C:\Users\Amit Choubey\Desktop .end

Fig. Logic Gate Representation of Half Adder Circuit

Fig. Output Waveforms as seen on Avanwaves

2. XOR Gate using Transmission Logic


Circuit Netlist xor using transmission logic .options list post

.param L = 180n *ANALYSYS .tran 1m 1

Fig. XOR Gate using Transmission Logic

*TRANSISTORS m1 x inac inbc inbc pmos w='L' l='L' m2 inbc ina x x nmos w='L' l='L' m3 x ina inb inb pmos w='L' l='L' m4 inb inac x x nmos w='L' l='L'

*SOURCES vina ina gnd pulse ( 0 1 0 0 0 100m 200m ) vinac inac gnd pulse ( 1 0 0 0 0 100m 200m ) vinb inb gnd pulse ( 0 1 0 0 0 100m 300m ) vinbc inbc gnd pulse ( 1 0 0 0 0 100m 300m )

*FILES .include 'C:\Users\Amit Choubey\Desktop\tsmc_180nm.txt' .end

Fig. Output Waveforms as seen on Avanwaves

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