Features: NA555, NE555, SA555, SE555 Precision Timers

NA555, NE555, SA555, SE555 PRECISION TIMERS
www.ti.com
SLFS022F SEPTEMBER 1973 REVISED JUNE 2006
FEATURES
Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source up to 200 mA
DESCRIPTION/ORDERING INFORMATION
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW)
GND TRIG OUT RESET
1 2 3 4
8 7 6 5
VCC DISCH THRES CONT
NC GND NC VCC NC
NC TRIG NC OUT NC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC DISCH NC THRES NC
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
NC RESET NC CONT NC
Copyright 19732006, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

www.ti.com
ORDERING INFORMATION
TA VTHRES MAX VCC = 15 V PDIP P SOIC D 0C to 70C 11.2 V SOP PS TSSOP PW PDIP P 40C to 85C 11.2 V SOIC D PDIP P 40C to 105C 11.2 V SOIC D PDIP P 55C to 125C 10.6 SOIC D CDIP JG LCCC FK (1) PACKAGE (1) Tube of 50 Tube of 75 Reel of 2500 Reel of 2000 Tube of 150 Reel of 2000 Tube of 50 Tube of 75 Reel of 2000 Tube of 50 Tube of 75 Reel of 2000 Tube of 50 Tube of 75 Reel of 2500 Tube of 50 Tube of 55 ORDERABLE PART NUMBER NE555P NE555D NE555DR NE555PSR NE555PW NE555PWR SA555P SA555D SA555DR NA555P NA555D NA555DR SE555P SE555D SE555DR SE555JG SE555FK TOP-SIDE MARKING NE555P NE555 N555 N555 SA555P SA555 NA555P NA555 SE555P SE555D SE555JG SE555FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
RESET Low High High High (1) TRIGGER VOLTAGE (1) Irrelevant <1/3 VDD >1/3 VDD >1/3 VDD THRESHOLD VOLTAGE (1) Irrelevant Irrelevant >2/3 VDD <2/3 VDD OUTPUT Low High Low DISCHARGE SWITCH On Off On
As previously established
Voltage levels shown are nominal.
Submit Documentation Feedback
www.ti.com

FUNCTIONAL BLOCK DIAGRAM

VCC 8 CONT 5 RESET 4
6 THRES
2 TRIG
R1 R S 1
3 OUT
7 1 GND Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: RESET can override TRIG, which can override THRES.
DISCH

www.ti.com
Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
MIN VCC VI IO Supply voltage (2) Input voltage Output current D package JA Package thermal impedance (3) (4) P package PS package PW package JC TJ Package thermal impedance (5) (6) Operating virtual junction temperature Case temperature for 60 s Lead temperature 1, 6 mm (1/16 in) from case for 60 s Tstg (1) (2) (3) (4) (5) (6) Storage temperature range FK package JG package 65 FK package JG package CONT, RESET, THRES, TRIG MAX 18 VCC 225 97 85 95 149 5.61 14.5 150 260 300 150 C/W C C C C C/W UNIT V V mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC)/JC. Operating at the absolute maximum TJ of 150C can affect reliability. The package thermal impedance is calculated in accordance with MIL-STD-883.
Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN VCC VI IO Supply voltage Input voltage Output current NA555 TA Operating free-air temperature NE555 SA555 SE555 40 0 40 55 NA555, NE555, SA555 SE555 CONT, RESET, THRES, and TRIG 4.5 4.5 MAX 16 18 VCC 200 105 70 85 125 C UNIT V V mA
www.ti.com

Electrical Characteristics
VCC = 5 V to 15 V, TA = 25C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN THRES voltage level THRES current (1) VCC = 15 V TRIG voltage level VCC = 5 V TRIG current RESET voltage level RESET current DISCH switch off-state current VCC = 15 V VCC = 5 V VCC = 15 V, IOL = 10 mA VCC = 15 V, IOL = 50 mA VCC = 15 V, IOL = 100 mA VCC = 15 V, IOL = 200 mA VCC = 5 V, IOL = 3.5 mA VCC = 5 V, IOL = 5 mA VCC = 5 V, IOL = 8 mA VCC = 15 V, IOL = 100 mA High-level output voltage VCC = 15 V, IOH = 200 mA VCC = 15 V, IOL = 100 mA Output low, No load Supply current Output high, No load (1) 3 TA = 55C to 125C VCC = 15 V VCC = 5 V VCC = 15 V VCC = 5 V 2 10 3 9 2 12 5 10 4 10 3 9 2 15 6 13 5 mA 13 TA = 55C to 125C 12 12.5 3.3 2.75 12.5 3.3 V TA = 55C to 125C 0.1 TA = 55C to 125C 0.15 13.3 9.6 TA = 55C to 125C TA = 55C to 125C TA = 55C to 125C 0.4 TA = 55C to 125C 2 TA = 55C to 125C 2.5 0.35 0.2 0.8 0.25 12.75 0.15 13.3 0.4 0.1 0.35 9.6 2.9 2.9 0.1 3.3 TRIG at 0 V 0.3 TA = 55C to 125C RESET at VCC RESET at 0 V 0.1 0.4 20 10 4.8 TA = 55C to 125C TA = 55C to 125C 0.5 0.7 3 1.45 1.67 VCC = 15 V VCC = 5 V 9.4 2.7 SE555 TYP 10 3.3 30 5 MAX 10.6 4 250 5.2 6 1.9 1.9 0.9 1 1.1 0.4 1 100 10.4 10.4 3.8 3.8 0.15 0.2 0.5 1 2.2 2.7 2.5 2 2.5 V 0.4 0.75 0.1 0.25 2.6 3.3 4 9 0.1 0.4 20 10 0.4 1.5 100 11 V 0.3 0.5 0.7 2 1 A V mA nA 1.1 1.67 2.2 4.5 MIN 8.8 2.4 NA555 NE555 SA555 TYP 10 3.3 30 5 MAX 11.2 4.2 250 5.6 V V nA UNIT
CONT voltage (open circuit)
Low-level output voltage
This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB 3.4 M, and for VCC = 15 V, the maximum value is 10 M.

www.ti.com
Operating Characteristics
VCC = 5 V to 15 V, TA = 25C (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN Initial error of timing interval (2) Temperature coefficient of timing interval Each timer, monostable (3) Each timer, astable (5) Each timer, monostable (3) Each timer, astable (5) TA = 25C CL = 15 pF, TA = 25C CL = 15 pF, TA = 25C TA = MIN to MAX TA = 25C SE555 TYP 0.5 1.5 30 90 0.05 0.15 100 100 200 (4) 200 (4) 0.2 (4) 100 (4) MAX 1.5 (4) MIN NA555 NE555 SA555 TYP 1 2.25 50 150 0.1 0.3 100 100 300 300 0.5 MAX 3 % ppm/ C %/V ns ns UNIT
(3) Supply-voltage sensitivity of Each timer, monostable timing interval Each timer, astable (5)
Output-pulse rise time Output-pulse fall time (1) (2) (3) (4) (5)
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 k to 100 k, C = 0.1 F. On products compliant to MIL-PRF-38535, this parameter is not production tested. Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 k to 100 k, C = 0.1 F.
www.ti.com

TYPICAL CHARACTERISTICS
Data for temperatures below 0C and above 70C are applicable for SE555 circuits only.
10 7 VOL Low-Level Output Voltage V 4 2 1 0.7 0.4 0.2 0.1 0.07 0.04 0.02 0.01
VOL Low-Level Output Voltage V

VCC = 5 V TA = 55C TA = 25C
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT

10 7 4 2 1 0.7 0.4 0.2 0.1 0.07 0.04 0.02 0.01

TA = 125C 7 10 20 40 70 100

VCC = 10 V TA = 25C TA= 55C TA = 125C
10
20
40
70 100
IOL Low-Level Output Current mA
IOL Low-Level Output Current mA
Figure 1.
Figure 2.
10 7 VOL Low-Level Output Voltage V 4 2 1 0.7 0.4 0.2 0.1 0.07 0.04 0.02

VCC = 15 V TA = 125C
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT

2.0 TA = 55C
TA = 55C ( VCC VOH) Voltage Drop V
1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2
TA = 25C
0.01 1 2 4 7 10 20 40 70 100 0 IOL Low-Level Output Current mA

TA = 25C TA = 125C VCC = 5 V to 15 V
2 4 7 10 20 40 70 100 IOH High-Level Output Current mA
Figure 3.
Figure 4.

www.ti.com
TYPICAL CHARACTERISTICS (continued)

Data for temperatures below 0C and above 70C are applicable for SE555 circuits only.
SUPPLY CURRENT vs SUPPLY VOLTAGE
10 9 8 I CC Supply Current mA TA = 25C 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 13 14 15 VCC Supply Voltage V TA = 55C TA = 125C Pulse Duration Relative to Value at VCC = 10 V Output Low, No Load 1.015
NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs SUPPLY VOLTAGE
1.010
1.005
0.995
0.990
0.985 0 5 10 15 20 VCC Supply Voltage V
Figure 5.
Figure 6.
NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs FREE-AIR TEMPERATURE

1.015 Pulse Duration Relative to Value at TA = 255C VCC = 10 V 1.010 tPD Propagation Delay Time ns 250 300
PROPAGATION DELAY TIME vs LOWEST VOLTAGE LEVEL OF TRIGGER PULSE
TA = 55C 200 TA = 0C 150
1.005
0.995
100
TA = 25C TA = 70C TA = 125C
0.990
50
0.985 75
0 50 25 0 25 50 75 100 125 0 0.1 x VCC 0.2 x VCC 0.3 x VCC 0.4 x VCC TA Free-Air Temperature C Lowest Voltage Level of Trigger Pulse
Figure 7.
Figure 8.
www.ti.com

APPLICATION INFORMATION Monostable Operation

For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
VCC (5 V to 15 V)
RA
4 7 6 Input 2
5 CONT RESET DISCH
8 VCC RL
OUT THRES TRIG GND 1
Output
Pin numbers shown are for the D, JG, P, PS, and PW packages.
Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.

tw Output Pulse Duration s

RA = 9.1 k CL = 0.01 F RL = 1 k See Figure 9
www.ti.com
APPLICATION INFORMATION (continued)

10 RA = 10 M 1 RA = 1 M
101
Voltage 2 V/div
Input Voltage
102
103

Output Voltage Capacitor Voltage Time 0.1 ms/div
RA = 100 k RA = 10 k RA = 1 k
104
105 0.001
0.01
0.1
10
100
C Capacitance F
Figure 10. Typical Monostable Waveforms
Figure 11. Output Pulse Duration vs Capacitance
Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. This astable connection results in capacitor C charging and discharging between the threshold-voltage level (0.67 VCC) and the trigger-voltage level (0.33 VCC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
VCC (5 V to 15 V)
RA
CONT
4 7 RB 6 2 C
8 VCC
RESET DISCH OUT THRES TRIG GND 1 3
RL
Output
Voltage 1 V/div
Open (see Note A) 5
0.01 F

RA = 5 kW RB = 3 kW C = 0.15 F RL = 1 kW See Figure 12
t H
tL
Output Voltage
Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications.
Capacitor Voltage Time 0.5 ms/div
Figure 12. Circuit for Astable Operation
Figure 13. Typical Astable Waveforms
10
www.ti.com

APPLICATION INFORMATION (continued)

Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows:
t + 0.693 (R ) R C A B) t + 0.693 (R C L B) H
f Free-Running Frequency Hz 100 k RA + 2 RB = 1 k RA + 2 RB = 10 k 10 k RA + 2 RB = 100 k
Other useful relationships are shown below. period + t ) t + 0.693 (R ) 2R ) C H L A B 1.44 frequency [ (R ) 2R ) C A B Output driver duty cycle + L B + t )t R ) 2R H L A B t R
1k
100
10
Output waveform duty cycle t R H + 1 B + t )t R ) 2R H L A B t R B Low-to-high ratio + L + t R ) R H A B
RA + 2 RB = 1 M RA + 2 RB = 10 M
0.1 0.001
0.01
0.1
10
100
C Capacitance F
Figure 14. Free-Running Frequency
Missing-Pulse Detector
The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 16.
VCC (5 V to 15 V)
Input 2
4 RESET TRIG
Voltage 2 V/div
8 VCC OUT
RL 3
DISCH 5 0.01 F CONT GND 1
THRES

RA VCC = 5 V RA = 1 k C = 0.1 F See Figure 15 Output Input Voltage C Output Voltage Capacitor Voltage Time 0.1 ms/div
A5T3644
Pin numbers shown are shown for the D, JG, P, PS, and PW packages.
Figure 15. Circuit for Missing-Pulse Detector
Figure 16. Completed Timing Waveforms for Missing-Pulse Detector
11

www.ti.com
APPLICATION INFORMATION (continued) Frequency Divider

By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

VCC = 5 V RA = 1250 C = 0.02 F See Figure 9
Voltage 2 V/div
Input Voltage
Output Voltage
Capacitor Voltage Time 0.1 ms/div
Figure 17. Divide-by-Three Circuit Waveforms
12
www.ti.com

APPLICATION INFORMATION (continued) Pulse-Width Modulation

The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used.
VCC (5 V to 15 V)
4 RESET Clock Input 2 TRIG
8 VCC OUT 3
RL
RA
Output 7
DISCH Modulation 5 Input (see Note A) CONT THRES GND 1 C 6
Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered.

RA = 3 k C = 0.02 F RL = 1 k See Figure 18 Modulation Input Voltage Clock Input Voltage Output Voltage Capacitor Voltage Time 0.5 ms/div
Figure 18. Circuit for Pulse-Width Modulation
Voltage 2 V/div
Figure 19. Pulse-Width-Modulation Waveforms
13

www.ti.com
APPLICATION INFORMATION (continued) Pulse-Position Modulation

As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
VCC (5 V to 15 V)
4 RESET 2 TRIG
8 VCC OUT
RL 3
RA Output Voltage 2 V/div
DISCH Modulation Input 5 (see Note A) CONT GND THRES
7 RB
C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered.

RA = 3 k RB = 500 RL = 1 k See Figure 20 Modulation Input Voltage Output Voltage Capacitor Voltage Time 0.1 ms/div
Figure 20. Circuit for Pulse-Position Modulation
Figure 21. Pulse-Position-Modulation Waveforms
14
www.ti.com

APPLICATION INFORMATION (continued) Sequential Timer

Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output waveforms.
VCC
4 RESET 2 S 5 CONT TRIG
8 VCC 3 OUT DISCH 7 6
RA 33 k 2 0.001 F 5
4 RESET TRIG
8 VCC 3 OUT DISCH 7
RB
33 k 2 0.001 F 5
4 RESET TRIG
8 VCC 3 OUT DISCH 7 6
RC
THRES GND 1
CONT
0.01 F
CA
0.01 F Output A
THRES GND 1 CB
CONT
0.01 F
THRES GND 1 CC
CA = 10 F RA = 100 k
CB = 4.7 F RB = 100 k
Output B
CC = 14.7 F RC = 100 k
Output C
Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0.

See Figure 22 Output A twA Output B Output C
Figure 22. Sequential Timer Circuit

twA = 1.1 RACA twB twB = 1.1 RBCB twC twC = 1.1 RCCC t=0 t Time 1 s/div
Voltage 5 V/div
Figure 23. Sequential Timer Waveforms
15
PACKAGE OPTION ADDENDUM

www.ti.com
31-Jul-2006
PACKAGING INFORMATION
Orderable Device JM38510/10901BPA NA555D NA555DG4 NA555DR NA555DRG4 NA555P NA555PE4 NE555D NE555DE4 NE555DG4 NE555DR NE555DRE4 NE555DRG4 NE555P NE555PE4 NE555PSLE NE555PSR NE555PSRE4 NE555PW NE555PWE4 NE555PWR NE555PWRE4 NE555Y SA555D SA555DE4 SA555DG4 Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE SOIC SOIC SOIC D D D Package Type CDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO SO TSSOP TSSOP TSSOP TSSOP Package Drawing JG D D D D P P D D D D D D P P PS PS PS PW PW PW PW Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 8 8 8 75 75 75 1 75 75 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 SNPB CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 75 75 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS) TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 150 150 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com
31-Jul-2006
Orderable Device SA555DR SA555DRE4 SA555DRG4 SA555P SA555PE4 SE555D SE555DR SE555FKB SE555JG SE555JGB SE555N SE555P
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE
Package Type SOIC SOIC SOIC PDIP PDIP SOIC SOIC LCCC CDIP CDIP PDIP PDIP
Package Drawing D D D P P D D FK JG JG N P
Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 20 8 8 8 8 50 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 2500 1 1 1 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD TBD TBD TBD Pb-Free (RoHS)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 SNPB A42 SNPB Call TI CU NIPDAU
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-220C-UNLIM Level-1-220C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI N / A for Pkg Type
POST-PLATE N / A for Pkg Type
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Low Power Wireless www.ti.com/lpw

Features: NA555, NE555, SA555, SE555 Precision Timers

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Features: NA555, NE555, SA555, SE555 Precision Timers

Uploaded by

Copyright:

Available Formats

NA555, NE555, SA555, SE555 PRECISION TIMERS

GND TRIG OUT RESET

VCC DISCH THRES CONT

NA555, NE555, SA555, SE555 PRECISION TIMERS

Voltage levels shown are nominal.

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

FUNCTIONAL BLOCK DIAGRAM

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

Absolute Maximum Ratings (1)

Recommended Operating Conditions

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

CONT voltage (open circuit)

Low-level output voltage

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

VOL Low-Level Output Voltage V

LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT

IOL Low-Level Output Current mA

IOL Low-Level Output Current mA

LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT

DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT

TA = 55C ( VCC VOH) Voltage Drop V

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2

0.01 1 2 4 7 10 20 40 70 100 0 IOL Low-Level Output Current mA

2 4 7 10 20 40 70 100 IOH High-Level Output Current mA

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

TYPICAL CHARACTERISTICS (continued)

NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs SUPPLY VOLTAGE

0.985 0 5 10 15 20 VCC Supply Voltage V

NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs FREE-AIR TEMPERATURE

PROPAGATION DELAY TIME vs LOWEST VOLTAGE LEVEL OF TRIGGER PULSE

TA = 55C 200 TA = 0C 150

TA = 25C TA = 70C TA = 125C

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

APPLICATION INFORMATION Monostable Operation

5 CONT RESET DISCH

OUT THRES TRIG GND 1

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

tw Output Pulse Duration s

APPLICATION INFORMATION (continued)

Figure 10. Typical Monostable Waveforms

Figure 11. Output Pulse Duration vs Capacitance

RESET DISCH OUT THRES TRIG GND 1 3

Open (see Note A) 5

Capacitor Voltage Time 0.5 ms/div

Figure 12. Circuit for Astable Operation

Figure 13. Typical Astable Waveforms

Submit Documentation Feedback

NA555, NE555, SA555, SE555 PRECISION TIMERS

APPLICATION INFORMATION (continued)

Output waveform duty cycle t R H + 1 B + t )t R ) 2R H L A B t R B Low-to-high ratio + L + t R ) R H A B

Figure 14. Free-Running Frequency

DISCH 5 0.01 F CONT GND 1

Figure 15. Circuit for Missing-Pulse Detector