HBK Tp HCMKhoa TBMT Mn hc: K thut s GVPT: H Trung M Bi tp gii sn v VHDL (AY1112-S1) (Cc m VHDL c chy th trn Altera

a MaxplusII v10.2) 1. Vit m VHDL m s bit 1 ca s nh phn 3 bit A vi cc cch sau: a) Dng m hnh hnh vi b) Dng m hnh lung d liu c) Lnh case-when d) Dng m hnh cu trc Bi gii. Vi yu cu ca bi, ta c c bng chn tr sau: Ng vo A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Ng ra C1 C0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

Phn u dng th vin IEEE v khai bo entity th ging nhau cho cc cch: TD: Vi khai bo ca cch 1: library ieee; use ieee.std_logic_1164.all; entity ONES_CNT_EX1 is

port ( A : in std_logic_vector(2 downto 0); C : out std_logic_vector(1 downto 0)); end ONES_CNT_EX1; a) M hnh hnh vi: architecture Algorithmic of ONES_CNT_EX1 is begin Process(A) -- Sensitivity List Contains only Vector A Variable num: INTEGER range 0 to 3; begin num :=0; For i in 0 to 2
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Loop IF A(i) = '1' then num := num+1; end if; end Loop; ---Transfer "num" Variable Value to a SIGNAL C C C C <= <= <= <= "00"; "01"; "10"; "11";

CASE num is WHEN 0 => WHEN 1 => WHEN 2 => WHEN 3 => end CASE; end process; end Algorithmic; Dng sng m phng hot ng:

Ch : C cch gii khc trong th d ca MaxplusII: -- MAX+plus II VHDL Example -- Combinatorial Process Statement -- Copyright (c) 1994 Altera Corporation ENTITY proc IS PORT ( d : IN BIT_VECTOR (2 DOWNTO 0); q : OUT INTEGER RANGE 0 TO 3 ); END proc; ARCHITECTURE maxpld OF proc IS BEGIN -- count the number of bits with the value 1 in word d PROCESS (d) VARIABLE num_bits : INTEGER; BEGIN
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num_bits := 0; FOR i IN d'RANGE LOOP IF d(i) = '1' THEN num_bits := num_bits + 1; END IF; END LOOP; q <= num_bits; END PROCESS; END maxpld; b) M hnh lung d liu architecture Two_Level of begin ONES_CNT_EX2 is

C(1) <= (A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1)); C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and not A(1) and A(0)) or (A(2) and A(1) and A(0)) or (not A(2) and A(1) and not A(0)); end Two_Level; Dng sng m phng hot ng:

c) Lnh case-when Process(A) -- Sensitivity List Contains only Vector A begin CASE A is WHEN "000" => C <= "00"; WHEN "001" => C <= "01"; WHEN "010" => C <= "01"; WHEN "011" => C <= "10"; WHEN "100" => C <= "01"; WHEN "101" => C <= "10"; WHEN "110" => C <= "10";
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WHEN "111" => C <= "11"; WHEN OTHERS => C <="ZZ"; end CASE; end process; end Truth_Table; d) Dng m hnh cu trc C nhiu cch gii cho phn ny. T bng chn tr ta c biu thc Boole cho cc ng ra: C1 = A1A0 + A0A2 + A1A2 + A0A1A2 C1 = A1A0 + A0A2 + A1A2 => cn AND 2 ng vo v OR 3 ng vo v C0 = A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0 C0 = ((A2A1A0).( A2A1A0) .(A2A1A0).(A2A1A0)) => Cn NAND 3 ng vo, NAND 4 ng vo v cng NOT Mch cho C1 c t tn l MAJ3 v mch cho C0 c t tn l OPAR3. T c bi gii sau: ----------------- NOT gate ----------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY notgate IS PORT( i: IN STD_LOGIC; o: OUT STD_LOGIC); END notgate; ARCHITECTURE Dataflow OF notgate IS BEGIN o <= NOT i; END Dataflow; ----------------- 3-input NAND gate --------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3gate IS PORT( i1, i2, i3: IN STD_LOGIC; o: OUT STD_LOGIC); END nand3gate; ARCHITECTURE Dataflow OF nand3gate IS BEGIN o <= NOT(i1 AND i2 AND i3); END Dataflow; ----------------- 4-input NAND gate --------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand4gate IS
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PORT( i1, i2, i3, i4: IN STD_LOGIC; o: OUT STD_LOGIC); END nand4gate; ARCHITECTURE Dataflow OF nand4gate IS BEGIN o <= NOT(i1 AND i2 AND i3 AND i4); END Dataflow; ----------------- 2-input AND gate --------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and2gate IS PORT( i1, i2: IN STD_LOGIC; o: OUT STD_LOGIC); END and2gate; ARCHITECTURE Dataflow OF and2gate IS BEGIN o <= i1 AND i2; END Dataflow; ----------------- 3-input OR gate ---------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or3gate IS PORT( i1, i2, i3: IN STD_LOGIC; o: OUT STD_LOGIC); END or3gate; ARCHITECTURE Dataflow OF or3gate IS BEGIN o <= i1 OR i2 OR i3; END Dataflow; ----------------- Majority of 3 bit number---------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity MAJ3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end MAJ3; architecture Structural_M of MAJ3 is COMPONENT and2gate PORT( I1, I2: in STD_LOGIC; -- Declare Components O: out STD_LOGIC); -- To Be Instantiated
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END COMPONENT; COMPONENT or3gate PORT(I1, I2, I3: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; -SIGNAL A1, A2, A3: STD_LOGIC; -- Declare Maj3 Local Signals begin -- Instantiate Gates g1: and2gate PORT MAP (X(0), X(1), A1); g2: and2gate PORT MAP (X(0), X(2), A2); -- Wiring of g3: and2gate PORT MAP (X(1), X(2), A3); -- Maj3 g4: or3gate PORT MAP (A1, A2, A3, Z); -- Compts. end Structural_M; ------------------OPAR3 Circuit-----------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity OPAR3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end OPAR3; architecture Structural_O of OPAR3 is COMPONENT notgate PORT( i: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; COMPONENT nand3gate PORT( I1, I2, I3: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; COMPONENT nand4gate PORT( I1, I2, I3, I4: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; -SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: STD_LOGIC; begin -- Instantiate Gates g1: notgate PORT MAP (X(0), A0B); g2: notgate PORT MAP (X(1), A1B); g3: notgate PORT MAP (X(2), A2B); g4: nand3gate PORT MAP (X(2), A1B, A0B, Z1); g5: nand3gate PORT MAP (X(0), A1B, A2B, Z2); g6: nand3gate PORT MAP (X(0), X(1), X(2), Z3); g7: nand3gate PORT MAP (X(1), A2B, A0B, Z4);
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g8: nand4gate PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural_O; -----------------ONES_CNT_EX4: Main Circuit-----------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity ONES_CNT_EX4 is port ( A : in STD_LOGIC_VECTOR(2 downto 0); C : out STD_LOGIC_VECTOR(1 downto 0)); end ONES_CNT_EX4; architecture Structural of ONES_CNT_EX4 is COMPONENT MAJ3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; COMPONENT OPAR3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; -begin -- Instantiate Components -c1: MAJ3 PORT MAP (A, C(1)); c2: OPAR3 PORT MAP (A, C(0)); end Structural; Dng sng ra m phng:

Ch : Ta c th s dng lun cc component c sn ca Altera MaxplusII. Tuy nhin lu phi khai bo component ng vi khai bo ca Altera MaxplusII! Cc cng logic ca Maxplus II c cc khai bo sau: 1) Cng NOT vi tn l A_NOT c khai bo sau: COMPONENT a_not PORT( a_in: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT;
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2) Cng AND c th c n ng vo (ANDn) vi n=2, 3, 4, 6, 8 v 12. TD: Khai bo sau cho cng AND c 2 ng vo: COMPONENT and2 PORT( IN1, IN2: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; 3) Cng OR c th c n ng vo (ORn) vi n=2, 3, 4, 6, 8 v 12. TD: Khai bo sau cho cng OR c 2 ng vo: COMPONENT or3 PORT(IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; 4) Cng NAND c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12. 5) Cng NOR c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12. 6) Cng XOR 2 ng vo c tn l a_XOR vi khai bo sau: COMPONENT a_xor PORT(IN1, IN2: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; 7) Cng XNOR 2 ng vo c tn l a_XNOR Nh vy ta c li gii khc ngn hn nu s dng cc component c sn ca Maxplus II: ----- Use built-in components of MaxplusII ----------------- Majority of 3 bit number---------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity MAJ3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end MAJ3; architecture Structural_M of MAJ3 is COMPONENT and2 PORT( IN1, IN2: in STD_LOGIC; -- Declare Components a_out: out STD_LOGIC); -- To Be Instantiated END COMPONENT; COMPONENT or3 PORT(IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; -SIGNAL A1,A2,A3: STD_LOGIC; -- Declare Maj3 Local Signals begin -- Instantiate Gates g1: and2 PORT MAP (X(0), X(1), A1); g2: and2 PORT MAP (X(0), X(2), A2); -- Wiring of g3: and2 PORT MAP (X(1), X(2), A3); -- Maj3
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g4: or3 PORT MAP (A1, A2, A3, Z); -- Compts. end Structural_M; ------------------OPAR3 Circuit--------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity OPAR3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end OPAR3; architecture Structural_O of OPAR3 is COMPONENT a_not PORT( a_in: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; COMPONENT nand3 PORT( IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; COMPONENT nand4 PORT( IN1, IN2, IN3, IN4: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; -SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: STD_LOGIC; begin -- Instantiate Gates g1: a_not PORT MAP (X(0), A0B); g2: a_not PORT MAP (X(1), A1B); g3: a_not PORT MAP (X(2), A2B); g4: nand3 PORT MAP (X(2), A1B, A0B, Z1); g5: nand3 PORT MAP (X(0), A1B, A2B, Z2); g6: nand3 PORT MAP (X(0), X(1), X(2), Z3); g7: nand3 PORT MAP (X(1), A2B, A0B, Z4); g8: nand4 PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural_O; -----------------ONES_CNT_EX4: Main Circuit-----------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity ONES_CNT_EX4B is port ( A : in STD_LOGIC_VECTOR(2 downto 0); C : out STD_LOGIC_VECTOR(1 downto 0)); end ONES_CNT_EX4B; architecture Structural of ONES_CNT_EX4B is
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COMPONENT MAJ3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; COMPONENT OPAR3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; -begin -- Instantiate Components c1: MAJ3 PORT MAP (A, C(1)); c2: OPAR3 PORT MAP (A, C(0)); end Structural; 2. Vi mch t hp sau:

Hy vit m VHDL vi cc cch sau (khng thit k ring mch gii m, m ch ci t hm F): 1) Lnh ng thi vi php gn dng cc ton t logic 2) Lnh ng thi WHEN-ELSE 3) Lnh ng thi WITH-SELECT-WHEN 4) Lnh tun t IF-THEN-ELSE 5) Lnh tun t CASE-WHEN Bi gii. 1) Lnh ng thi vi php gn dng cc ton t logic --- signal assignment with logic operators library ieee; use ieee.std_logic_1164.all; entity Q02_1 is port ( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_1; architecture a of Q02_1 is signal D1, D5, D7: std_logic; begin D1 <= not(A) and not(B) and C;
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D5 <= A and not(B) and C; D7 <= A and B and C; F <= D1 or D5 or D7; end a;

2) Lnh ng thi WHEN-ELSE --- signal assignment with WHEN-ELSE library ieee; use ieee.std_logic_1164.all; entity Q02_2 is port( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_2; architecture a of Q02_2 is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A&B&C; F <= '1' when ABC="001" or ABC="101" or ABC ="111" else '0'; end a; 3) Lnh ng thi WITH-SELECT-WHEN --- signal assignment with WITH-SELECT-WHEN library ieee; use ieee.std_logic_1164.all; entity Q02_3 is port( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_3; architecture a of Q02_3 is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A&B&C; with ABC select F <= '1' when "001" | "101" | "111", '0' when others; end a;
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4) Lnh tun t IF-THEN-ELSE --- signal assignment with IF-THEN-ELSE library ieee; use ieee.std_logic_1164.all; entity Q02_4 is port( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_4; architecture a of Q02_4 is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A&B&C; process(ABC) begin if (ABC= "001" or ABC = "101" or ABC ="111") then F <= '1'; else F <= '0'; end if; end process; end a; 5) Lnh tun t CASE-WHEN --- signal assignment with CASE-WHEN library ieee; use ieee.std_logic_1164.all; entity Q02_5 is port( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_5; architecture a of Q02_5 is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A&B&C; process(ABC) begin case (ABC) is when "001" | "101" | "111" => F <= '1'; when others => F <= '0'; end case; end process; end a;

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3. Hy v mch logic tng ng (khng n gin ha hm Boole v c th s dng cc thnh phn t hp c bn nh cng logic, mux, decoder, FA, HA, ) ca m VHDL sau: library ieee; use ieee.std_logic_1164.all; entity blackbox is port( a, b, cin: in std_logic; inst: in std_logic_vector(2 downto 0); F, cout: out std_logic); end blackbox; architecture bg of blackbox is signal s0, s1, s2, s3, s4 : std_logic; --signal command : std_logic_vector(1 downto 0); begin s0 <= a and s4; s1 <= a or s4; s2 <= a xor s4; s3 <= a xor s4 xor cin; cout <= (a and s4) or ( s4 and cin) or (a and cin); U1: process(inst) begin case(inst(2 downto 1)) is when "00" => F <= s0; when "01" => F <= s1; when "10" => F <= s2; when others => F <= s3; end case; end process; U2: process(inst) begin if (inst(0) = '0') then s4 <= b; else s4 <= not b; end if; end process; end bg; Bi gii. Ta thy 2 php gn sau : s3 <= a xor s4 xor cin; cout <= (a and s4) or ( s4 and cin) or (a and cin); nhm thc hin mch FA, do c th dng khi ny trong mch logic. Process U1 chnh l MUX 4 sang 1 vi ng chn l inst(2:1). Process U2 chnh l MUX 2 sang 1 vi ng chn l inst(0). T ta c mch logic ca m VHDL trn l: (ALU 1 bit)
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4. Hy v mch logic tng ng (khng n gin ha hm Boole v c th s dng cc thnh phn t hp c bn nh cng logic, mux, decoder, FA, HA, ) ca m VHDL sau: library ieee; use ieee.std_logic_1164.all; entity CIRCUIT is port(A, B, C: in std_logic; S:in std_logic_vector (1 downto 0); Z: out std_logic); end CIRCUIT; architecture a of CIRCUIT is begin process(A, B, C, S) begin if (S(0)= 1) then Z <= A; elsif (S(1) = 1) then Z <= B; else Z <= C; end if; end process; end a;
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Bi gii. T m VHDL ta c th vit trc tip cc biu thc Boole cho cc bin ra vi loi lnh IF : Lnh Biu thc Boole tng ng F = C1.X + C1(C2.Y + C2.Z) if (cond1) then F = C1.X + C1C2.Y + C1 C2.Z F <= X ; elsif (cond2) then Vi C1 = cond1 v C2 = cond2 F <= Y ; else F <= Z ; end if ; p dng qui tc ny ta tm c biu thc Boole cho Z: Z = S(0).A + S(0)(S(1).B + S(1).C) Nh li vi MUX 2 sang 1c ng ra Y v cc ng vo I0, I1 v S th ng ra l: Y = S.I0 + S.I1 Nh vy ta phi dng 2 mch MUX 2 sang 1 thc hin mch trn:

5. Hy v mch logic tng ng (khng n gin ha hm Boole v c th s dng cc thnh phn t hp c bn nh cng logic, mux, decoder, FA, HA, ) ca m VHDL sau: entity CIRCUIT is port (A, B, S1, S2, S3, CLK: in std_logic; Y: out std_logic); end CIRCUIT; architecture a of CIRCUIT is begin process(CLK) begin if (CLK'event and CLK='1') then if (A='1') then Y <= S3; elsif (B = '0') then Y <= S2; else Y <= S1; end if; end if; end process; end a;
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Bi gii. NX : Ng ra ch c cp nht khi c cnh ln ti CLK y l D F/F kch cnh ln vi ng vo l mch t hp nh cu trn.

6. Ta cn thit k 1 mch t hp m xut pht t thit k s thng thng, mch ny c ghp t mch m ha u tin t 10 ng vo (in_n) sang 4 (BCD): ng vo tch cc thp v u tin bit c trng s thp nht, ng ra l s BCD 4 bit ch ng vo no c tch cc thp. o TD: Ng vo in_n = 11111100 th ng ra l BCD = 0000 Mch gii m BCD ra 7 on ni vi LED (gi s logic 1 lm cho on LED sng) : mch ny nhn gi tr ra t mch trn v chuyn sang m 7 on hin trn LED 7 on. a) Hy vit m VHDL vi 2 mch ny c lp. b) Hy vit m VHDL ch c 1 mch duy nht. Bi gii. Ta c th dng when-else hay with-select-when m t cc mch ny. a) M VHDL vi 2 mch c lp library ieee; use ieee.std_logic_1164.all; entity Q06_1 is port( in_n: in std_logic_vector(9 downto 0); -- in_n : low active and higher priority LSB LED_7seg: out std_logic_vector(6 downto 0)); -- LED_7seg(0) = segment a end Q06_1; architecture bg of Q06_1 is signal s_BCD : std_logic_vector (3 downto 0); begin -- Priority Encoder s_BCD <= "0000" when (in_n(0) = '0') else "0001" when in_n(1) = '0' else "0010" when in_n(2) = '0' else "0011" when in_n(3) = '0' else "0100" when in_n(4) = '0' else "0101" when in_n(5) = '0' else "0110" when in_n(6) = '0' else "0111" when in_n(7) = '0' else "1000" when in_n(8) = '0' else "1001" when in_n(9) = '0' else "1111"; -- invalid BCD
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-- BCD to 7 segment Decoder: LED_7seg = gfedcba LED_7seg <= "0111111" when s_BCD = "0000" else "0000110" when s_BCD = "0001" else "1011011" when s_BCD = "0010" else "1001111" when s_BCD = "0011" else "1100110" when s_BCD = "0100" else "1101101" when s_BCD = "0101" else "1111101" when s_BCD = "0110" else "0000111" when s_BCD = "0111" else "0000000" when s_BCD = "1000" else "1101111" when s_BCD = "1001" else (others => '0'); end bg; Dng sng m phng :

b) M VHDL vi 1 mch duy nht library ieee; use ieee.std_logic_1164.all; entity Q06_2 is port( in_n: in std_logic_vector(9 downto 0); LED_7seg: out std_logic_vector(6 downto 0)); end Q06_2; architecture bg of Q06_2 is begin LED_7seg <= "0111111" when in_n(0) = '0' else "0000110" when in_n(1) = '0' else "1011011" when in_n(2) = '0' else "1001111" when in_n(3) = '0' else "1100110" when in_n(4) = '0' else "1101101" when in_n(5) = '0' else "1111101" when in_n(6) = '0' else
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"0000111" when in_n(7) = '0' else "0000000" when in_n(8) = '0' else "1101111" when in_n(9) = '0' else (others => '0'); end bg; 7. Thit k JK flipfop nh hnh bn di (cc ng Preset PR v Clear CLR tch cc cao v bt ng b, CLR c u tin cao hn PR) a) Dng phng trnh c tnh ca JK FF. b) Dng bng hot ng ca JK FF. c) Nu mun Preset PR ng b th phi sa li nh th no? Bi gii. a) Dng phng trnh c tnh ca JK FF:
library ieee; use ieee.std_logic_1164.all; entity JK_FF is port( J, K, CLK, PR, CLR: in std_logic; -- PR, CLR: Asynchronous Preset and Clear Q, Q_n: out std_logic); end JK_FF; architecture bg of JK_FF is signal Q_int: std_logic; begin process(CLK, PR, CLR) begin if (CLR = '1') then Q_int <= '0'; elsif (PR = '1') then Q_int <= '1'; elsif rising_edge(CLK) then Q_int <= (J and not Q_int) or (not K and Q_int); end if; end process; Q <= Q_int; Q_n <= not Q_int; end bg;

Dng sng m phng:

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b) Dng bng hot ng ca JK FF: library ieee; use ieee.std_logic_1164.all; entity JK_FF is port( J, K, CLK, PR, CLR: in std_logic; Q, Q_n: out std_logic); end JK_FF; architecture bg of Q07_2 is signal Q_int: std_logic; signal JK: std_logic_vector(1 downto 0); begin JK <= J & K; process(CLK, PR, CLR) begin if (CLR = '1') then Q_int <= '0'; elsif (PR = '1') then Q_int <= '1'; elsif rising_edge(CLK) then case JK is when "01" => Q_int <= '0'; -- Reset when "10" => Q_int <= '1'; -- Set when "11" => Q_int <= not Q_int;-- Toggle when others => null; end case; end if; end process; Q <= Q_int; Q_n <= not Q_int; end bg; c) Ta ch cn vit li nh sau : if (CLR = '1') then Q_int <= '0'; elsif rising_edge(CLK) then if (PR = '1') then Q_int <= '1'; else --Phn m gn Q_int end if ; end if ;

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Dng sng m phng :

8. Thit k mch cng song song 2 s nh phn N bit (dng pht biu generic thit k tng qut, mc nhin N =4) l A v B. Tng l Sum v s nh/mn l C_out. a) M t VHDL cho mch ny. b) Thm vo tn hiu iu khin cho php cng/tr vi tn l Add_Sub (0: cng v 1:tr) th phi chnh sa nh th no? Bi gii. a) Khi s dng ton t cng/tr th ta phi dng gi ieee.std_logic_unsigned.all : -- Parallel Adder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Q08_1 is generic (N: integer := 4); port( A, B: in std_logic_vector(N-1 downto 0); C_out: out std_logic; Sum: out std_logic_vector(N-1 downto 0)); end Q08_1; architecture bg of Q08_1 is signal Sum_int: std_logic_vector(Num downto 0); begin Sum_int <= ('0' & A) + ('0' & B); Sum <= Sum_int(N-1 downto 0); C_out <= Sum_int(N); end bg; b) Thm tn hiu iu khin Add_Sub: Ta ch cn nh ngha thm Add_sub v vit li lnh gn ca Sum_int : Sum_int <= ('0' & A) + ('0' & B) when Add_sub = '0' else ('0' & A) - ('0' & B); Dng sng m phng :

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9. Thit k mch cng ni tip 2 s nh phn vi A v B c chiu di l Num_bits bit (mc nhin cho Num_bits = 4). D liu vo c nhp ni tip vi LSB i trc. Kt qu l tng Sum c chiu di Num_bits bit v c s nh ra l C_out. Tn hiu Start =1 ch bt u thc hin cng (ch tn ti < 1 chu k xung nhp). C tn hiu Finished bo hon tt php cng. Mch hot ng theo cnh xung xung nhp CLK. Hy vit m VHDL cho mch ny. Bi gii.
library ieee; use ieee.std_logic_1164.all; entity Q09_1 is generic (Num_bits: integer := 4); port( A, B, Start, CLK: in std_logic; C_out, Finished: out std_logic; Sum: out std_logic_vector(Num_bits-1 downto 0)); end Q09_1; architecture bg of Q09_1 is begin process(CLK, Start) variable FIN: std_logic; -- Internal Finish signal variable N: integer range 0 to Num_bits; variable S, C_in: std_logic; variable Sum_int: std_logic_vector(Num_bits-1 downto 0); begin if (Start = '1') then FIN := '0'; N := Num_bits; C_in := '0'; Finished <= '0'; elsif (CLK'event and CLK = '0') then -- and FIN = '0') if (FIN = '0') then S := A xor B xor C_in; C_in := (A and B) or ( B and C_in) or ( A and C_in); Sum_int:= S & Sum_int(Num_bits-1 downto 1); N := N - 1;
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end if; end process; end bg;

if N = 0 then FIN := '1'; Finished <= '1'; Sum <= Sum_int; C_out <= C_in; end if; end if;

Dng sng m phng : Vi A = 0110 v B = 1011 => A + B = 10001 => C_out = 1 v Sum = 0001

Ch : C 1 cch gii khc l tn dng ton t + (trong ieee.std_logic_unsigned.all) tm C v S :

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; . . . -- Thay dng: variable S, C_in: std_logic; bng dng sau: variable CS: std_logic_vector(1 downto 0); -- Carry v Sum . . . -- M mi phn tnh full adder nh sau: if (FIN = '0') then CS := ('0' & CS(1)) + ('0' & A) + ('0' & B) ; Sum_int := CS(0) & Sum_int(Num_bits-1 downto 1); N := N - 1; if N = 0 then FIN := '1'; Finished <= '1'; Sum <= Sum_int; C_out <= CS(1); end if; end if;
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10. Cho trc h tun t ng b sau:

a) Lp bng chuyn trng thi ca mch trn. b) Vit m VHDL cho cu a) c thm tn hiu reset_n tch cc thp cho chy t trng thi Q1Q2=00. Bi gii. a) T s mch ta c th tm c cc phng trnh c tnh cho cc FF v ng ra Z : D1 = Q1+ = Q1 + Q2 ; D2 = Q2+ = XQ2 ; Z = Q1 + Q2 Suy ra bng chuyn trng thi sau: PS NS (Q1+Q2+) Z Q1Q2 X=0 X =1 00 10 01 1 01 10 10 0 11 00 10 1 10 00 01 1 b) M VHDL cho cu a): library ieee; use ieee.std_logic_1164.all; entity Q10_1 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q10_1; architecture bg of Q10_1 is signal state: std_logic_vector( 1 downto 0); signal state_X: std_logic_vector( 2 downto 0); begin state_X <= state & X; Z <= '0' when state = "01" else '1'; process(CLK, reset_n) begin if (reset_n = '0') then state <= "00"; elsif rising_edge(CLK) then case state_X is when "000" => state <= "10"; when "001" => state <= "01";
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when "010" | "011" => when "110" => state <= when "111" => state <= when "100" => state <= when "101" => state <= when others => null; end case; end if; end process; end bg; Dng sng m phng:

state <= "10"; "00"; "10"; "00"; "01";

Ch : C nhiu cch vit khc m t FSM, th d sau y l 1 cch vit khc: library ieee; use ieee.std_logic_1164.all; entity Q10_2 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q10_2; architecture bg of Q10_2 is signal Present_state: std_logic_vector( 1 downto 0); PS signal Next_state: std_logic_vector( 1 downto 0); NS begin Z <= '0' when Present_state = "01" else '1'; State_transition: process(CLK, reset_n) begin if (reset_n = '0') then Present_state <= "00"; elsif rising_edge(CLK) then Present_state <= Next_state ; end if; end process;
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---

Find_Next_state: process(Present_state) begin case Present_state is when "00" => if else when when

X = '0' then Next_state <= "10";

when

when end case; end process; end bg;

Next_state <= "01"; end if; "01" => Next_state <= "10"; "11" => if X = '0' then Next_state <= "00"; else Next_state <= "10"; end if; "10" => if X = '0' then Next_state <= "00"; else Next_state <= "01"; end if; others => null;

Dng sng m phng:

11. Thit k mch pht hin chui bit vo ni tip c tr l "101". Vit m VHDL vi: a) Dng FSM loi Mealy vi m t FSM. b) FSM loi Mealy dng thanh ghi dch cha 3 bit lin tip v so snh vi "101". Bi gii. a) FSM loi Mealy Ta c c gin trng thi v bng chuyn trng thi nh sau (kt qu ly t bi ging thit k h tun t ng b)

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Ta nh ngha thm kiu mi cho cc trng thi khng cn gn trng thi m CAD s t gn tr cho n. library ieee; use ieee.std_logic_1164.all; entity Q11_1 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q11_1; architecture bg of Q11_1 is type state_type is (S0, S1, S2); signal state: state_type; begin Z <= '1' when (state = S2 and X = '1') else '0'; process(CLK, reset_n) begin if (reset_n = '0') then state <= S0; elsif rising_edge(CLK) then case state is when S0 => if X = '1' then state <= S1; end if; when S1 => if X = '0' then state <= S2; end if; when S2 => if X = '0' then state <= S0; else state <= S1; end if; when others => null; end case; end if; end process; end bg;

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b) Thanh ghi dch library ieee; use ieee.std_logic_1164.all; entity Q11_2 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q11_2; architecture bg of Q11_2 is signal pattern: std_logic_vector(2 downto 0); begin Z <= '1' when (pattern = "101" and X = 1) else '0'; process(CLK, reset_n) begin if (reset_n = '0') then pattern <= (others => '0') ; elsif rising_edge(CLK) then pattern <= pattern(1 downto 0) & X; end if; end process; end bg;

12. Thit k mch gii m 3 sang 8 v mch m ha u tin 8 sang 3 (u tin ng vo c trng s thp nht khi c nhiu bit vo l 1). Mch gii m c cc ng vo l C, B, v A (LSB) v ra l Y. Mch m ha c ng vo 8 bit D_in v ng ra 3 bit D_out. Bi gii.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- Dung cho ham conv_std_logic_vector(integer, number of bits) use ieee.std_logic_unsigned.all; -- Dung cho ham conv_integer(std_logic_vector) entity Q12_1 is port( C, B, A: in std_logic; -- A: LSB Y: out std_logic_vector(0 to 7); D_in: in std_logic_vector(0 to 7); D_out: out std_logic_vector(0 to 2)); end Q12_1; Cc BT gii sn v VHDL 2011 trang 27

architecture bg of Q12_1 is signal CBA: std_logic_vector(0 to 2); signal CBA_int: integer range 0 to 7; begin -- Decoder 3 to 8 CBA <= C & B & A; CBA_int <= conv_integer(CBA); process (CBA_int) variable Y_int: std_logic_vector(0 to 7); begin Y_int := (others => '0'); Y_int(CBA_int) := '1'; Y <= Y_int; end process; --- Priority Encoder 8 to 3 process(D_in) variable index_in: integer; begin for i in D_in'length -1 downto 0 loop if D_in(i) = '1' then index_in := i; end if; end loop; D_out <= conv_std_logic_vector(index_in,3); end process; end bg;

Dng sng m phng ca mch gii m:

Dng sng m phng ca mch m ha:

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13. Thit k b m ln 3 bit loi ni tip (cn gi l b m gn hay bt ng b) vi xung nhp vo CLK (kch cnh). Mch c ng reset tch cc thp reset_n. Hy vit m VHDL vi a) M hnh cu trc vi component DFF c sn. b) Cc lnh tun t. Bi gii. a) Dng component DFF c sn ca Maxplus II library ieee; use ieee.std_logic_1164.all; entity Q13_1 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q13_1; architecture bg of Q13_1 is COMPONENT DFF PORT (d : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC ); END COMPONENT; -Inputs | Output --prn clrn CLK D | Q -- L H X X | H -- H L X X | L -- L L X X | Illegal -- H H L | L -- H H H | H -- H H L X | Qo* -- H H H X | Qo -- * Qo = level of Q before Clock pulse -- All flipflops are positive-edge-triggered. signal D0, D1, D2, prn: std_logic; signal Q2_int, Q1_int, Q0_int: std_logic; begin U1: DFF port map(D0, CLK, reset_n, prn, Q0_int); U2: DFF port map(D1, D0, reset_n, prn, Q1_int); U3: DFF port map(D2, D1, reset_n, prn, Q2_int); prn <= '1'; D0 <= not Q0_int; D1 <= not Q1_int; D2 <= not Q2_int; Q0 <= Q0_int; Q1 <= Q1_int; Q2 <= Q2_int; end bg;
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c) Cc lnh tun t: library ieee; use ieee.std_logic_1164.all; entity Q13_2 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q13_2; architecture bg of Q13_2 is signal Q2_int, Q1_int, Q0_int: std_logic; begin process(CLK, reset_n) begin if reset_n = '0' then Q0_int <= '0'; elsif rising_edge(CLK) then Q0_int <= not Q0_int; end if; end process; process(Q0_int) begin if reset_n = '0' then Q1_int <= '0'; elsif falling_edge(Q0_int) then Q1_int <= not Q1_int; end if; end process; process(Q1_int) begin if reset_n = '0' then Q2_int <= '0'; elsif falling_edge(Q1_int) then Q2_int <= not Q2_int; end if; end process; Q0 <= Q0_int; Q1 <= Q1_int; Q2 <= Q2_int; end bg;
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Ch : Ta c th khai bo buffer cho cc i tng ra Q2, Q1, v Q0, khi khng cn dng cc tn hiu Q2_int, Q1_int, Q0_int. 14. Thit k b m ln 3 bit loi song song (cn gi l b m ng b) vi xung nhp vo CLK (kch cnh). Mch c ng reset tch cc thp reset_n. Hy vit m VHDL vi a) M hnh cu trc vi component JKFF c sn. b) Cc lnh tun t. c) Vi dy m 1, 3, 5, 7, 1, . . Bi gii. a) M hnh cu trc vi component JKFF c sn: library ieee; use ieee.std_logic_1164.all; entity Q14_1 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: buffer std_logic); -- Q0: LSB end Q14_1; architecture bg of Q14_1 is COMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; -Inputs | Output -- PRN CLRN CLK J K | Q -- L H X X X | H -- H L X X X | L -- L L X X X | Illegal -- H H L X X | Qo* -- H H L L | Qo* -- H H H L | H -- H H L H | L -- H H H H | Toggle -- * Qo = level of Q before Clock pulse -- All flipflops are positive-edge-triggered. signal J0, J1, J2, prn: std_logic; begin U1: JKFF port map(J0, J0, CLK, reset_n, prn, Q0); U2: JKFF port map(J1, J1, CLK, reset_n, prn, Q1); U3: JKFF port map(J2, J2, CLK, reset_n, prn, Q2); prn <= '1'; J0 <= '1'; J1 <= Q0; J2 <= Q1 and Q0; end bg;
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b) Cc lnh tun t: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- De tinh cong so nhi phan voi so nguyen entity Q14_2 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q14_2; architecture bg of Q14_2 is signal Q: std_logic_vector(2 downto 0); begin process(CLK) begin if reset_n ='0' then Q <= "000"; elsif rising_edge(CLK) then Q <= Q + 1; end if; end process; Q2 <= Q(2); Q1 <= Q(1); Q0 <= Q(0); end bg; c) Vi dy m 1, 3, 5, 7, 1, . . Ch cn sa li trong phn process ca b) nh sau: if reset_n ='0' then Q <= "001"; elsif rising_edge(CLK) then if Q = "111" then Q <= "001"; else Q <= Q + 2; end if; end if;

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