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    Experiment 1: Object

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    Shalini Sharma
    The document describes an experiment using Verilog HDL to verify the functionality of various logic gates. It defines an AND, OR, NOT, NAND, NOR, XOR and XNOR gate in a Verilog module. The module is then simulated using Xilinx ISE 8.2i software to generate waveform outputs verifying the operation of each gate. The experiment demonstrated successful design and verification of the logic gates in Verilog HDL.

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    Experiment 1: Object

    Uploaded by

    Shalini Sharma
    17 views4 pages
    The document describes an experiment using Verilog HDL to verify the functionality of various logic gates. It defines an AND, OR, NOT, NAND, NOR, XOR and XNOR gate in a Verilog module. The module is then simulated using Xilinx ISE 8.2i software to generate waveform outputs verifying the operation of each gate. The experiment demonstrated successful design and verification of the logic gates in Verilog HDL.

    Original Description:

    verilog

    Original Title

    Experiment 1

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    The document describes an experiment using Verilog HDL to verify the functionality of various logic gates. It defines an AND, OR, NOT, NAND, NOR, XOR and XNOR gate in a Verilog module. The module is then simulated using Xilinx ISE 8.2i software to generate waveform outputs verifying the operation of each gate. The experiment demonstrated successful design and verification of the logic gates in Verilog HDL.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    17 views4 pages

    Experiment 1: Object

    Uploaded by

    Shalini Sharma
    The document describes an experiment using Verilog HDL to verify the functionality of various logic gates. It defines an AND, OR, NOT, NAND, NOR, XOR and XNOR gate in a Verilog module. The module is then simulated using Xilinx ISE 8.2i software to generate waveform outputs verifying the operation of each gate. The experiment demonstrated successful design and verification of the logic gates in Verilog HDL.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as doc, pdf, or txt
    of 4

    Experiment 1

    Object: Using Verilog HDL, verify the working of the following gates:i.

    AND Gate

    ii.

    OR Gate

    iii.

    NOT Gate

    iv.

    XOR Gate

    v.

    NAND Gate

    vi.

    NOR Gate

    vii.

    EX-NOR Gate

    Software Used:

    XILINX ISE 8.2i

    Theory:

    Verilog Code :module a(input_1, input_2, and_out, or_out, not_out, nand_out, nor_out, xor_out, xnor_out);
    input input_1;
    input input_2;
    output and_out;
    output or_out;
    output not_out;
    output nand_out;
    output nor_out;
    output xor_out;
    output xnor_out;
    not(not_out,input_1);
    and(and_out,input_1,input_2);
    or(or_out,input_1,input_2);
    nand(nand_out,input_1,input_2);
    xor(xor_out,input_1,input_2);
    nor(nor_out,input_1,input_2);
    xnor(xnor_out,input_1,input_2);
    endmodule

    RTL Schematic:2

    Simulation Waveforms:-

    Conclusion: All the gates were designed using Verilog HDL and verified using ISE
    Simulator.

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