DESIGN AND IMPLEMENTATION OF RADAR SIMULATOR

ABSTRACT:
Radar simulator is an embedded application developed to generate digitized pulse data replicating radar pulses which aids in development and testing of ESM Processor subsystem.ESM Processor is a vital part of an ESM system responsible for de-interleaving and identification of radar signals. An ESM (Electronic Support Measure) System is designed to intercept, locate and identify the radars operating in the environment. The System consists of antenna array , front end receiver ,ESM Processor and display. Antenna Array & front end receiver intercepts and measures the pulse by pulse parameters of the radars operating in the environment. The measured pulse parameters are digitized and organized as PDWs. The pulse by Pulse data is forwarded to ESM Processor which de-interleaves and applies emitter processing algorithms to form radar track. Finally, the emitter is identified and information is presented to the operator on display. The ESM Processor is driven by digitized pulse data called Pulse Descriptor Words (PDWs).To facilitate testing of ESM Processor in development phase, simulated PDW data in real time is a mandatory requirement. The RADAR Simulator is developed to generate PDWs which can be used as a test input for the ESM Processor in standalone mode for the development and testing of algorithms. The RADAR Simulator is to be designed as an embedded hardware module targeted to a FPGA capable of generating 10 emitters. It accepts configurable radar parameters namely (a) frequency (b) direction of arrival (DOA) (c)pulse width (d) amplitude (e)pulse repetition interval for each radar and generates PDWs as per specified parameters. Design and development of RADAR simulator involves design of PDW generation logic in verilog, testing in simulation for functionality and timing. The developed logic is to be ported on Virtex-5 FX70T based ML507 development platform using Xilinx ISE Design Suite Vivado Design Suite.