EXPERIMENT #1 XILINX FPGA TOOLS

Goals: To introduce the modeling, simulation and implementation of digital circuits

using Xilinx's FPGA ISE design tools.

References:

ithin the ISE there are se!eral tutorials that are a!aila"le. In particular, the ISE #uic$ Start descri"es ho% to create a file using either &'() or &E*I)+G. The ISE also offers an extensi!e set of manuals under the 'elp menu. In addition to the electronic !ersion of the manual and the #uic$ Sort Tutorial, Xilinx offers man, tutorials that are a!aila"le on the %e" site at %%%.xilinx.com.

Equip en!: The Xilinx ISE field programma"le gate arra,s FPGA de!elopment tools
are a!aila"le in la"orator,. These tools can also "e do%nloaded from Xilinx's %e" site at %%%.xilinx.com. The ISE E--ASE de!elopment tools that %e %ill use for the la"orator, experiments are located under the support do%nload section at %%%.xilinx.com.support.do%nload. The ISE E-PA/0 soft%are is a!aila"le for %indo%s XP, Solaris and )inix. Please ta$e note that the file do%nload si1e exceeds 2 G- and also during the installation process updates ma, ha!e to "e installed. It can ta$e ,ou up to a fe% hours to do%nload and install the ISE on a user computer. The user does not need to ha!e the -AS3S de!elopment "oard interface to the computer to design and simulate an FPGA. Finall,, a cop, of EXP+*T from (igilent Inc. 4%%%.digilentinc.com5 %ill "e used to do%nload an FPGA design to the FPGA configuration *+6 located on the -AS3S de!elopment "oard. This *+6 is read at po%er up ", the FPGA to configure the de!ice.

Pre"la#ora!or$: *ead this experiment carefull, to "ecome familiar %ith the

procedural steps in this experiment.

%iscussion: Xilinx's ISE is an FPGA design, simulation and implementation tool set
that allo%s the designer the a"ilit, to de!elop digital s,stems using either schematic capture or '() using &E*I)+G or &'(). These digital s,stems are then !erified using simulation tools that are part of the de!elopment s,stem. +nce the simulation outputs meet the design re7uirements, implementation is simpl, assigning the inputs and outputs to the appropriate pins on the FPGA. Appendix ( gi!es the pin configuration for the -AS3S "oard ", (igilent Inc. 4%%%.digilentinc.com5 relating the )E( and s%itch connections to the FPGA pin assignments. Experiment 82 is di!ided into four sections. Part 2 of this experiment %ill guide the student through the steps re7uired to create an FPGA using the schematic

29 2

capture part of the ISE and the steps re7uired to s,nthesi1e this design. :ext, the steps re7uired to simulate this design are gi!en along %ith the steps re7uired to implement the design in the FPGA on the -AS3S "oard. Part ; %ill expand on part 2 for additional logic gates 4:A:(, +*, EX+*, :+T5. In part < of this experiment, the design implemented in Parts 2 and ; %ill "e implemented using the &E*I)+G design language. The steps re7uired to create a &E*I)+G pro=ect %ill "e gi!en along %ith the steps re7uired to simulate and implement this design. In part >, a t%o9input fi!e9output logic s,stem %ill "e designed and implemented.

Par! 1& In!ro'uc!ion !o !(e XILINX ISE

In this part, ,ou %ill use Xilinx's ISE to design, simulate and implement a simple ; input A:( gate digital circuit. +nce completed, this ; input A:( gate implementation %ill "e do%nloaded to the -AS3S "oard and then tested using the on "oard )E('s and s%itches. 2. (ou"le clic$ on the ISE icon to open up the de!elopment tools as sho%n "elo%. There are fi!e general areas that %ill "e of interest. At the top are the tool "ars for file input and output, for running of the !arious tools, and s,m"ol inputs for the schematic capture. To the left are Sources )in'o) and the Processes )in'o) and at the "ottom is the 'ispla$ )in'o). The user %or$ area is located to the right.

;. :o% that the ISE is open, the next step is to open a pro=ect. ?nder the file menu select Ne) Pro*ec!. Enter the pro=ect name and lea!e the default

29 ;

location as /@AAXilinxB;IA. :ext select the Top"Le+el Source T$pe as sc(e a!ic. )ater in this experiment the &E*I)+G language t,pe %ill "e selected. hen all of the inputs ha!e "een entered the user should clic$ the next "utton. This %ill lead to the configuration menu as sho%n "elo%. The important items on this menu are the FPGA t,pe and the Preferred )anguage t,pe. Select the Preferre' lan,ua,e !$pe !o -ERILOG and the FPGA fa il$ !o Spar!an.e, 'e+ice !o X/.S100E, pac1a,e !$pe !o T2133 and Spee' !o ei!(er "3 or "4. The FPGA on the -AS3S "oard is the Spartan<E X/S2CCE in a T#2>> 42>> pins5 pac$age. Select the next "utton %hen finished.

<. In the process of creating a ne% pro=ect, the user must also create a ne) source file. There are t%o %a,s of doing this. The first is to create a ne% source file %ithin the next menu or from the Pro=ect 6enu, :e% Source item. Selecting the :e% Source "utton "rings up another dialog "ox. In this "ox, select Sc(e a!ic as the top9le!el t,pe and select a file na e 4eg. )a"25. Finall, clic$ the next "utton.

29 <

>. /lic$ the finish "utton. A dialog "ox %ill come up and state that the schematic file does not exist and should one "e created. /lic$ the 3es "utton. The last dialog "ox %ill indicate that the file D.sch has "een created and is of t,pe Schematic. /lic$ the :ext "utton to continue. The Add Source dialog "ox %ill no% appear. This dialog "ox allo%s the user to add an existing source to the pro=ect. For Experiment 82, clic$ the :ext "utton.

E. A pro=ect summar, dialog "ox appears, clic$ the Finish "utton. The ISE %ill no% create the pro=ect as sho%n "elo%. The Sources )in'o) sho%s the name of the pro=ect and the name of the top9le!el source as D.sch %ith a < "ox9icon to the left of the filename. The %esi,n Su ar$ )in'o) gi!es a summar, of the pro=ect and the Processes )in'o) lists all of the processes that are a!aila"le to this pro=ect. The Processes %indo% is an important %indo%. It is this %indo% that %ill allo% the user to simulate and implement an FPGA pro=ect.

29 >

F. (ou"le clic$ on the la#1 5la#1&sc(6 item in the Sources %indo%. The )a" 2 schematic %ill appear on the right hand side. At an, time an, of the %indo%s can "e floated as separate %indo%s ", selecting the indo% menu and selecting float menu item.

G. The follo%ing figure sho%s the menu items that are of importance %hen creating a schematic. Going from left to right, the arro% is the selec! tool, the next set of tools are the a'' )ire tool, a'' a ne! na e tool, rena e

29 E

selec!e' #us tool, a'' a #us !ap tool, a'' an I7O s$ #ol tool and an Ins!ance Na e tool.

ar1er tool, a'' a

H. /lic$ the A%% a S$ #ol tool. The Sources %indo% %ill change to the S,m"ol %indo% and the Processes %indo% %ill change to the option %indo%. There are t%o parts to this %indo% one for the categor, and the other the s,m"ols for that categor,. Select the lo,ic ca!e,or$ and select an'8 s$ #ol. A I"I in the s,m"ol name indicates an in!erter is located on an input pin. For example and>"2 is a > inputs and gate %ith one of the inputs connected to an in!erter. And; is a s,m"ol for a t%o9input and gate. At an,time selecting a s,m"ol and clic$ing the S,m"ol Info "utton an 'T6) file %ill appear descri"ing the s,m"ol selected. :o% mo!e the mouse o!er to the schematic %indo%. The s,m"ol %ill appear next to the mouse as the mouse is mo!ed across the schematic. Select the desired location and clic$ the mouse. This places the s,m"ol in the schematic. 'it the ES/ $e, on the $e,"oard to cancel an, further s,m"ol additions to the schematic.

B. In the tool"ars there are t%o magnif,ing glasses one for 1oom in 4J5 and one for 1oom out 495. ?se the 9oo in e$e,lass to 1oom into the schematic so the s,m"ol is easil, !isi"le. 2C. Adding %ires@ select the A'' :ires tool and clic$ one of the inputs 4four "oxes appear %hen the mouse is on the input to the A:( gate5 to the A:( gate and drag the %ire to the left and then dou"le clic$ the mouse. +ne clic$ allo%s the user to change direction for the %ire ", appl,ing a tie point on

29 F

the schematic. To end a %ire input dou"le clic$ of the mouse is re7uired. Add a %ire to "oth inputs and the output of the A:( gate. 22. :ext, I.+ mar$ers must "e added to the schematic. I.+ mar$ers ena"le inputs and outputs to "e tied to ph,sical pins on the FPGA. Select the A'' I7O ar1er tool. 6o!e the mouse to the %ire ends 4selected %hen four "oxes appear5 and clic$ the mouse. This %ill appl, an I.+ mar$er for that input.output. *epeat this for "oth the inputs and the output of the A:( gate. 2;. The ISE gi!es default names to the I.+ mar$ers. -, highlighting the I.+ mar$er and right clic$ing the mouse and selecting o#*ec! proper!ies allo%s the user to change the name. *ename the t%o inputs to IAI and I;I and the output to KOL. (o not use I+utI as an I.+ mar$er name as it is a reser!e %ord. The figure "elo% sho%s the final schematic. ?nder the File enu select the sa+e op!ion to sa!e this schematic.

2<. :o% that the schematic is finished, it must "e s,nthesi1ed. In the Processes )in'o) select the processes !a# and in the Sources )in'o) select the source !a# as sho%n "elo%. -efore an, schematic can "e s,nthesi1ed, the schematic must "e sa!ed as sho%n in Step 2;.

2>. The process %indo% lists the processes that are a!aila"le for this pro=ect. 'ighlight the top9le!el 4indicated ", three cu"es5 schematic Ila"2 29 G

4la"2.sch5L in the Sources %indo%. To s,nthesi1e this pro=ect =ust dou"le clic$ on the S$n!(esi9e " XST item in the Process %indo%. A "lue <( cu"e %ill start spinning and the message %indo% at the "ottom %ill start displa,ing messages. If there are errors in the s,nthesis, a red circle %ith an X %ill appear. -, clic$ing on the Error ta" in the message %indo% at the "ottom of the screen, the user can !ie% the error. )i$e%ise, if there are %arnings present, the user can !ie% the %arning ", clic$ing the %arning ta". If the ISE %as a"le s,nthesi1e the schematic, a ,reen c(ec1 %ill appear in front of the S,nthesi1e9XST process. :ext, the pro=ect must implemented. (ou"le clic$ the I ple en! %esi,n process. If the ISE is a"le to implement the design, a green chec$ "ox %ill appear in front of the Implement (esign process. If a %arning icon appears, ignore them at this point and continue on %ith the rest of the steps of this experiment. 2E. At this point the user can simulate the design. An input test "ench must "e created that defines the inputs and outputs to "e used in the simulation process. ?nder pro*ec! enu select ne) sources item. /hoose !es! #enc( )a+efor source t,pe and select a name for the test "ench. The name must "e different than the pro=ect name. :ote@ an,time the num"er of inputs or outputs change, the user should create a ne% test "ench file and the old one remo!ed from the pro=ect. The ISE has difficult, updating the test "ench file to reflect these changes. Select the next "utton t%ice and finall, the finish "utton. The follo%ing dialog "ox appears as sho%n "elo%. This "ox allo%s the user to select either a cloc$ input or com"inatorial input as inputs to the schematic. If the user selects one of the inputs as a cloc$ input, then the user can select !arious timing parameters associated %ith this cloc$. For this experiment, the inputs are simpl, com"inatorial inputs. The user should

choose the co #ina!orial 5or in!ernal cloc16 option and clic$ the finish "utton. 29 H

2F. The test "ench %indo% is no% displa,ed sho%ing "oth the inputs and the output for the t%o9input A:( gate circuit. -, mo!ing o!er the input %a!eforms and clic$ing the mouse the user can change the inputs from a 1ero to a one and "ac$ to 1ero. Also, if the user right clic$s on the mouse and selects set end of test "ench, the total time used for the test "ench can "e changed. The default time is 2CCC nano9seconds. For this part of the experiment, the user should define the inputs@ A<0= ;<0, then A<1= ;<0, then A<0= ;<1, and finall, A<1= ;<1 as sho%n "elo%. The "lue mar$er can "e mo!ed from right to left and the !alue on the inputs 4M2N or MCN5 can "e seen next the input name. hen finished, this test "ench should "e sa!ed using the File"Sa+e option. The user should no% close the test "ench %indo%.

2G. To simulate this pro=ect, the user needs to select in the Sources )in'o) in the top drop "ox selection area the ;e(a+ioral Si ula!ion option. The default selection is the S,nthesis. Implementation option. 'ighlight the test "ench file 4D.t"%5 listed in the Sources %indo%. :ext, in the Processes %indo% clic$ the plus s,m"ol next to the Xilinx ISE Simulator Process. The Si ula!e ;e(a+ioral Mo'el %ill "e displa,ed. (ou"le clic$ on this item to start the simulation.

29 B

2H. If there are no errors, the simulation %indo% appears sho%ing the inputs as defined ", the test "ench file and the appropriate output4s5 as sho%n "elo%. The magnif,ing glasses can "e used to 1oom in or out. The enlarged !ie% of the simulation %indo% %as o"tained ", closing the Processes and Sources %indo%s. These %indo%s can "e reopened using the &ie% menu and ", selecting these %indo%s. T(e user s(oul' c(ec1 !(e ou!pu! an' +erif$ !(a! !(is ou!pu! follo)s !(e !ru!( !a#le for a !)o"inpu! AN% ,a!e& In this %indo%, ma$e sure that the simulation time starts at MCN ns, else mo!e the scroll "ar to the right and "ac$ to the left. Re e #er !o sa+e a screen s(o! of !(is )in'o) for $our repor!& hen the user is finished %ith the simulation %indo%, the user can close it under the File menu 9 /lose item option.

2B. The last step is to assign the I.+ pins in the schematic to the ph,sical pins on the FPGA and to generate the FPGA programming file. In the Sources )in'o) select the S$n!(esis7 I ple en!a!ion option. :ext, clic$ on the plus s,m"ol on the user cons!rain!s i!e in the Processes )in'o). (ou"le clic$ on /rea!e Area /ons!rain!s Item. A dialog "ox appears as$ing the user to create D.?/F file. /lic$ on the 3es "utton. If this dialog "ox does not appear, rerun the s,nthesi1e XST and (esign again. The PA/E pro,ra %ill open as sho%n "elo%. Select the pac1a,e +ie) ta" at the "ottom. The input and output mar$ers 4"lue "ox5 from the schematic are listed in the %esi,n O#*ec! Lis! :in'o) on the left. T(e user s(oul' si pl$ 'ra, !(e #lue #o> ne>! !o !(e inpu!7ou!pu! !o !(e 'esire' pin& From Appendix (, S:0 is loca!e' on pin .?, S:1 is loca!e' on pin .@ and LE%0 is loca!e' on pin 14. :ote the pac$age pin num"er and t,pe ", mo!ing the mouse o!er the pins. +nce ,ou ha!e identified a pin num"er, mo!e the "lue "ox from the (esign +"=ect )ist indo% to the pin. Select 292C

pins for A 4pin <H5, - 4pin <F5, and C 4pin 2E5. Sa!e this configuration file using the File"Sa+e option. The Pace program can no% "e closed.

;C. The I ple en! %esi,n %ill ha!e to "e rerun. This is indicated ", a 7uestion mar$ next to this process in the Processes %indo%. (ou"le clic$ on the Implement (esign option. 6a$e sure ,ou ha!e a green chec$ mar$ in front of the Implement (esign. Finall,, dou"le clic$ on the Genera!e Pro,ra in, File. This generates the D.-IT program needed to program the FPGA. A Xilinx E-Tal$ %indo% %ill open. /lose this %indo%. The programming file for the FPGA %ill no% "e located in the pro=ect folder. ;2. :o% open the EXPORT pro,ra 4loo$ for a short cut on the des$top or indo%s Start O All Programs O (igilent O Adept O ExPort5. This program %ill "e used to do%nload the D.-IT file to the -AS3S "oard. Ma1e sure !(a! !(e ;ASAS #oar' is plu,,e' in!o !(e 'es1!op co pu!er +ia an BS; por!& +nce EXP+*T is running, select the Ini!iali9e /(ain "utton. T%o de!ices appear. The first one is for the FPGA and the second one is for the FPGA configuration *+6. ?sing the ;ro)se #u!!on select the C&;IT file in the pro=ect director, for "oth de!ices. The default location of this file is /@.XI)I:XB;I.pro=ect name.D."it. A dialog "ox %ill appear stating that the file is un$no%n. Ignore this dialog "ox and select the 3es "utton. The D.-IT file %ill appear in the file name "oxes for "oth de!ices. The last step is to program the de!ices selecting the Pro,ra /(ain "utton. If successful, a dialog "ox %ill open indicating that "oth de!ices ha!e "een programmed successfull,. Select the +0 "utton to proceed. T(e FPGA (as no) #een pro,ra e'& 2922

;;. /hec$ the operation for the t%o9input A:( GATE and fill in the follo%ing ta"le. *emem"er %e ha!e selected s%itch S C for input A, s%itch S 2 for input - and led )E(C for the output +. Toggle the s%itches for the states sho%n in the ta"le "elo% and fill in the output ", o"ser!ing )E(C. This ta"le should confirm the truth ta"le for a t%o9input A:( gate. S C C C 2 2 S 2 C 2 C 2 )E(C

Par! 8& I ple en!a!ion of !(e OR= NAN%= NOT an' E>"OR GATES usin, Xilin>Ds ISE
2. *epeat steps 29;; in part one of this experiment, "ut this time for a t%o9 input :A:( gate 4:A:(;5 under the logic categor, in the S,m"ols option of the Sources %indo%. +pen a :e% Pro=ect, do not tr, to include a ne% schematic file in the same pro=ect used for the ; input A:( gate. ;. *epeat steps 29;; in part one of this experiment, "ut this time for a t%o9 input +* gate 4+*;5 under the logic categor, in the S,m"ols option of the Sources %indo%.

292;

<. *epeat steps 29;; in part one of this experiment, "ut this time for a t%o9 input exclusi!e9or gate 4X+*;5 under the logic categor, in the S,m"ols option of the Sources %indo%. >. *epeat steps 29;; in part one of this experiment, "ut this time for an in!erter 4I:&5 under the logic categor, in the S,m"ols option of the Sources %indo%. ?se this truth ta"le for the in!erter circuit. S C C 2 )E(C

Par! .& I ple en!a!ion of an AN% Ga!e usin, -ERILOG an' Xilin>Ds ISE
2. *epeat steps 29< of part 2 to open a ne% pro=ect and to select a ne% source. This time select the source as a -ERILOG o'ule instead of a schematic. After selecting the &E*I)+G module, ", selecting the :ext "utton the follo%ing input.output dialog "ox %ill appear. For this part of the pro=ect t%o inputs and one output pins must "e defined. Enter in the port name + and select the direction to "e an output. :ext, define inputs A and - in the port name column and select direction as input. Finall,, select the :ext "utton.

;. /lic$ the finish "utton. A dialog "ox appears and states that the &E*I)+G file does not exist. /lic$ the 3es "utton to create the file. /lic$ the :ext "utton to continue. The Add Source dialog "ox %ill no% appear. This dialog "ox allo%s the user to add an existing source to the pro=ect. For Experiment 82, clic$ the :ext "utton.

292<

<. A pro=ect summar, dialog "ox appears, clic$ the Finish "utton. The ISE %ill no% create the pro=ect as sho%n "elo%. The Sources %indo% sho%s the name of the pro=ect and the name of the top9le!el source gi!en ", the < "ox9 icon next to the &E*I)+G source file name D.!. The design summar, %indo% gi!es a summar, of the pro=ect and the process %indo% lists all of the processes that are a!aila"le. The process %indo% is an important %indo%. It is this %indo% that %ill allo% the user to simulate and implement the FPGA. >. /lic$ on the D.& ta" in the "ottom of the design %indo%. The &E*I)+G source file appears %here the schematic %indo% %as located in part 2. :ote that the module sho%s the defined inputs and outputs that %ere selected pre!iousl,. The s,ntax for &E*I)+G is !er, similar to / programming language. All lines must end in a semicolon, and all comments use either .. or . D.. +ne difference is that all inputs and outputs need t%o definitions. The first defines if the I.+ connection is an input or an output port and the second defines if this input is a I%ireI or a register IregI. For this experiment, onl, %ires %ill "e used. Also, to set an output e7ual to an input the KassignL function must "e used. A summar, of the &E*I)+G s,ntax is gi!en in Appendix E. E. The 'P' s,m"ol is the :+T operator, the MQN s,m"ol is the +* operator, the MRN s,m"ol is the A:( operator and MSN s,m"ol is the EX+* operator. Add the follo%ing lines to the &E*I)+G program after the input and output definitions@ %ire a, ", oT assign o U a R "T

292>

This defines the code re7uired to implement a t%o9input A:( gate module called la"2a@ module la"2a4+, A, -5T output +T input AT input -T %ire A, -, +T assign + U A R -T endmodule F. *epeat Steps 2< through ;C in part one to implement, design, simulate and do%nload this t%o9input A:( gate using the &E*I)+G language. The onl, difference "et%een creating a schematic and using &E*I)+G to design is the source file. here!er the steps refer to the schematic and the D.S/' file, replace the %ording %ith the &E*I)+G and the source file D.&. G. (o%nload the D.-IT file to the FPGA using EXP+*T as defined in step ;2 of part one. &erif, that the t%o9input A:( gate is functioning as designed on the -AS3S "oard as descri"ed in step ;2. H. *epeat steps 29G in part three of this experiment, "ut this time for a t%o9 input :A:( gate 4 P 4A R -55. *efer Appendix E for &E*I)+G s,ntax. B. *epeat steps 29G in part three of this experiment, "ut this time for a t%o9 input +* gate. 2C. *epeat steps 29G in part three of this experiment, "ut this time for a t%o9 input exclusi!e9or gate. 22. *epeat steps 29G in part three of this experiment, "ut this time for an in!erter 4I:&5. ?se this ta"le for the in!erter circuit. S C C 2 )E(C

Par! 3& I ple en!a!ion of a !)o"inpu! fi+e"ou!pu! lo,ic circui!&

2. Implement the t%o9input and fi!e9output logic circuit using schematic capture in the ISE. Simulate the fi!e9outputs for all possi"le inputs. (o%nload the finished design to the -AS3S "oard and !erif, its functionalit, using the follo%ing ta"le.

292E

A C 2 C 2

C C 2 2

)E(C 4S5

)E(24 5

)E(;4X5

)E(<435

)E(>4V5

a b

s w x y z

;. Implement the t%o9input and fi!e9output logic circuit using &E*I)+G in the ISE. Simulate the fi!e9outputs for all possi"le inputs. (o%nload the finished design to the -AS3S "oard and !erif, its functionalit, using the follo%ing ta"le. A C 2 C 2 C C 2 2 )E(C 4S5 )E(24 5 )E(;4X5 )E(<435 )E(>4V5

Repor!: Please follo% the procedures in this la"orator, manual for %riting the report for this
experiment. 2. Summari1e in ,our o%n %ords the steps re7uired to complete Part one of this experiment. Include screen shots 4Alt9Printscreen to place the screen into the clip"oard5 in ,our report to sho% the steps ta$en to complete part one. ;. Include and discuss the simulated results from part one for the t%o9input A:( gate. <. Gi!e the ta"le from part one step ;2 for the t%o9input A:( gate. 292F

>. Sho% the %iring diagram of the A:( gate as connected to S C, S 2 and )E(C include the pin num"ers of the FPGA used. E. *epeat Steps ;, <, and > in the reporting section for the +*, :+T, :A:( and the EX+* gate simulations as implemented in part t%o of this experiment. (o not forget the input9output 4truth5 ta"les for the +*, :A:( and the EX+* gate. The in!erter 4:+T gate5 used a different truth ta"le. F. *epeat Steps ;, <, and > in the reporting section for the A:(, +*, :+T, :A:( and the EX+* gate simulations as implemented in part three of this experiment using the &E*I)+G design language. (o not forget the input9output ta"les for the A:(, +*, :A:( and the EX+* gate. The in!erter used a different ta"le. G. *epeat Steps ;, <, and > in the reporting section for the t%o9input and fi!e9output logic circuit gi!en in part four of this experiment. Include the simulation results and the input9output ta"les for "oth the schematic and &E*I)+G implementations. H. (o not forget the Test Plan and the (esign Specification Plan re7uired for this experiment. *efer to the Introduction section of this manual for details of %hat is expected in this section. Steps in this experiment that are !er, similar can use the same plans.

292G