EX: 3

AIM:

DESIGN AND SIMULATION OF COMBINATIONAL LOGIC CIRCUITS

To write the Verilog HDL code for the design and simulation of multiplexers, decoders, comparators. TOOLS REQUIRED: Xilinx ISE PROCEDURE: 1. In the Xilinx, open a new project and give the file name. 2. Select family name, Verilog HDL module and then click ok. 3. Click the file option to create a new source in Verilog HDL. Type the program. 4. After the program is typed, give file name as .vhd. Select implementation constraint file. 5. Check the syntax of the program by running the synthesis XST. 6. Select simulation constraint file and then run the simulation. 7. Output will be shown in the simulation window.

Multiplexer

Fig Block diagram of 4x1 Multiplexer

Fig Logic diagram of 4x1 Multiplexer

INPUT S0 0 0 1 1 S1 0 1 0 1

OUTPUT O a b c D

Truth table for 4x1 Multiplexer

MUX (4 :1) module multiplexer(a,b,s,y); input a,b,s; output y; wire w1,w2,w3; not(w1,s); and(w2,s,b); and(w3,a,w1); or(y,w2,w3); endmodule

OUTPUT:

Decoder

Fig Block diagram of 2x4 Decoder

Fig Logic Diagram of 2x4 Decoder

A 0 0 1 1

B 0 1 0 1

Output O0 O1 O2 O3

Truth Table for 2x4 Decoder

DECODER 2:4 module decoder(a,b,s1,s2,s3,s4); input a,b; output s1,s2,s3,s4; wire w1,w2; not(w1,a); not(w2,b); and(s1,w1,w2); and(s2,w1,b); and(s3,a,w2); and(s4,a,b); endmodule

OUTPUT:

Comparator:

A=B

2 bit comparator

A>B A<B

Fig Block diagram of comparator

Fig logic Diagram of comparator

A 0 0 1 1

B 0 1 0 1

A=B 1 0 0 1

A>B 0 0 1 0

A<B 0 1 0 0

Truth Table for comparator Comparator module comparator(a,b,x,y,z); input a,b; output x,y,z; wire w1,w2; not(w1,a); not(w2,b); and(x,w1,b); xnor(y,a,b); and(z,w2,a); endmodule

Output:

RESULT:

Thus the Design and Simulation of multiplexer, decoder and comparator was done and its output was verified successfully