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  • Gunma: A Time-to-Digital Converter With Small Circuitry

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    This document summarizes a new time-to-digital converter (TDC) architecture presented by researchers from Gunma University and Musashi Institute of Technology. The proposed TDC uses a novel approach of two interleaved delay lines with different delays (τ1 and τ2) to achieve fine time resolution comparable to existing designs but with significantly reduced circuitry. A prototype 5-bit TDC using the approach was designed, laid out, and measured to confirm the principle works as intended.

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    1D-10

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    This document summarizes a new time-to-digital converter (TDC) architecture presented by researchers from Gunma University and Musashi Institute of Technology. The proposed TDC uses a novel approach of two interleaved delay lines with different delays (τ1 and τ2) to achieve fine time resolution comparable to existing designs but with significantly reduced circuitry. A prototype 5-bit TDC using the approach was designed, laid out, and measured to confirm the principle works as intended.

    Copyright:

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    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    5 views7 pages

    Gunma: A Time-to-Digital Converter With Small Circuitry

    Uploaded by

    t_sreeram
    This document summarizes a new time-to-digital converter (TDC) architecture presented by researchers from Gunma University and Musashi Institute of Technology. The proposed TDC uses a novel approach of two interleaved delay lines with different delays (τ1 and τ2) to achieve fine time resolution comparable to existing designs but with significantly reduced circuitry. A prototype 5-bit TDC using the approach was designed, laid out, and measured to confirm the principle works as intended.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 7

    Gunma University

    ASP-DAC 2009 University LSI Design Contest

    Kobayashi LAB 1

    1D-10

    A Time-to-Digital Converter with Small Circuitry


    Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai Gunma University Masao Hotta Musashi Institute of Technology

    Conventional TDC Architectures


    start stop D0 D1 Encoder 1 start stop DQ 2 D0 1 DQ 1 DQ D2 DQ DQ DQ Start Stop 1LSB = D0=1 D1=1 Depends on CMOS process rule D2=1 D3=0 D4=0 Dout[k] Start Vernier Type 1LSB = 1 - 2 D0=1 Fine time resolution Dout[k] D1=1 D2=0 D3=0

    Basic Type

    Stop

    2 2 D2 D1 Encoder

    New TDC Architecture


    start stop 1 2 D Q
    D0

    3
    Stop

    1 2 D D Q
    D2

    1 2 DQ
    D6

    Start D0=1 D1=1 D2=0 D3=0


    30ps 1

    DQ
    D1

    D D Q
    D4

    DQ
    D8

    DQ
    D3

    DQ
    D7

    DQ
    D9

    Encoder Dout[k]

    1LSB = 1 - 2 Fine time resolution Small circuitry

    CLK

    60ps 1 80ps 100ps

    90ps 1

    20ps 40ps

    2 2

    50ps 70ps

    2 2

    2 2

    Comparison among TDC Architectures

    Basic TDC Vernier Delay Line TDC


    Time resolution # of delay buffers

    Proposed TDC 1-2


    10ps

    2
    20ps

    1-2
    10ps

    19

    38

    19

    1 : 30ps 2 : 20ps Input range : 0 - 200ps

    Proposed TDC Layout and photo


    Delay line1 Delay line2

    Process: TSMC 0.18um CMOS (1P6M) Vdd:1.8V 5bit output time interval:100ps

    850um

    300um

    TDC

    Measurement Results
    4 3 2 1 0 -1 -2 -3 -4 0 0.5 1 1.5 2

    6 DFF Teg measurement

    4 3 2 1 0 -1 -2 -3 -4 0 0.5 1 1.5 2

    Start Stop

    DFF out

    Whole TDC measurement +2n sec output Low output High

    Conclusion

    We have proposed a TDC architecture with small circuitry. We have designed and laid out a prototype TDC. We have measured the prototype TDC Its principle is confirmed.

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