IES200 5 Digital Circuits and Design 2 Laborator y Progra m m e

0 Introduction

Students will work in pairs through a set of design exercises involving combinational and sequential circuits. It should be noted that work will not be confined to the laboratory sessions alone; it is likely to be more efficient to do most of the design work and construction outside the laboratory, using the laboratory for queries, testing and demonstration of working circuits. During the laboratory each student should keep a hardback !"#D $not loose%leaf& '( notebook in which are recorded both the day%to%day laboratory work and any design work done outside the laboratory, the log book should be a complete chronological record. )he entry for each exercise should contain*% a& b& c& d& e& )he design specification. )he design method used, showing and evaluating alternative solutions. )he final choice of design with +ustification. ' diagram giving the logical design and containing all the information $e.g. device types, pin numbers& required to construct the system. ' record of any simulations.

f& )he test procedure used to verify that the system constructed meets the design specification. Sufficient information should be included in the record to make it intelligible at a later date when the detail has been forgotten. )he record should be updated as the work proceeds and once a circuit is functioning correctly a demonstrator will check both the system and the logbook. ,hen the demonstrator is satisfied with both, the logbook will be signed and the next task can be undertaken.

Proposed Timetable and Assessment )here is some flexibility in this laboratory programme, but the following timetable should be used as a guide to ensure you complete all the tasks. Activity -ombinational circuits, multiplexers Synchronous Sequential -ircuits 'synchronous Sequential -ircuits Sessions ., / 2 (, 4, 5 Submission deadline ./.00pm 1onday 2.st !ctober ./.00pm 1onday 3th #ovember ./.00pm 1onday ./th December

'ssessment of the laboratory exercises will be based on the logbook )hey should be handed in for feedback at the end of each activity.

't the start of the laboratory each pair of students will receive a kit of parts $See 'ppendix .& for which they will be responsible. It would be prudent to remove the entire kit at the end of each laboratory period to a more wander proof environment. Students should provide themselves with ,I67 S)6I8876S and -"))76S. 9ogic devices are not indestructible but a few rules will aid their longevity* .. )o reduce the probability of connecting power supplies the wrong way round $usually fatal& use the same orientation for all devices, e.g. pin . bottom left hand corner. Devise your own wiring colour code % it will also assist in fault finding. "se only :cc ;4:. "nused inputs on used gates should be connected either to 0: or $through a .0k resistor& to ;4:, whichever is appropriate. )he same resistor can be used for up to /4 inputs. 1anual inputs can be generated using a switch and pull%up resistor. ;4

/. 2. (.

4.

0 5. 3. Inputs should not be driven below 0 or above :cc. Data books and notes on the use of ))9 devices are available in the laboratory, make yourself thoroughly familiar with them but do not remove them from the lab.

#eatness in paper designs and wiring will improve accuracy and reduce the time and frustration involved in finding and correcting faults. Simulation of the circuit will also assist in producing a correct design. )he results of monitoring the internal nodes of the circuit during the simulation may be used in the construction and fault finding of the circuit. 7ach pair of students should seek to divide and organise their work to produce efficiently designs which work first time.

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1.1

!ercises
"ombinational "ircuits

Design and build circuits to the following specifications using only packages 3(00, 3(0(, 3(.0, 3(/0. Draw <arnaugh maps where appropriate and attempt to use as few packages as possible in your implementations. #. . )esting the following circuits requires many input combinations. =ou may find it convenient to use the outputs from a (%bit counter, 3(.>2, instead of using switches $but see ..(a&. -onstruct the counter circuit on your breadboard and test that it is working correctly. #ote that you may wish to use this circuit for a number of exercises. ' (%input, .%output circuit is defined by truth table ...a ' 0 0 0 0 0 0 0 0 . . . . . . . . 0 0 0 0 . . . . 0 0 0 0 . . . . 0 0 . . 0 0 . . 0 0 . . 0 0 . . D 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . ? . 0 0 0 . 0 . . 0 0 . . . . . .

a&

)able ...a

b& ' -D to 7xcess%2 converter takes a (%bit number, n, 0 n >, and converts it to the (%bit number n ; 2.

x2 x/ x. x0

y2 y/ y. y0

n;2

#ote that a number of D!#@) -'67 conditions exist which can help the simplification. 1.# $ultiple!ers

Implement the circuit in ...a, basing your design on multiplexers.

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Synchronous Se&uential "ircuits Switch Debouncing 1ost mechanical switches AbounceA causing problems if they provide signals to transition%sensitive inputs. -ommon methods of eliminating the problem are shown in $i& and $ii& below*

;4 ;4 6 0 0 0 ;4

$i&

$ii&

$i& B $ii& represent practical solutions to the problem. 7xplain clearly and concisely how circuit $i& operates, including its ability to remove the effects of switch bounce. b& $'., '0& represents a /%bit number which changes synchronously with the -9!-<. Design the circuit to detect the sequence .02/ each time it occurs, i.e. C should go to . for one -9!-< period each time the sequence occurs. Use as few D flip-flops as possible. '. C '0 -9!-<

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Asynchronous Se&uential "ircuits '. and '0 are determined by a /%bit Dray code from a shaft encoder. If the shaft rotation is clockwise* '. '0 E ...... 00%0.%..%.0%00 ..... '. '0 )he output - is to be . if the rotation is clockwise, 0 if anticlockwise. #ote that the direction of rotation can be determined as soon as '. or '0 changes. Fow should the circuit be modified if '. and '0 are the least significant bits from an n%bit Dray codeG

b& -9!-< C 8 )he output, C, is to consist of the first complete positive%going -9!-< pulse following each 0 % . transition on 8. Hor example*%

-9!-<

8 C

8 can change at any time but it can be assumed that transitions in 8 are infrequent relative to those of the clock.

APP ()I* 1 Standard kit readboard 3(00 (/ % #'#D 3(0( Fex Inverter 3(.0 22 % #'#D 3(/0 /( % #'#D 3(.4. I%input multiplexer 3(.42 Dual (%input multiplexer 3(.34 Juad D%flip%flop 3(.>2 inary counter /35( 786!1 Switch and display board APP ()I* # Switch and Display oard Schematic . 2 / / / / / . . . .

# * )his board needs to be connected to the same ;4: and 0: power supply connections as your circuit.