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Chapter 3 Singel Stage Amplifier
Chapter 3 Singel Stage Amplifier
W/L=35.6 um/0.6um
Amplitude of input: 2 mV (peak to peak) Amplitude of output: 19.5 (peak to peak) Av=9.75
Numerical Calculation
Small Signal Gain:
gm=2 mS ro=1/gds=22.288 Kohms RD=6 Kohms AV=-gm(roRD/(ro+RD))=-9.454
Region
Disadvantage of resistively loaded CS: The DC level of Vout is tied to the AV. An increase of RD will increase AV, but at the price of pushing the transistor closer into the triode region.
Useful when tightly controlled resistors are not available, or physically not realizable. Impedance: (Body Effect ignored.)
Example
M1: W/L=4.62 um/0.6um Bias Current: 100 uA gm2=8 mS gds2=35.43 uS gmbs2=100.6 uS RX=1,068 Ohms
Amplitude of input: 2 mV (peak to peak) Amplitude of output: 4.447 mV (peak to peak) Av=2.22
Design Issue
If the bias current is fixed and the dc Vout (VGS) is fixed, then (W/L) of the load is fixed. It maybe difficult to increase Av.
Plot
Amplitude of input: 2 mV (peak to peak) Amplitude of output: 15.24 mV (peak to peak) Av=7.62
Gain Calculation
M1: W/L=6.00 um/0.6um Bias Current: 100 uA Current source: 75 uA gm=2 mS gm2=200 uS gds2=4.69 uS gds=44.8 uS Av=-8.013
ro2 depends on L and ID of a transistor. |VDS2,min=VGS-Vth2| can be reduced by increasing the width of M2. Downside: the DC output voltage is not well-defined.
Spice Example
Amplitude of input: 2 mV (peak to peak) Amplitude of output: 62.92 mV (peak to peak) Av=-31.44
Sensitivty
Even a slight deviation in the gate voltage of PFET is enough to change the output voltage signficantly. E.g. Sensitivity of output voltage around 0.6 V.
Calculation:
W/L for T2: 24.06um/0.6um ro1=22.288 Kohm ro2=53.20 Kohm gm=2 mS Av=-31.41 Ideal Vout=0.6 V Vth2=-0.269 Vod=-0.213 Vb=717.64 mV
Intuition
Vin, ID , VS vin is dropped across RS, thus leading to a smoother variation of ID.
Gain By Inspection
Interpretation: The resistance at the drain Divided by the resistance in the source path
Output Resistance
Homework: Derive the output resistance using the small equivalent circuit
Analysis
Output Resistance