Chapter 1: Introduction 1.

INTRODUCTION

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As the technology is scaling down the demand for low voltage low power efficient circuits that can be implemented in portable battery operated devices has lead to development and use of current mode circuits rather than their voltage mode counterparts. Current-mode circuits are very useful in analog signal processing. A useful function block for high-frequency currentmode applications is a current conveyor. The current conveyor presents an alternative method of implementing analog system which traditionally has been used on op-amp. Current conveyor in many design cases is far better in performance, gain, bandwidth than traditional op-amp [paper !. . OBJECTIVE OF THE THESIS WORK

." Motivation for curr nt !o" fi#t r " $i%n

1.1 MOTIV&TION'

#ith the reduction in the supply voltage and device threshold voltage of C$%& technology, the performance of voltage-mode circuits has been greatly affected which results in a reduced dynamic range, reduced voltage swing, increased propagation delay and low noise margins. The influence of supply voltage reduction on the performance of current-mode circuits, however, is less severe as compared with that of voltage-mode circuits. This is because the design emphasis of current-mode circuits is on branch currents rather than nodal voltages. The usefulness of C$%& current-mode circuits in overcoming the difficulties arising from the reduction of the supply voltage and the increase in the operation speed has received an increasing attention from the industry ['!. Current Conveyors represent the emerging class of high performance analog circuit design based on current-mode approach. They have simple structure, wide bandwidth and capability to operate at low voltages. Current conveyors are unity gain active elements e(hibiting higher linearity, wider dynamic range and better high frequency performance. A current conveyor can function like voltage mode operational amplifier, thus can be used as effective alternative to the same op-amp for analog circuit design [)*)+C$%& CC book ferri,guerrini!

., CONTRIBUTION &ND OR(&NI)&TION OF THESIS $ain contributions of this thesis are .esign and simulation of C$%& *C%s by the use of two circuit techniques.

Chapter 1: Introduction
voltage-frequency plot. &election of *C% for pacemaker application. .esign of a low frequency *C% for pacemaker application. The thesis report is organi/ed into si( chapters. The chapter wise detail is given below-

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Comparative study of C$%& *C%s, based on their linearity, which is observed from

C*a+t r 1' 0n this chapter, the ob1ective of the thesis work is presented .The .esign $ethodology and 2.A Tools used. C*a+t r ,' This chapter presents introduction of pacemaker and the need of *C% in it. C*a+t r -- 0n this chapter, basic theory of %scillators and its types are discussed. C*a+t r .- 0n this chapter, )iterature 3eview is presented. C*a+t r /' 0n this chapter, brief introduction to the $24T%3 53A+60C& tool is presented. C*a+t r 0' This chapter discusses the design and comparison of C$%& *C%s with results of the schematic and layout simulations. 0t also presents the design of *C% for pacemaker application. C*a+t r 1' This chapter presents the conclusion of the work done and future scope. 1.- DESI(N METHODO2O(3 &ND ED& TOO2S USED The design flow shown in figure is typically used by a C$%& 0C designer .0n any design, specifications are written first. &pecifications describe abstractly the circuit inputs, outputs, interfaces and functionality. The C$%& circuit design process consists of defining circuit specification, hand calculations and schematics. After that simulations of circuit is performed and checkout whether it meets design specification. 0f the circuit meets specification then the layout engineer makes layout of circuit. 0t is e(tremely important that the engineer be able to layout a chip and understands the parasitics involved in the layout. Then circuit will be again simulated with parasitics. This step is called post layout simulation. And again checkout whether it meets design specification. 0f the circuit meets specification finally sent for the fabrication and testing. Again specification is checkout and last sent for the mask production.

Chapter 1: Introduction

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7igure - 7low chart for the C$%& 0C design process THE SOFTW&RE &ND ED& TOO2S USED %perating &ystem Tools .esign Architect 0C &tation #indows, )inu( $24T%3 53A+60C& 2).% &+0C2 &0$8)AT%3 &.), .3C, )*& 9 +2:

The Current conveyors are unity gain active element e(hibiting high linearity, wide dynamic range and high frequency performance than their voltage mode counterparts.

Chapter 1: Introduction
A current-mode approach is not 1ust restricted to current processing, but also offers certain important advantages when interfaced to voltage-mode circuits.

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1. INTRODUCTION
Current-mode circuits are very useful in analog signal processing. A useful function block for high-frequency current-mode applications is a current conveyor. The current conveyor presents an alternative method of implementing analog system which traditionally has been used on opamp. Current conveyor in many design cases is far better in performance, gain, bandwidth than traditional op-amp.

1.2 4ROB2EM ST&TEMENT'

The current-mode design technique is a good alternative for the high performance analog circuit design as it offers voltage independent high bandwidth. 0n current-mode design, the stress is more on the current levels for the operation of the circuits and the voltage levels at various nodes are immaterial. 0n voltage-mode circuits ;*$Cs<, such as operational amplifiers ;op amp<, the performance of the circuit is determined in terms of voltage levels at various nodes including the input and the output nodes. =ut all these circuits suffer from the following disadvantages1. %utput voltage cannot change instantly when there is a sudden change in the input voltage due to stray and other circuit capacitances. 2. =andwidth of the op amp based circuits is usually low because of finite unity gain bandwidth. 3. &lew rate is dependent on the time constants associated with the circuit. 4. Circuits do not have high voltage swings. 5. 3equire higher supply voltages for better signal-to-noise ratio. Therefore, *$Cs are not suitable for high frequency applications. #hen the signal is conveyed as a current, the voltages in $%& transistor circuits are proportional to the square root of the signal, if the devices are assumed to be operating in saturation region. Therefore, a compression of voltage signal swing and a reduction of supply voltage are possible. 6owever, as a result of the device mismatches, this non-linear operation may generate an e(cessive amount of distortion and cannot be used for the applications where high linearity is required. Thus, lineari/ation techniques are utili/ed in current-mode circuits to reduce the nonlinearity of the transistor transconductance and in this case the voltage signal swing is also not reduced. 1.- OBJECTIVE OF DISSERT&TION'

Chapter 1: Introduction

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The ob1ective of the proposed dissertation is to design high gain, high bandwidth opamp using current conveyor ;CC-00< configuration. The designed op-amp is then compared with conventional op-amp using voltage mode approach, the comparison parameters are slew rate, C$33, gain, bandwidth and propagation delay. The proposed CC-00 based op-amp is then used to design instrumentation amplifier to achieve better C$33 and high frequency performance.